National Semiconductor LM3146 Technical data

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LM3146 High Voltage Transistor Array

LM3146 High Voltage Transistor Array

February 1995

General Description

The LM3146 consists of five high voltage general purpose
silicon NPN transistors on a common monolithic substrate.
Two of the transistors are internally connected to form a
differentially-connected pair. The transistors are well suited
to a wide variety of applications in low power system in the
dc through VHF range. They may be used as discrete tran­sistors in conventional circuits however, in addition, they
provide the very significant inherent integrated circuit ad­vantages of close electrical and thermal matching. The
LM3146 is supplied in a 14-lead molded dual-in-line pack­age for applications requiring only a limited temperature
range.

Connection Diagram

Dual-In-Line and Small Outline Packages

Features

Y

High voltage matched pairs of transistors, VBEmatched

g

5 mV, input offset current 2 mA max at I

Y

Five general purpose monolithic transistors

Y

Operation from dc to 120 MHz

Y

Wide operating current range

Y

Low noise figure 3.2 dB typ at 1 kHz

e

1mA

C

Applications

Y

General use in all types of signal processing systems
operating anywhere in the frequency range from dc to
VHF

Y

Custom designed differential amplifiers

Y

Temperature compensated amplifiers

Top View

TL/H/7959– 1

Order Number LM3146M or LM3146N

See NS Package Number M14A or N14A

C

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

TL/H/7959

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

CEO

b

b

LM3146 Units

30 V

40 V

50 mA

40 toa85§C

65 toa150§C

Power Dissipation: Each transistor

e

T

25§Cto55§C 300 mW

A

l

T

55§C Derate at 6.67 mW/§C

A

Power Dissipation: Total Package

e

T

25§C 500 mW

A

l

T

25§C Derate at 6.67 mW/§C

A

Collector to Emitter Voltage, V

Collector to Base Voltage, V

CBO

Collector to Substrate Voltage,

V

(Note 1) 40 V

CIO

Emitter to Base Voltage, V

(Note 2) 5 V

Collector to Current, I

EBO

C

Operating Temperature Range

Storage Temperature Range

Soldering Information

Dual-In-Line Package

Soldering (10 seconds) 260

Small Outline Package

Vapor Phase (60 seconds) 215
Infrared (15 seconds) 220

See AN-450 ‘‘Surface Mounting Methods and Their Effect
on Product Reliability’’ for other methods of soldering sur­face mount devices.

C

§

C

§

C

§

DC Electrical Characteristics T

Symbol Parameter Conditions

e

25§C

A

Limits

Units

Min Typ Max

V

(BR)CBO

V

(BR)CEO

V

(BR)CIO

V

(BR)EBO

I

CBO

I

CEO

h

FE

IB1–I

B2

V

BE

V

BE1–VBE2

Collector to Base Breakdown Voltage I

Collector to Emitter Breakdown Voltage I

Collector to Substrate Breakdown I
Voltage I

Emitter to Base Breakdown Voltage
(Note 2)

Collector Cutoff Current V

Collector Cutoff Current V

Static Forward Current Transfer I
Ratio (Static Beta) I

Input Offset Current for Matched I
Pair Q1 and Q2 V

Base to Emitter Voltage I

Magnitude of Input Offset Voltage V
for Differential Pair

DVBE/DT Temperature Coefficient of Base V

to Emitter Voltage

V

CE(SAT)

Collector to Emitter Saturation I
Voltage

DV10/DT Temperature Coefficient of Input I

Offset Voltage

Note 1: The collector of each transistor is isolated from the substrate by an integral diode. The substrate must be connected to a voltage which is more negative
than any collector voltage in order to maintain isolation between transistors and provide normal transistor action. To avoid undesired coupling between transistors,
the substrate terminal should be maintained at either dc or signal (ac) ground. A suitable bypass capacitor can be used to establish a signal ground.

Note 2: If the transistors are forced into zener breakdown (V

Note 3: See curve.

(BR)EBO

e

10 mA, I

C

e

1 mA, I

C

e

CI

e

0

E

e

I

0, I

C

e

CB

e

CE

e

10 mA, V

C

e

1 mA, V

C

e

I

10 mA, V

C

e

C1

e

CE

e

1 mA, V

C

e

CE

e

CE

e

10 mA, I

C

e

1 mA, V

C

), degradation of forward transfer current ratio (hFE) can occur.

e

04072 V

E

e

03056 V

B

10 mA, I

e

0,

B

e

10 mA57 V

E

e

10V, I

10V, I

1

C2

5V

5V, I

5V, I

0 0.002 100 nA

E

e

0 (Note 3) 5 mA

B

e

CE

e

5V 30 100

CE

e

CE

e

1 mA,

e

3V 0.63 0.73 0.83 V

CE

e

1mA

E

e

1mA

E

e

1mA

B

e

5V

CE

40 72 V

5V 85

5V 90

0.3 2 mA

0.48 5 mV

b

1.9 mV/§C

0.33 V

1.1 mV/

C

§

2

AC Electrical Characteristics

Symbol Parameter Conditions

Min Typ Max

NF Low Frequency Noise Figure fe1 kHz, V

e

I

100 mA, R

C

f

T

C

EB

C

CB

C

CI

Gain Bandwidth Product V

Emitter to Base Capacitance V

Collector to Base Capacitance V

Collector to Substrate Capacitance V

CE

EB

CB

CI

e

e

e

e

e

5V,

CE

e

1kX

S

e

5V, I

3 mA 300 500 MHz

C

e

5V, I

0 0.70 pF

E

e

5V, I

0 0.37 pF

C

e

5V, I

0 2.2 pF

C

Low Frequency, Small Signal Equivalent Circuit Characteristics

e

h

fe

h

ie

h

oe

h

re

Forward Current Transfer Ratio fe1 kHz, V

Short Circuit Input Impedance fe1 kHz, V

Open Circuit Output Impedance fe1 kHz, V

Open Circuit Reverse Voltage fe1 kHz, V
Transfer Ratio I

e

1mA

C

CE

CE

CE

CE

e

3V, I

1 mA 100

C

e

e

3V, I

1 mA 3.5 kX

C

e

e

3V, I

1 mA 15.6 mmho

C

e

3V, 1.8 x 10

Admittance Characteristics

e

Y

fe

Y

ie

Y

oe

Y

re

Note 1: The collector of each transistor is isolated from the substrate by an integral diode. The substrate must be connected to a voltage which is more negative
than any collector voltage in order to maintain isolation between transistors and provide normal transistor action. To avoid undesired coupling between transistors,
the substrate terminal should be maintained at either dc or signal (ac) ground. A suitable bypass capacitor can be used to establish a signal ground.

Note 2: If the transistors are forced into zener breakdown (V

Note 3: See curve.

Forward Transfer Admittance fe1 MHz, V

Input Admittance fe1 MHz, V

Output Admittance fe1 MHz, V

Reverse Transfer Admittance fe1 MHz, V

), degradation of forward transfer current ratio (hFE) can occur.

(BR)EBO

CE

CE

CE

CE

e

3V, I

1mA 31bj 1.5 mmho

C

e

e

3V, I

1 mA 0.3aj 0.04 mmho

C

e

e

3V, I

1 mA 0.001aj 0.03 mmho

C

e

e

3V, I

1 mA (Note 3) mmho

C

Limits

3.25 dB

b

4

Units

3

Typical Performance Characteristics

vs TAfor

I

CEO

Any Transistor

vs TAfor

V

BE

Any Transistor

I

vs TAfor

CBO

Any Transistor

V
for Any Transistor

CE(SAT)

vs I

C

hFEvs ICfor
Any Transistor

IIOvs IC(Q1 and Q2)

and VIOvs

V

vs TAfor Q1 and Q2 IEfor Q1 and Q2

V

IO

BE

@

NF vs I

e

R

C

500X

S

TL/H/7959– 2

4

Typical Performance Characteristics (Continued)

@

e

R

NF vs I

C

1kX NF vs I

S

Yfevs f Yievs f Yoevs f

e

e

R

C

10 kX hfe,hie,hoe,hrevs I

S

C

vs f fTvs I

Y

re

C

EB,CCB,CCI

C

Voltage

vs Bias

TL/H/7959– 3

5

Physical Dimensions inches (millimeters)

LM3146 High Voltage Transistor Array

SO Package (M)

Order Number LM3146M

NS Package Number M14A

Molded Dual-In-Line Package (N)

Order Number LM3146N

NS Package Number N14A

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failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

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a

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a

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