National Semiconductor LM2524D, LM3524D Technical data

LM2524D/LM3524D Regulating Pulse Width Modulator

General Description

The LM3524D family is an improved version of the industry standard LM3524. It has improved specifications and additional features yet is pin for pin compatible with existing 3524 families. New features reduce the need for additional external circuitry often required in the original version.

The LM3524D has a ±1% precision 5V reference. The current carrying capability of the output drive transistors has been raised to 200 mA while reducing V breakdown to 60V. The common mode voltage range of the error-amp has been raised to 5.5V to eliminate the need for a resistive divider from the 5V reference.

In the LM3524D the circuit bias line has been isolated from the shut-down pin. This prevents the oscillator pulse amplitude and frequency from being disturbed by shut-down. Also at high frequencies (≃300 kHz) the max. duty cycle per output has been improved to 44% compared to 35% max. duty cycle in other 3524s.

In addition, the LM3524D can now be synchronized externally, through pin 3. Also a latch has been added to insure one

and increasing V

CEsat

pulse per period even in noisy environments. The LM3524D includes double pulse suppression logic that insures when a shut-down condition is removed the state of the T-flip-flop will change only after the first clock pulse has arrived. This feature prevents the same output from being pulsed twice in a row, thus reducing the possibility of core saturation in push-pull designs.

Features

CE

Fully interchangeable with standard LM3524 family

■

±1% precision 5V reference with thermal shut-down

■

Output current to 200 mA DC

■

60V output capability

■

Wide common mode input range for error-amp

■

One pulse per period (noise suppression)

■

Improved max. duty cycle at high frequencies

■

Double pulse suppression

■

Synchronize through pin 3

■

LM2524D/LM3524D Regulating Pulse Width Modulator

May 2, 2008

Connection Diagram

Order Number LM2524DN or LM3524DN

Top View

See NS Package Number N16E

Order Number LM3524DM

See NS Package Number M16A

865002

Block Diagram

LM2524D/LM3524D

865001

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LM2524D/LM3524D

Absolute Maximum Ratings (Note 5)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage 40V Collector Supply Voltage (LM2524D) 55V (LM3524D) 40V Output Current DC (each) 200 mA

Internal Power Dissipation 1W Operating Junction Temperature Range (Note 2) LM2524D −40°C to +125°C LM3524D 0°C to +125°C Maximum Junction Temperature 150° Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering 4 sec.) M, N Pkg. 260°C

Oscillator Charging Current (Pin 7) 5 mA

Electrical Characteristics

(Note 1)

LM2524D LM3524D

Symbol Parameter Conditions

Typ Limit Limit Typ Limit Limit

REFERENCE SECTION

V

REF

Output Voltage

V

RLine

RLoad

Line Regulation VIN = 8V to 40V 10 15 30 10 25 50 mV

Load Regulation IL = 0 mA to 20 mA 10 15 25 10 25 50 mV

Ripple Rejection f = 120 Hz 66 66 dB

Tested Design Tested Design

(Note 3) (Note 4)

4.85 4.80

5

5.15 5.20

(Note 3) (Note 4)

4.75 V

5

5.25 V

Units

Min

Max

I

OS

Short Circuit V

= 0 25 25 mA Min

REF

Current 50 50

180 200 mA Max

N

O

Output Noise

10 Hz ≤ f ≤ 10 kHz

Long Term TA = 125°C

40 100 40 100

20

Stability

OSCILLATOR SECTION

f

OSC

Max. Freq.

RT = 1k, CT = 0.001 μF

550

500 350

(Note 7)

f

OSC

Initial

RT = 5.6k, CT = 0.01 μF

17.5 17.5 kHz

Accuracy (Note 7) 20 20

22.5 22.5 kHz

RT = 2.7k, CT = 0.01 μF

34 30 kHz

(Note 7) 38 38

42 46 kHz

Δf

OSC

with V

Δf

OSC

Freq. Change VIN = 8 to 40V

IN

0.5 1

Freq. Change TA = −55°C to +125°C

0.5 1.0

with Temp. at 20 kHz RT = 5.6k, 5 5 %

V

OSC

Output Amplitude

CT = 0.01 μF

RT = 5.6k, CT = 0.01 μF

3 2.4

(Pin 3) (Note 8)

t

PW

Output Pulse

RT = 5.6k, CT = 0.01 μF

0.5 1.5

Width (Pin 3)

Sawtooth Peak

RT = 5.6k, CT = 0.01 μF

3.4 3.6 3.8

3.8

Voltage

μV

rms Max

mV/kHr

kHz

%

Max

V

Min

μs

Max

V

Max

Min

Max

Min

Max

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LM2524D LM3524D

Symbol Parameter Conditions

Tested Design Tested Design

Typ Limit Limit Typ Limit Limit

Sawtooth Valley

RT = 5.6k, CT = 0.01 μF

(Note 3) (Note 4)

1.1 0.8 0.6

(Note 3) (Note 4)

0.6

Voltage

LM2524D/LM3524D

ERROR-AMP SECTION

V

IO

Input Offset VCM = 2.5V

2 8 10 2 10

mV

Voltage

I

IB

Input Bias VCM = 2.5V

1 8 10 1 10

Current

I

IO

Input Offset VCM = 2.5V

0.5 1.0 1 0.5 1

Current

I

COSI

Compensation V

IN(I)

− V

= 150 mV 65 65

IN(NI)

Current (Sink) 95 95

125 125

I

COSO

Compensation V

IN(NI)

− V

= 150 mV −125 −125

IN(I)

Current (Source) −95 −95

−65 −65

A

VOL

Open Loop Gain

RL = ∞, VCM = 2.5 V

80 74 60 80 70 60 dB

VCMR Common Mode 1.5 1.4 1.5 V

Input Voltage

5.5 5.4 5.5 V

Range

CMRR Common Mode

90 80

dB

Rejection Ratio

G

BW

Unity Gain A

= 0 dB, VCM = 2.5V

VOL

3

2

Bandwidth

V

O

Output Voltage

RL = ∞

0.5 0.5 V

Swing 5.5 5.5 V

PSRR Power Supply VIN = 8 to 40V

80

70 80 65

db

Rejection Ratio

COMPARATOR SECTION

V

COMPZ

Minimum Duty Pin 9 = 0.8V,

Cycle

[RT = 5.6k, CT = 0.01 μF]

Maximum Duty Pin 9 = 3.9V,

Cycle

[RT = 5.6k, CT = 0.01 μF]

Maximum Duty Pin 9 = 3.9V,

Cycle

[RT = 1k, CT = 0.001 μF]

Input Threshold Zero Duty Cycle

0 0

49 45

44 35

1

0 0

49 45

44 35

1

%

(Pin 9)

V

COMPM

Input Threshold Maximum Duty Cycle

3.5

(Pin 9)

I

IB

Input Bias

−1

Current

CURRENT LIMIT SECTION

V

SEN

Sense Voltage

V

(Pin 2)

− V

(Pin 1)

≥

180 180 mV

150 mV 200 200

220 220 mV

TC-V

sense

Sense Voltage T.C. 0.2 0.2 mV/°C

Units

V

Min

Max

μA

Max

μA

Max

μA

Min

μA

Max

μA

Min

μA

Max

Min

Max

Min

MHz

Min

Max

Min

Max

Min

V

μA

Min

Max

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LM2524D LM3524D

Symbol Parameter Conditions

Tested Design Tested Design

Units

Typ Limit Limit Typ Limit Limit

(Note 3) (Note 4)

Common Mode −0.7 −0.7 V

Voltage Range V5 − V4 = 300 mV 1 1 V

SHUT DOWN SECTION

V

SD

High Input

V

(Pin 2)

− V

(Pin 1)

≥

1

0.5

0.5 V

1

Voltage 150 mV 1.5 1.5 V

I

SD

High Input I

(pin 10)

1

mA

Current

OUTPUT SECTION (EACH OUTPUT)

V

CES

Collector Emitter

IC ≤ 100 μA

55

40

V

Voltage Breakdown

I

CES

V

CESAT

V

EO

Collector Leakage VCE = 60V

Current

VCE = 55V 0.1 50

VCE = 40V 0.1 50

Saturation IE = 20 mA 0.2 0.5 0.2 0.7

Voltage

Emitter Output IE = 50 mA

IE = 200 mA 1.5 2.2 1.5 2.5

18 17

μA

V

Voltage

t

R

Rise Time VIN = 20V,

IE = −250 μA

200 200 ns

RC = 2k

t

F

Fall Time RC = 2k 100 100 ns

SUPPLY CHARACTERISTICS SECTION

V

IN

Input Voltage After Turn-on 8 8 V

Range 40 40 V

T Thermal Shutdown (Note 2) 160 160 °C

Temp.

I

IN

Note 1: Unless otherwise stated, these specifications apply for TA = TJ = 25°C. Boldface numbers apply over the rated temperature range: LM2524D is −40° to 85°C and LM3524D is 0°C to 70°C. VIN = 20V and f

Note 2: For operation at elevated temperatures, devices in the N package must be derated based on a thermal resistance of 86°C/W, junction to ambient. Devices in the M package must be derated at 125°C/W, junction to ambient.

Note 3: Tested limits are guaranteed and 100% tested in production.

Note 4: Design limits are guaranteed (but not 100% production tested) over the indicated temperature and supply voltage range. These limits are not used to

calculate outgoing quality level.

Note 5: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its rated operating conditions.

Note 6: Pins 1, 4, 7, 8, 11, and 14 are grounded; Pin 2 = 2V. All other inputs and outputs open.

Note 7: The value of a Ct capacitor can vary with frequency. Careful selection of this capacitor must be made for high frequency operation. Polystyrene was used

in this test. NPO ceramic or polypropylene can also be used.

Note 8: OSC amplitude is measured open circuit. Available current is limited to 1 mA so care must be exercised to limit capacitive loading of fast pulses.

Stand By Current VIN = 40V (Note 6) 5 10 5 10 mA

= 20 kHz.

OSC

LM2524D/LM3524D

Min

Max

Min

Max

Min

Max

Min

Max

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Typical Performance Characteristics

LM2524D/LM3524D

Switching Transistor Peak Output Current

vs Temperature

Maximum & Minimum Duty Cycle Threshold

Voltage

Maximum Average Power

Dissipation (N, M Packages)

865029

865028

Output Transistor

Saturation Voltage

Output Transistor Emitter

Voltage

865030

865032

865031

Reference Transistor Peak Output Current

865033

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LM2524D/LM3524D

Standby Current

vs Voltage

Current Limit Sense Voltage

865034

Standby Current

vs Temperature

865035

Test Circuit

865036

865004

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