National Semiconductor LM1276 Technical data

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LM1276 150 MHz I

C Compatible RGB Preamplifier with Internal 512 Character OSD ROM, 512 Character RAM and 4 DACs

General Description

The LM1276 pre-amp is an integrated CMOS CRT preamp with an integrated Hi-Brite Window generator, 512 Character OSD generator, and an auto size measurement circuit. It has

C compatible interface, which allows control of all the

an I parameters necessary to directly setup and adjust the gain and contrast in the CRT display. Brightness and bias can be controlled through the DAC outputs, which are well matched to the LM2479 and LM2480 integrated bias clamp ICs. The LM1276 preamp is also designed to be compatible with the LM247x high gain driver family.

Black level clamping of the video signal is carried out directly on the AC coupled input signal into the high impedance preamplifier input, thus eliminating the need for additional clamp capacitors. Horizontal and vertical blanking of the outputs is provided. Vertical blanking is optional and its duration is register programmable.

The IC is packaged in an industry standard 28-lead narrow DIP molded plastic package.

Features

n Integrated Hi-Brite Window Generator operation

independent of the Microcontroller.

n Programmable Video Emphasis Control. n 8 Programmable Hi-Brite Windows. n Hi-Brite Enhancement on full screen, window only, or

outside of windows.

n Fully addressable 512 Character OSD. n Internal 512 character OSD ROM usable as either (a)

384 2-color plus 128 4-color characters, (b) 640 2-color characters, or (c) some combination in between.

n Internal 512 character RAM.

May 2005

n Enhanced I

allow versatile Page RAM access.

n OSD Window Fade In/Fade Out. n OSD Variable Tone Transparency. n 3 Bit OSD Contrast. n Video Data detection for Auto Centering & Sizing. n 2 Bit Adjustable Burn-in screen Mode with no video

input.

n 4 DAC outputs (8-bit resolution) for bus controlled CRT

bias and brightness.

n Spot killer, which blanks the video outputs when V

falls below the specified threshold.

n Suitable for use with discrete or integrated clamp, with

software configurable brightness mixer.

n Programmable ABL Onset for Multi-Limit Applications. n 4-Bit Programmable start position for internal Horizontal

Blanking.

n Horizontal blanking and OSD synchronization directly

from deflection signals. The blanking can be disabled, if desired.

n Vertical blanking and OSD synchronization directly from

sync signals. The blanking width is register programmable and can be disabled, if desired.

n Power Saving Mode with 65% power reduction. n Matched to LM246x, LM247x drivers, and LM2479/80

bias IC’s.

C compatible microcontroller interface to

Applications

n Ideal preamplifier IC for total Hi-Brite Solution. n 17" and 19” bus controlled monitors with OSD. n Low cost systems with LM247x drivers.

Character RAM and 4 DACs

LM1276 150 MHz I

C Compatible RGB Preamplifier with Internal 512 Character OSD ROM, 512

Internal Block Diagram

LM1276

FIGURE 1. Block Diagram

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20096961

Internal Block Diagram (Continued)

LM1276

FIGURE 2. LM1276 Pinout

Order Number LM1276AAA/NA

See NS Package Number N28D

20096962

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Absolute Maximum Ratings (Notes 1,

LM1276

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage V

, Pins 10, 14, 17,

Thermal Resistance to Case (θ

Junction Temperature (T

) 150˚C

) 32˚C/W

ESD Susceptibility (Note 4) 3.0 kV

ESD Machine Model (Note 13) 350V

Storage Temperature −65˚C to +150˚C

Lead Temperature (Soldering, 10 sec.) 265˚C

and 22 6.0V

Peak Video DC Output Source Current

(Any One Amp) Pins 23, 24 or 25 1.5 mA

Voltage at Any Input Pin (V

Video Inputs (pk-pk) 0.0V ≤ V

Thermal Resistance to Ambient (θ

Power Dissipation (P

) –0.5V ≤ VIN≤ VCC+0.5V

) 51˚C/W

)

≤ 1.2V

Operating Ratings (Note 2)

Temperature Range 0˚C to +70˚C

Supply Voltage V

Video Inputs (pk-pk) 0.0V ≤ V

4.75V ≤ VCC≤ 5.25V

(Above 25˚C Derate Based

and TJ) 2.4W

on θ

Video Signal Electrical Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.70 V

P-P,VABL=VCC,CL

numbers refer to the definitions in Table 1. See (Note 7) for Min and Max parameters and (Note 6) for Typicals.

Symbol Parameter Conditions Min Typ Max Units

Supply Current Test Setting 1, both supplies, no

output loading. See (Note 8).

S-PS

O BLK A-B

Supply Current, Power Save

Mode

Typical Video Black Level

Test Setting 1, both supplies, no output loading. See (Note 8).

No AC Input Signal Difference between Normal Video and Hi-Brite Video.

O BLK A-B, CH-CH

Typical Channel to Channel

No AC Input Signal Video Black Level Difference between Normal Video and Hi-Brite Video.

O BLK

O BLK STEP

Active Video Black Level Output Voltage

Active Video Black Level Step

Test Setting 4, no AC input signal, DC

offset register (0x8438) set to 0xD5.

Test Setting 4, no AC input signal. Size

Max Maximum Video Output Voltage Test Setting 3, Video in = 0.70 V

LE Linearity Error Test Setting 4, staircase input signal

(see (Note 9)).

Video Rise Time (Note 5), 10% to 90%, Test Setting 4,

AC input signal.

Rising Edge Overshoot (Note 5), Test Setting 4, AC input

signal.

Video Fall Time (Note 5), 90% to 10%, Test Setting 4,

AC input signal.

Falling Edge Overshoot (Note 5), Test Setting 4, AC input

signal.

BW Channel Bandwidth (−3 dB) (Note 5), Test Setting 4, AC input

signal.

10 kHz Video Amplifier 10 kHz Isolation (Note 14), Test Setting 8. −60 dB

SEP

10 MHz Video Amplifier 10 MHz Isolation (Note 14), Test Setting 8. −50 dB

SEP

Max Maximum Voltage Gain Test Setting 8, AC input signal. 3.8 4.1 V/V

C-50% Contrast Attenuation@50% Test Setting 5, AC input signal. −5.2 dB

Min/AVMax Maximum Contrast Attenuation

Test Setting 2, AC input signal. (dB)

= 8 pF, Video Outputs = 2.0 V

220 300 mA

55 85 mA

-50 0 TBD VDC

-50 0 50 VDC

1.2 VDC

100 mVDC

P-P

4.0 4.3 V

3.1 ns

2.9 ns

150 MHz

−12 dB

. Setting

P-P

≤ 1.0V

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Video Signal Electrical Characteristics (Continued)

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.70 V

P-P,VABL=VCC,CL

numbers refer to the definitions in Table 1. See (Note 7) for Min and Max parameters and (Note 6) for Typicals.

Symbol Parameter Conditions Min Typ Max Units

G-50% Gain Attenuation@50% Test Setting 6, AC input signal. −4.0 dB

G-Min Maximum Gain Attenuation Test Setting 7, AC input signal. −11 dB

Match Maximum Gain Match between

Test Setting 3, AC input signal.

Channels

Track Gain Change between Channels Tracking when changing from Test

Setting 8 to Test Setting 5. See (Note

11).

Vid

Threshold

TH ABL Control Range Upper Limit (Note 12), Test Setting 4, AC input

ABL

Video Threshold Normal Operation 80 mV

signal.

Range ABL Gain Reduction Range (Note 12), Test Setting 4, AC input

ABL

signal.

V 3.5/AV Max

V 2.0/AV Max

Max ABL Input Current Sink Capability (Note 12), Test Setting 4, AC input

ABL

ABL Gain Reduction at 3.5V (Note 12), Test Setting 4, AC input

signal. V

ABL

= 3.5V

ABL Gain Reduction at 2.0V (Note 12), Test Setting 4, AC input

signal. V

ABL

= 2.0V

signal.

Max Maximum ABL Input Voltage

ABL

during Clamping

(Note 12), Test Setting 4, AC input signal. I

ABL=IABL

MAX

AVABL Track ABL Gain Tracking Error (Note 9), Test Setting 4, 0.7 V

input signal, ABL voltage set to 4.5V and 2.5V.

Minimum Input Resistance (pins

Test Setting 4.

5, 6, 7)

= 8 pF, Video Outputs = 2.0 V

0.5 dB

4.8 V

2.8 V

−2 dB

−12 dB

P-P

20 MΩ

. Setting

P-P

2.5 mA

0.1

5.0 %

LM1276

OSD Electrical Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5.0V. See (Note 7) for Min and Max parameters and (Note 6) for Typicals.

Symbol Parameter Conditions Min Typ Max Units

OSDHIGH

∆V

max Maximum OSD Level with OSD

Contrast 111

110 Maximum OSD Level with OSD

Contrast 110

101 Maximum OSD Level with OSD

Contrast 101

100 Maximum OSD Level with OSD

Contrast 100

011 Maximum OSD Level with OSD

Contrast 011

010 Maximum OSD Level with OSD

Contrast 010

001 Maximum OSD Level with OSD

Contrast 001

000 Maximum OSD Level with OSD

Contrast 000

(Black) Difference between OSD Black

OSD

Level and Video Black Level (same channel)

Palette Set at 111, OSD Contrast = 111, Test Setting 3

Palette Set at 111, OSD Contrast = 110, Test Setting 3

Palette Set at 111, OSD Contrast = 01, Test Setting 3

Palette Set at 111, OSD Contrast = 100, Test Setting 3

Palette Set at 111, OSD Contrast = 011, Test Setting 3

Palette Set at 111, OSD Contrast = 010, Test Setting 3

Palette Set at 111, OSD Contrast = 001, Test Setting 3

Palette Set at 111, OSD Contrast = 000, Test Setting 3

3.02 V

2.91 V

2.79 V

2.67 V

2.55 V

2.43 V

2.32 V

2.20 V

130 mV

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OSD Electrical Characteristics (Continued)

Unless otherwise noted: TA= 25˚C, VCC= +5.0V. See (Note 7) for Min and Max parameters and (Note 6) for Typicals.

LM1276

Symbol Parameter Conditions Min Typ Max Units

∆V

OSD-black

(Track)

(White) Output Match between Channels Palette Set at 111, OSD Contrast =

∆V

OSD

Difference between OSD Black Level and Video Black Level between any 2 channels

11, Maximum difference between R,

115 mV

G and B

(Track) Output Variation between Channels OSD contrast varied from max to

OSD-out

min

DAC Output Electrical Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.7V, V

ABL=VCC,CL

for Min and Max parameters and (Note 6) for Typicals. DAC parameters apply to all 4 DACs.

Symbol Parameter Conditions Min Typ Max Units

Min DAC

Max DAC

Mode 00

Max DAC

Mode 01

∆V

Max DAC

(Temp)

∆V

Max DAC(VCC

Min Output Voltage of DAC Register Value = 0x00 0.5 0.7 V

Max Output Voltage of DAC Register Value = 0xFF,

DCF[1:0] = 00b

Max Output Voltage of DAC in DCF Mode 01

DAC Output Voltage Variation

DCF[1:0] = 01b

<T<

70˚C ambient

with Temperature

) DAC Output Voltage Variation

with V

VCCvaried from 4.75V to 5.25V, DAC

Linearity Linearity of DAC over its Range 5 %

Monotonicity Monotonicity of the DAC

Excluding Dead Zones

MAX

Max Load Current −1.0 1.0 mA

= 8 pF, Video Outputs = 2.0 V

3.7 4.2 V

1.85 2.35 V

0.5 mV/˚C

50 mV

0.5 LSB

. See (Note 7)

P-P

System Interface Signal Characteristics

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.7V, V

ABL=VCC,CL

for Min and Max parameters and (Note 6) for Typicals. DAC parameters apply to all 4 DACs.

Symbol Parameter Conditions Min Typ Max Units

VTH+

VFLYBACK Positive Switching

Vertical Blanking triggered

Guarantee

SPOT

Ref

(SCL, SDA) Logic Low Input Voltage −0.5 1.5 V

(SCL, SDA) Logic High Input Voltage

Spot Killer Voltage (Note 17), VCCAdjusted to Activate 3.4 3.9 4.3 V

Output Voltage (pin 2) 1.25 1.45 1.65 V

Ref

IL(SCL, SDA) Logic Low Input Current SDA or SCL, Input Voltage = 0.4V

(SCL, SDA) Logic High Input Voltage SDA or SCL, Input Voltage = 4.5V

(SCL, SDA) Logic Low Output Voltage IO= 3 mA 0.5 V

Min Minimum Horizontal Frequency PLL & OSD Functioning 25 kHz

Max Maximum Horizontal Frequency PLL & OSD Functioning 110 kHz

Max Horizontal Flyback Input Current Absolute Maximum during

HFB IN

Flyback

HFB OUT

OUT

IN THRESHOLD

Max Horizontal Flyback Input Current Absolute Maximum during Scan −700 µA

Peak Current during Flyback Design Value 4 mA

Peak Current during Scan Not exact - Duty Cycle Dependent −550 µA

IINH-Blank Detection Threshold 0 µA

= 8 pF, Video Outputs = 2.0 V

2.0 V

3.0

10 µA

. See (Note 7)

P-P

VCC+

0.5

5mA

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System Interface Signal Characteristics (Continued)

Unless otherwise noted: TA= 25˚C, VCC= +5.0V, VIN= 0.7V, V

ABL=VCC,CL

for Min and Max parameters and (Note 6) for Typicals. DAC parameters apply to all 4 DACs.

Symbol Parameter Conditions Min Typ Max Units

H-BLANK ON

H-Blank Time Delay - On + Zero crossing of I

output blanking start. I

H-BLANK OFF

H-Blank Time Delay - Off − Zero crossing of I

output blanking end. I

Max Maximum Video Blanking Level Test Setting 4, AC input signal 0 0.25 V

BLANK

FREERUN

Free Run H Frequency, Including H Blank

PW CLAMP

CLAMP MAX

Minimum Clamp Pulse Width See (Note 15) 200 ns

Maximum Low Level Clamp

Video Clamp Functioning

Pulse Voltage

CLAMP MIN

Minimum High Level Clamp

Video Clamp Functioning

Pulse Voltage

Low Clamp Gate Low Input Current V23= 2V −0.4 µA

CLAMP

High Clamp Gate High Input Current V23= 3V 0.4 µA

CLAMP

CLAMP-VIDEO

Note 1: Limits of Absolute Maximum Ratings indicate below which damage to the device must not occur.

Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits.

Note 3: All voltages are measured with respect to GND, unless otherwise specified.

Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor.

Note 5: Input from signal generator: t

Note 6: Typical specifications are specified at +25˚C and represent the most likely parametric norm.

Note 7: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. The guaranteed specifications apply only for the test conditions

listed. Some performance characteristics may change when the device is not operated under the listed test conditions.

Note 8: The supply current specified is the quiescent current for V therefore all the supply current is used by the pre-amp.

Note 9: Linearity Error is the maximum variation in step height of a 16 step staircase input signal waveform with a 0.7 V with each at least 100 ns in duration.

Note 10: dt/dV

Note 11: ∆A

gain change between any two amplifiers with the contrast set to A amplifiers’ gains might be 12.1 dB, 11.9 dB, and 11.8 dB and change to 2.2 dB, 1.9 dB and 1.7 dB respectively for contrast set to A gain change of 10.0 dB with a tracking change of

Note 12: The ABL input provides smooth decrease in gain over the operational range of 0 dB to −5 dB: ∆A V

ABL MIN GAIN

Note 13: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200 pF cap is charged to the specific voltage, then discharged directly into the IC with no external series resistor (resistance of discharge path must be under 50Ω).

Note 14: Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. Terminate the undriven amplifier inputs to simulate generator loading. Repeat test at f

Note 15: A minimum pulse width of 200 ns is the guaranteed minimum for a horizontal line of 15 kHz. This limit is guaranteed by design. If a lower line rate is used then a longer clamp pulse may be required.

Note 16: Adjust input frequency from 10 MHz (A

Note 17: Once the spot killer has been activated, the LM1276 remains in the off state until V

Time from End of Clamp Pulse to Start of Video

1 ns.

r,tf

= 200*(t

track is a measure of the ability of any two amplifiers to track each other and quantifies the matching of the three gain stages. It is the difference in

). Beyond −5 dB the gain characteristics, linearity and pulse response may depart from normal values.

5.5V–t4.5V

)/ ((t

5.5V+t4.5V

)) %/V, where: t

0.2 dB.

= 10 MHz for V

max reference level) to the −3 dB corner frequency (f

Referenced to Blue, Red and Green inputs

and 5V Dig with RL=∞. Load resistors are not required and are not used in the test circuit,

is the rise or fall time at VCC= 5.5V, and t

5.5V

C−50% and measured relative to the AVmax condition. For example, at AVmax the three

10 MHz.

SEP

= 8 pF, Video Outputs = 2.0 V

to 50% of

HFB

= +1.5mA

to 50% of

HFB

= −100µA

P-P

45 ns

85 ns

42 kHz

3.0 V

50 ns

level at the input. All 16 steps equal,

P-P

is the rise or fall time at VCC= 4.5V.

4.5V

C−50%. This yields a typical

= A(V

ABL

−3 dB

is cycled (reduced below 0.5V and then restored to 5V).

ABL=VABL MAX GAIN

. See (Note 7)

2.0 V

)–A(V

ABL

LM1276

Hexadecimal and Binary Notation

Hexadecimal numbers appear frequently throughout this document, representing slave and register addresses, and register values. These appear in the format “0x...”. For example, the slave address for writing the registers of the LM1276 is hexadecimal BA, written as 0xBA. On the other hand, binary values, where the individual bit values are shown, are indicated by a trailing “b”. For example, 0xBA is equal to 10111010b. A subset of bits within a register is referred to by the bit numbers in brackets following the

register value. For example, the OSD contrast bits are the fourth, fifth, and sixth bits of register 0x8538. Since the first bit is bit 0, the OSD contrast register is 0x8538[5:3].

Table 1 shows the definitions of the Test Settings 1–8 referred to in the specifications sections. Each test setting is a combination of five hexadecimal register values, Contrast, Gain (Blue, Red, Green) and DC offset.

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LM1276

Control No. of Bits

Contrast 7 0x7F

B, R, G

Gain

DC Offset 3 0x00

1234 5678

(Max)

7 0x7F

(Max)

(Min)

TABLE 1. Test Settings

0x00

Min

0x7F

(Max)

0x7F

(Max)

0x7F

(Max)

0x05 0x07

(Max)

Test Settings

0x7F

(Max)

Set V

P-P

0x40

(50.4%)

0x7F

(Max)

0x7F

(Max)

0x40

(50.4%)

0x7F

(Max)

0x00 (Min)

0x05 0x05 0x05 0x05 0x05

0x7F

(Max)

0x7F

(Max)

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OSD vs Video Intensity

The OSD amplitude has been increased over the LM1237 level. During monitor alignment the three gain registers are used to achieve the desired front of screen color balance. This also causes the OSD channels to be adjusted accordingly, since these are inserted into the video channels prior to the gain attenuators. This provides the means to fine-tune the intensity of the OSD relative to the video as follows. If a typical starting point for the alignment is to have the gains at maximum (0x7F) and the contrast at 0x55, the resultant OSD intensity will be higher than if the starting point is with the gains at 0x55 and the contrast at maximum (0x7F). This

LM1276

tradeoff allows the fine-tuning of the final OSD intensity relative to the video. In addition, the OSD contrast register, 0x85C8[5:3], provides 8 major increments of intensity. Together, these allow setting the OSD intensity to the most pleasing level.

ESD Protection

The LM1276 features a 3.0 kV ESD protection level (see (Notes 4, 13)). This is provided by special internal circuitry, which activates when the voltage at any pin goes beyond the supply rails by a preset amount. This protection is applied to all the pins, including SDA and SCL.

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Typical Performance Characteristics V

LM1276

= 5V, TA= 25˚C unless otherwise specified

FIGURE 3. Logic Horizontal Blanking

FIGURE 4. Logic Vertical Blanking

20096902

20096903

20096906

FIGURE 6. Logic Clamp Pulse

20096907

FIGURE 7. Red Cathode Response

20096904

FIGURE 5. Deflection Horizonal Blanking

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20096908

FIGURE 8. ABL Gain Reduction Curve

Typical Performance Characteristics

otherwise specified (Continued)

SYSTEM INTERFACE SIGNALS

The Horizontal Sync, Flyback, Vertical Sync, and the Clamp input signals are important for proper functionality of the LM1276. Both blanking inputs must be present for OSD synchronization. In addition, the Horizontal blanking input also assists in setting the proper cathode black level, along with the Clamping pulse. The Vertical blanking input initiates a blanking level at the LM1276 outputs, which is programmable from 3 to 127 lines (at least 10 is recommended). This input is set up to only accept a vertical sync pulse, and the leading edge is used to start the programmable vertical blanking signal directly. The start position of the internal Horizontal blanking pulse is programmable from 0 to 64 pixels ahead of the start position of the Horizontal flyback input. Both horizontal and vertical blanking can be individually disabled, if desired.

Figure 3 and Figure 4 show the Horizontal Flyback input when it is logic level and the Vertical input (which must always be logic level). Figure 3 shows the smaller pin 28 voltage superimposed on the horizontal blanking pulse input to the neck board with R where the voltage at pin 28 is clamped to about 1V when the pin is sinking current. Figure 4 shows the smaller pin 1 voltage superimposed on the vertical blanking input to the neck board with R spond to the application circuit of Figure 9.

Please note that the Horizontal Flyback signal to pin 28 MUST be continuously provided to the IC, even during energy save or sleep modes. In the application, this signal should be always generated whether the VGA cable is disconnected, the monitor is in energy save mofe, or sleep mode.

Figure 5 show the case where the horizontal input is from deflection. Figure 5 shows the pin 28 voltage which is derived from a horizontal flyback pulse of 35V peak to peak with R

= 8.2K and C1jumpered.

Figure 6 shows the pin 27 clamp input voltage superimposed on the neck board clamp logic input pulse.R=1kandshould be chosen to limit the pin 27 voltage to about 2.5V peak to peak. This corresponds to the application circuit given in Figure 9. The clamp input pin can also be internally connected to the Horizontal Sync pin, thus eliminating the need for a Clamp signal supplied to the neckboard. This can be enabled with register 0x853E[4].

VCC= 5V, TA= 25˚C unless

= 4.7k and C1= 0.1 µF. Note

= 4.7k. These component values corre-

H SYNC & V SYNC

V Sync at pin 1 and H Sync at pin 15 must be supplied with logic level signals generated by the MCU. In an application where a logic level clamp pulse is used, the same signal can be used for the H Sync input. It is important that both V Sync and H Sync are always receiving signals, even during VGA cable disconnect, energy save mode, or sleep mode.

CATHODE RESPONSE

Figure 7 shows the response at the red cathode for the application circuit in Figures 9, 10. The input video rise time is 1.5 ns. The resulting leading edge has a 7.1 ns rise time and 7.6% overshoot, while the trailing edge has a 7.1 ns rise time and 6.9% overshoot using an LM2467 driver.

ABL GAIN REDUCTION

The ABL function reduces the contrast level of the LM1276 as the voltage on pin 26 is lowered from V

to around 2V.

Figure 8 shows the amount of gain reduction as the voltage is lowered from V until V

reaches the knee around 3.7V, where the slope

(5.0V) to 2V. The gain reduction is small

increases. Many system designs will require about 3 dB to 5 dB of gain reduction in full beam limiting. Additional attenuation is possible, and can be used in special circumstances. However, in this case, video performance such as video linearity and tracking between channels will tend to depart from normal specifications.

The onset of ABL in the LM1276 is adjustable so that the amount of beam limiting can be varied, especially for larger Hi-Brite window displays where the contrast level is not desired to be reduced as much as a normal video display. The beam current limiting is 4-bit adjustable in steps of 80 µA each all the way up to a delta of 1.2 mA. The value of the ABL pull up resistor (R2) to the external +80V supply must be selected carefully such that the ABL threshold current will be at the desired maximum (i.e. 2 mA) when register 0x85C4 is at the lowest setting, 0x00.

There are 4 different ABL current registers corresponding to 4 different ABL settings. Each setting or register (0x85C4 0x85C7) can be assigned a different ABL current threshold. ABL current register 0 can correspond to a minimal area of the screen being highlighted, and ABL current register 4 can correspond to the maximum area of the screen being highlighted. This area is calculated by the HiBrite software, and the particular ABL register that is is to be activated is selected by the software. The values of each register are written by the MCU.

LM1276

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Typical Performance Characteristics

LM1276

otherwise specified (Continued)

VIDEO PROCESSING

Emphasis, Center Frequency at Maximum

Center Frequency, Emphasis at Maximum

These two plots show the processing done by the LM1276 on the video input signal. There are two variables for the video processing, emphasis and center frequency. Empha-

sis is controlled by bits 0-2 in registers 0x85C8, 0x85CA, or 0x85CC. This gives 8 different levels of emphasis. In the

top plot the center frequency is set at its maximum level and the 8 different levels of emphasis are measured. The video with no emphasis is adjusted to a 0.7 V maximum emphasis the video is increased to a 0.9 V level at the rising edge of the video. If the falling edge was measured it would show a similar waveform, but going in the negative direction.

Center frequency is shown in the bottom plot. Control of the

center frequency is done with bits 4-7 in register 0x85C1. This gives 16 adjustments for this feature. Every

other adjustment is shown in the bottom plot, since showing all 16 adjustments would have made the plot too difficult to read. The curves closely approximate the peaking of an RC

VCC=5V,TA= 25˚C unless

P-P

20096963

20096964

level. Using

P-P

network. Therefore, the term center frequency means the RC time constant that is approximated by each curve in the above plot. A true RC peaking network would give very large overshoot. The LM1276 has special circuitry to clip the very large overshoot, yet has the complete benefit of the RC peaking. This special circuitry allows for much more overshoot than one could do with RC peaking and still not saturate the video channel.

Note that the video channel with the emphasis also has its own independent contrast control. This allows the user to adjust his monitor for a brighter picture within the Hi-Brite window and optimize the emphasis for the resolution he is using with the monitor. Now, the monitor user can give his pictures or video a special “sparkle” when using the capabilities of the LM1276.

OSD PHASE LOCKED LOOP

The PLL in the LM1276 serves both the OSD as well as the Hi-Brite Window generation. The pixels per line range for the LM1276 OSD is from 704 to 1152 pixels per line, in increments of 64. The maximum OSD pixel frequency available is 111 MHz. For example, if the horizontal scan rate is 106 kHz, 1024 pixels per line would be acceptable to use, since the OSD pixel frequency is:

Horizontal Scan Rate X PPL =

106kHz X 1024 = 108.5 MHz

If 1152 pixels per line is being used, the horizontal scan rate would have to be lower than 106 kHz in order to not exceed the maximum OSD pixel frequency of 111 MHz. The maximum number of video lines that may be used is 1536 lines as in a 2048x1536 display. At this line rate, using a PPL setting of 4 is recommended. The LM1276 has a PLL Auto feature, which will automatically select an internal PLL frequency range setting that will guarantee optimal OSD locking for any horizontal scan rate and for improved jitter performance over a wider temperature range. This eliminates the need for PLL register settings determined by the user, as well as improved PLL performance. To initialize the PLL Auto feature, set bit, 0x8439[4] to 1. This will effectively perform all necessary calibrations and activate the PLL Auto mode, which takes approximately 2–4 vertical scan period to complete, and must be done while the video is blanked. Table 2 shows the recommended horizontal scan rate ranges (in kHz) for each pixels per line register setting, 0x8401[7:5]. These ranges are recommended for chip ambient temperatures of 0

C, and the recommended PLL filter values are 6.2 kΩ,

Cto

0.01 uF, and 1000 pF. While the OSD PLL will lock for other register combinations and at scan rates outside these ranges, the performance of the loop will be improved if these recommendations are followed.

PLL AUTO MODE INITIALIZATION SEQUENCE

Blank video.

•

Set 0x8539[4] to 1.

•

Wait for at least 2–4 vertical periods or vertical sync

•

pulses to pass. Unblank Video.

•

This sequence must be done by the microcontroller at system power up, as well as each time there is a horizontal line rate change from the video source, for the PLL Auto mode to function properly.

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LM1276

Typical Performance Characteristics V

=5V,TA= 25˚C unless otherwise specified (Continued)

TABLE 2. OSD Register Recommendations

PPL=0 PPL=1 PPL=2 PPL=3 PPL=4 PPL=5 PPL=6 PPL=7

PLL Auto 25 - 61 25 - 53 25 - 98 25 - 110 25 - 110 25 - 108 25 - 102 25 - 96

Pin Descriptions and Application Information

Pin No.

1 V Sync Logic level vertical sync signal received from the

2 4

Pin Name Schematic Description

video card in the PC or sync stripper circuit.

Analog V

Analog Ground

Ground pin and power supply pin for the input analog portion of the LM1276. Note the recommended charge storage and high frequency capacitors, which should be as close to pins 2 and 4 as possible.

5 6 7

8 9

REFREXT

Blue Video In

Red Video In

Green Video In

PLL Ground

PLL Filter

External current set resistor, 10k 1%, sets the internal bias current level for optimum performance of the LM1276. This resistor should be placed as close to pin 3 and the pin 4 ground return as possible.

These video inputs must be AC coupled with a .0047 µF cap. Internal DC restoration is done at these inputs. A series resistor of about 33Ω and external ESD protection diodes should also be used for protection from ESD damage.

Recommended topology and values are shown to the left. It is recommended that both filter branches be bypassed to the independent ground as close to pin 8 as possible. Great care should be taken to prevent external signals from

coupling into this filter from video, I

C, etc.

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Pin Descriptions and Application Information (Continued)

LM1276

Pin No.

10 PLL V

11 14

Pin Name Schematic Description

Digital Ground

Digital V

The ground pin should be connected to the rest of the circuit ground by a short but independent PCB trace to prevent contamination by extraneous signals. The PLL V isolated from the rest of the V

pin should be

line by a ferrite

bead and bypassed to pin 8 with an electrolytic capacitor and a high frequency ceramic.

Ground pin and power supply pin for the digital portion of the LM1276. Note the recommended charge storage and high frequency capacitors, which should be as close to pins 11 and 14 as possible.

12 SCL

13 SDA

15 H Sync

The I2C compatible clock line. A pull-up resistor of about 2.2 kΩ should be connected between this pin and V

. A resistor of at least 100Ω

should be connected in series with the clock line for additional ESD protection.

The I2C compatible data line. A pull-up resistor of about 2.2 kΩ should be connected between this pin and V

. A resistor of at least 100Ω

should be connected in series with the data line for additional ESD protection.

Logic level horizontal sync signal received from the MCU or sync stripper circuit. This input can also be derived from the clamp input as long as it is a logic level signal.

16 17

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Digital Ground

Digital V

Ground pin and power supply pin for the digital portion of the LM1276. Note the recommended charge storage and high frequency capacitors, which should be as close to pins 16 and 17 as possible.

Pin Descriptions and Application Information (Continued)

LM1276

Pin No.

18 19 20

Pin Name Schematic Description

DAC 3 Output DAC 2 Output DAC 1 Output

2122Analog Ground

23 24 25

Analog V

Green Output

Red Output

Blue Output

DAC outputs for cathode cut-off adjustments and brightness control. The DAC values are set

through the I

C compatible bus. A resistor of at least 1kΩ should be connected in series with these outputs for additional ESD protection.

Ground pin and power supply pin for the output analog portion of the LM1276. Note the recommended charge storage and high frequency capacitors which should be as close to pins 21 and 22 as possible.

These are the three video output pins. They are intended to drive the LM2476 and LM246X family of cathode drivers. Nominally, about 2V peak to peak will produce 40V peak to peak of cathode drive.

26 ABL

27 CLAMP

The Automatic Beam Limiter input is biased to the desired beam current limit by R and normally keeps D

forward biased. When

INT

ABL

and V

the current resupplying the CRT capacitance (averaged by C

) exceeds this limit, then D

ABL

INT

begins to turn off and the voltage at pin 26 begins to drop. The LM1276 then lowers the gain of the three video channels until the beam current reaches an equilibrium value.

This pin accepts either TTL or CMOS logic levels. This pin can also be internally connected to the Horizontal sync pin. The internal switching threshold is approximately one-half of V

.An external series resistor, R, of about 1k is recommended to avoid overdriving the input devices. In any event, R must be large enough to prevent the voltage at pin 27 from going higher than V

or below GND.

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