National Semiconductor FPD87208AXA Technical data
FPD87208AXA
+2.5V Low EMI, Low Dynamic Power XGA/WXGA
TFT-LCD Timing Controller with Reduced Swing
July 2004
FPD87208AXA +2.5V Low EMI, Low Dynamic Power XGA/WXGA TFT-LCD Timing Controller with
Reduced Swing Differential Signaling RSDS Outputs
Differential Signaling RSDS
General Description
The FPD87208AXA is a timing controller that combines an
LVDS single pixel input interface with National Reduced
Swing Differential Signaling (RSDS
for XGA and Wide XGA resolutions. It resides on the TFTLCD panel and provides the data buffering and control signal
generation for XGA, and Wide XGA graphic modes. The
RSDS path to the column driver contributes toward lowering
radiated EMI and reducing system dynamic power consumption.
This single RSDS bus conveys the 6-bit color data for XGA,
and three different WXGA resolutions.
System Diagram
™
) output driver interface
™
Outputs
Features
n Reduced Swing Differential Signaling (RSDS) digital bus
reduces dynamic power, EMI and bus-width from the
timing controller
n LVDS single pixel input interface system
n Input clock range from 25 MHz to 85 MHz
n Drives RSDS column drivers at 170 Mb/s with an
85 MHz clock (Max)
n BIST Function
n CMOS circuitry operates from a 2.25V–2.75V; 0˚C–70˚C
n 64 TQFP package with body size 10 mm x 10 mm x
1.0 mm
20101401
FIGURE 1. Block Diagram of the LCD Module
RSDS™is a trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation DS201014 www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
FPD87208AXA
Supply Voltage (V
DC TTL Input Voltage (V
DC LVDS Input Voltage (V
DC Output Voltage (V
Junction Temperature +150˚C
Storage Temperature Range
(T
) −65˚C to +150˚C
STG
Lead Temperature (T
(Soldering 10 sec.) 260˚C
) −0.3V to +3.0V
DD
) −0.3V to (VDD+ 0.3V)
IN
) −0.3V to (VDD+ 0.3V)
IN
) −0.3V to (VDD+ 0.3V)
OUT
)
L
ESD Rating:
HBM:
MM:
(HBM: R
MM: R
ZAP
ZAP
=0Ω,C
= 1.5 kΩ,C
= 200 pF)
ZAP
ZAP
= 100 pF,
2kV
200V
Operating Conditions
Min Max Units
Supply Voltage (V
Operating Temp. Range (T
Supply Noise Voltage 200 mV
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply that
the devices should be operated at these limits. The table of “Electrical
Characteristics” specifies conditions of device operation.
) 2.25 2.75 V
DD
) 0 70 ˚C
A
PP
DC Electrical Characteristics V
= 2.5V±0.25V, TA= 0˚C to 70˚C, IPI= 100 µA (Unless otherwise
DD
specified)
TTL DC Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Units
V
DD
V
IH
V
IL
V
OH
V
OL
I
IN
I
DD
Supply Voltage 2.25 2.5 2.75
Minimum Input High Voltage 1.8 V
Maximum Input Low Voltage 0.7 V
Output High Voltage IOH=−8mA 0.8xV
DD
Output Low Voltage IOL=8mA 0.4
Input Current VIN=V
V
= GND 10 µA
IN
DD
10 µA
Average Supply Current CLK = 85 MHz, RPI = 12.3k
=50pF,
C
L(TTL)
L(RSDS)
L(RSDS)
= 100Ω and
=5pF
80
= 100 µA
I
P
V
DD
= 2.5V
= 100 µA
I
P
V
DD
120
mA
= 2.75V
R
C
(jig & test fixture capacitance),
See Figure 3 for input
conditions
FPD-Link (LVDS) Receiver Input (RxCLKP/N; RxIN[y]P/N, y = 0,1,2)
Symbol Parameter Conditions Min Typ Max Units
LVDS RECEIVER DC SPECIFICATIONS
Note: LVDS Receiver DC parameters are measured under Static and Steady state conditions which may not be reflective
of its performance in the end application.
This device is compatible with TIA644 SPEC. V0 and V2.4.
V
TH
LVDS
V
TL
LVDS
I
IN
V
IN
|V
| Differential Input Voltage 0.100 0.600 V
ID
V
CM
Differential Input High Threshold
Voltage
Differential Input Low Threshold
= 1.2V
V
CM
Voltage
INput Current VIN=VDD–0.4V,
= 2.75V
V
DD
V
= 0V, VDD= 2.75V
IN
−100 mV
+100 mV
±
10 µA
±
10 µA
INput Voltage Range 0 VDD–0.4 V
Common Mode Voltage Offset
0+|V
|/2
ID
(V
DD
|V
–0.4) −
|/2
ID
V
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FPD87208AXA
DC Electrical Characteristics V
specified) (Continued)
FIGURE 2. LVDS VIDand VCMAllowable Operating Range
FPD-Link Receiver Input Pattern Used to Measure I
= 2.5V±0.25V, TA= 0˚C to 70˚C, IPI= 100 µA (Unless otherwise
DD
| and VCMDefinitions
|V
ID
DD
20101402
FIGURE 3. FPD-Link Receiver IDDPattern
20101403
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DC Electrical Characteristics V
= 2.5V±0.25V, TA= 0˚C to 70˚C, IPI= 100 µA (Unless otherwise
DD
specified) (Continued)
RSDS Output
(CLKP/N, xyP/N;x=R,G,B;y=0,1,2),VDD= 2.25V to 2.75V (Unless otherwise specified)
FPD87208AXA
Symbol Parameter Conditions Min Typ Max Units
|V
V
| Differential Output Voltage Typ. RL= 100Ω
OD
RSDS
OS
RSDS
Offset Voltage 1.2 V
= 100 µA
I
PI
200 (Figure 4)mV
20101404
FIGURE 4. RSDS Output Waveforms: Single Ended vs Differential
20101405
FIGURE 5. Typical RSDS VODvs RPIResponse Curve
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FPD87208AXA
DC Electrical Characteristics V
= 2.5V±0.25V, TA= 0˚C to 70˚C, IPI= 100 µA (Unless otherwise
DD
specified) (Continued)
Schmitt Trigger
Symbol Parameter Conditions Min Typ Max Units
V
V
V
I
INHYS
H
T−
T+
Hysteresis Voltage VT+–V
T−
0.4 V
Hysteresis Low Threshold Voltage 1.2 V
Hysteresis High Threshold Voltage 1.6 V
Input Current VIN=V
V
IN=VSS
DD
−20 0 µA
20101406
20 µA
FIGURE 6. Hysteresis Definition
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AC Electrical Characteristics
TA= 0˚C to 70˚C, VDD= 2.5V±0.25V, IPI= 100 µA (Unless otherwise specified)
LVDS Data Input
Symbol Parameter Conditions Min Max Units
FPD87208AXA
F
RXCLK
RPLLS FPD-Link Receiver
RMS RxIN Strobe Margin (Note 2) and (Figure 7) F = 85 MHz 400 ps
Note 2: Receiver Strobe Margin is defined as the valid data sampling region at the receiver inputs.
RxCLK Frequency (LVDS) 25 85 MHz
Phase Lock Loop Wake-Up Time
10 ms
FIGURE 7. FPD-Link Receiver Input Skew Margin
20101407
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