National Semiconductor DS92001 Technical data

DS92001

3.3V B/LVDS-BLVDS Buffer

General Description

The DS92001 B/LVDS-BLVDS Buffer takes a BLVDS input signal and provides a BLVDS output signal. In many large systems, signals are distributed across backplanes. One of the limiting factors for system speed is the "stub length" or the distance between the transmission line and the unterminated receivers on individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns often make it difficult to make the stubs as short as the designer would like.

The DS92001 has edge transitions optimized for multidrop backplanes where the switching frequency is in the 200 MHz range or less. The output edge rate is critical in some systems where long stubs may be present, and utilizing a slow transition allows for longer stub lengths.

The DS92001, available in the LLP (Leadless Leadframe Package) package, will allow the receiver inputs to be placed very close to the main transmission line, thus improving system performance.

July 29, 2008

A wide input dynamic range allows the DS92001 to receive differential signals from LVPECL, CML as well as LVDS sources. This will allow the device to also fill the role of an LVPECL-BLVDS or CML-BLVDS translator.

Features

Single +3.3 V Supply

■

Receiver inputs accept LVDS/CML/LVPECL signals

■

TRI-STATE outputs

■

Receiver input threshold < ±100 mV

■

Fast propagation delay of 1.4 ns (typ)

■

Low jitter 400 Mbps fully differential data path

■

Compatible with BLVDS 10-bit SerDes (40MHz)

■

Compatible with ANSI/TIA/EIA-644-A LVDS standard

■

Available in SOIC and space saving LLP package

■

Industrial Temperature Range

■

DS92001 3.3V B/LVDS-BLVDS Buffer

Connection and Block Diagrams

SOIC - Top View

20024705

LLP - Top View

20024743

20024702

Functional Operation

BLVDS Inputs BLVDS Outputs

[IN+] − [IN−] OUT+ OUT−

VID ≥ 0.1V

VID ≤ −0.1V

−0.1V ≤ VID ≤ 0.1V

H L

L H

Undefined Undefined

Ordering Information

Order Number NS Pkg. No. Pkg. Type

DS92001TMA M08A SOIC

DS92001TLD LDA08A LLP

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

DS92001

please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage (VCC)

LVCMOS/LVTTL Input Voltage (EN)

B/LVDS Receiver Input Voltage

−0.3V to (VCC + 0.3V)

−0.3V to +4V

Maximum Package Power Dissipation at 25°C M Package 726 mW Derate M Package 5.8 mW/°C above +25°C LDA Package 2.44 W Derate LDA Package 19.49 mW/°C above +25°C ESD Ratings

(HBM, 1.5kΩ, 100pF)

(EIAJ, 0Ω, 200pF)

(IN+, IN−) −0.3V to +4V BLVDS Driver Output Voltage

(OUT+, OUT−) −0.3V to +4V BLVDS Output Short Circuit

Current

Continuous

Junction Temperature +150°C Storage Temperature Range −65°C to +150°C Lead Temperature Range Soldering (4 sec.) +260°C

Recommended Operating Conditions

Min Typ Max Units

Supply Voltage (VCC) 3.0 3.3 3.6 V

Receiver Differential Input Voltage (VID) with VCM=1.2V

Operating Free Air Temperature

B/LVDS Input Rise/Fall 20% to 80%

0.1 2.4 |V|

−40 +25 +85 °C

2 20 ns

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3)

Symbol Parameter Conditions Min Typ Max Units

LVCMOS/LVTTL DC SPECIFICATIONS (EN)

BLVDS OUTPUT DC SPECIFICATIONS (OUT)

|VOD| Differential Output Voltage (Note

ΔV

OFF

OS1

OSD

High Level Input Voltage 2.0 V

Low Level Input Voltage GND 0.8 V

High Level Input Current VIN = VCC or 2.0V +7 +20

Low Level Input Current VIN = GND or 0.8V −10 ±1 +10

Input Clamp Voltage ICL = −18 mA −0.6 −1.5 V

RL = 27Ω

Change in Magnitude of VOD for

RL = 50Ω

RL = 27Ω or 50Ω Figure 1, Figure 2

Complimentary Output States

Offset Voltage

Change in Magnitude of VOS for

RL = 27Ω or RL = 50Ω

Figure 1

Complimentary Output States

Output TRI-STATE Current EN = 0V, V

= VCC or GND −20

OUT

Power-Off Leakage Current VCC = 0V or Open Circuit, V

Output Short Circuit Current (Note4)EN = VCC, VCM = 1.2V,VID = 200mV, V

VID = −200mV, VCM = 1.2V, V

VID = −200mV, VCM = 1.2V, V VID = 200mV, VCM =1.2V, V

Differential Output Short Circuit Current (Note 4)

EN = VCC, VID = |200mV|, VCM. = 1.2V, VOD = 0V (connect true and complement outputs through a

= 3.6V −20

OUT

= 0V, or

OUT+

= 0V

OUT−

= VCC , or

OUT+

= V

OUT−

250 350 500 mV

350 450 600 mV

20 mV

1.1 1.25 1.375 V

2 20 mV

±5 +20

−30 −60 mA

53 80 mA

|30| |42| mA

current meter)

≥2.5kV

≥250V

μA

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Symbol Parameter Conditions Min Typ Max Units

B/LVDS RECEIVER DC SPECIFICATIONS (IN)

Differential Input High Threshold

VCM = +0.05V, +1.2V or +3.25V −30 −5 mV

(Note 5)

Differential Input Low Threshold

−70 −30 mV

(Note 5)

CMR

Common Mode Voltage Range (Note 5)

|VID|/2 V

−|VID|/ 2

ΔI

Input Current VIN = V

VIN = 0V |1.5| |20|

Change in Magnitude of I

VIN = V

VIN = 0V 1 6

VCC = 3.6V or 0V |1.5| |20|

1 6

μA

SUPPLY CURRENT

CCD

Total Dynamic Supply Current (includes load current)

EN = VCC, RL = 27Ω or 50Ω, CL = 15 pF, Freq. = 200MHz 50% duty cycle,

50 65 mA

VID = 200mV, VCM = 1.2V

CCZ

TRI-STATE Supply Current EN = 0V,Freq. = 200MHz 50% duty cycle,

36 46 mA

VID = 200mV, VCM= 1.2V

DS92001

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AC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Note 3)

DS92001

Symbol Parameter Conditions Min Typ Max Units

LVDS OUTPUT AC SPECIFICATIONS (OUT)

PHLD

PLHD

SKD1

SKD3

SKD4

LHT

HLT

PHZ

PLZ

PZH

PZL

Differential Propagation Delay High to Low (Note 10)

Differential Propagation Delay

VID = 200mV, VCM = 1.2V,

RL = 27Ω or 50Ω, CL = 15pF Figure 3 and Figure 4

1.0 1.4 2.0 ns

1.0 1.4 2.0 ns Low to High (Note 10)

Pulse Skew |t

PLHD

− t

PHLD

0 20 200 ps (measure of duty cycle) (Notes 5, 6)

Part-to-Part Skew (Notes 5, 7) 0 200 300 ps

Part-to-Part Skew (Notes 5, 8) 0 1 ns

Rise Time (Notes 5, 10) 20% to 80% points

Fall Time (Notes 5, 10)

RL = 50Ω or 27Ω, CL = 15pF Figure 3 and Figure 5

0.350 0.6 1.0 ns

80% to 20% points

Disable Time (Active High to Z)

Disable Time (Active Low to Z)

RL = 50Ω, CL = 15pF

Figure 6 and Figure 7

3 25 ns

Enable Time (Z to Active High) 100 120 ns

Enable Time (Z to Active Low) 100 120 ns

LVDS Data Jitter, Deterministic (Peak-to-Peak) (Note 9)

LVDS Clock Jitter, Random (Note9)VID = 300mV; VCM = 1.2V at 200MHz clock

VID = 300mV; PRBS = 223 − 1 data; VCM = 1.2V at 400Mbps (NRZ)

78 ps

36 ps

MAX

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VID, VOD, VTH, VTL, and ΔVOD. VOD has a value and direction. Positive direction means OUT+ is a more positive voltage than OUT−.

Note 3: All typical are given for VCC = +3.3V and TA = +25°C, unless otherwise stated.

Note 4: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.

Note 5: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT (process, voltage and

temperature) range.

Note 6: t the same channel (a measure of duty cycle).

Note 7: t applies to devices at the same VCC and within 5°C of each other within the operating temperature range. This parameter guaranteed by design and characterization.

Note 8: t operating temperature and voltage ranges, and across process distribution. t

Note 9: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT range with the following test equipment setup: Agilent 86130A used as stimulus, 5 feet of RG142B cable with DUT test board and Agilent 86100A (digital scope mainframe) with Agilent 86122A (20GHz scope module). Data input jitter pk to pk = 22 picoseconds; Clock input jitter = 24 picoseconds; tDJ measured 100 picoseconds, tRJ measured 60 picoseconds.

Note 10: Propagation delay, rise and fall times are guaranteed by design and characterization to 200MHz. Generator for these tests: 50MHz ≤ f ≤ 200MHz, Zo = 50Ω, tr, tf ≤ 0.5ns. Generator used was HP8130A (300MHz capability).

Note 11: f is guaranteed by design and characterization. A minimum is specified, which means that the device will operate to specified conditions from DC to the minimum guaranteed AC frequency. The typical value is always greater than the minimum guarantee.

Maximum guaranteed frequency (Note 11)

, |t

− t

SKD1

PLHD

, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification

SKD3

, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices over recommended

SKD4

test: Generator (HP8133A or equivalent), Input duty cycle = 50%. Output criteria: VOD ≥ 200mV, Duty Cycle better than 45/55%. This specification

MAX

|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of

PHLD

VID = 200mV, VCM = 1.2V

is defined as |Max − Min| differential propagation delay.

SKD4

200 300 MHz

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