National Semiconductor DS90UR241, DS90UR124 Technical data
DS90UR241/DS90UR124
5-43 MHz DC-Balanced 24-Bit LVDS Serializer and
Deserializer
User selectable clock edge for parallel data on both
General Description
The DS90UR241/124 Chipset translates a 24-bit parallel bus
into a fully transparent data/control LVDS serial stream with
embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by
eliminating the skew problems between parallel data and
clock paths. It saves system cost by narrowing data paths that
in turn reduce PCB layers, cable width, and connector size
and pins.
The DS90UR241/124 incorporates LVDS signaling on the
high-speed I/O. LVDS provides a low power and low noise
environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for
the operating frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost signals
over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled
interconnects. Using National Semiconductor’s proprietary
random lock, the Serializer’s parallel data are randomized to
the Deserializer without the need of REFCLK.
Features
5 MHz–43 MHz embedded clock and DC-Balanced 24:1
■
and 1:24 data transmission
User defined pre-emphasis driving ability through external
■
resistor on LVDS outputs and capable to drive up to 10
meters shielded twisted-pair cable
■
Transmitter and Receiver
Supports AC-coupling data transmission
■
Individual power-down controls for both Transmitter and
■
Receiver
Embedded clock CDR (Clock and Data Recovery) on
■
Receiver and no source of reference clock required
All codes RDL (random data lock) to support live-
■
pluggable applications
LOCK output flag to ensure data integrity at Receiver side
■
Balanced T
■
Receiver side
Adjustable PTO (progressive turn-on) LVCMOS outputs
■
on Receiver to minimize EMI and SSO effects
@Speed BIST to validate LVDS transmission path
■
All LVCMOS inputs and control pins have internal
■
pulldown
On-chip filters for PLLs on Transmitter and Receiver
■
48-pin TQFP package for Transmitter and 64-pin TQFP
■
package for Receiver
Pure CMOS .35 µm process
■
Power supply range 3.3V ± 10%
■
Temperature range –40°C to +105°C
■
Greater than 8 kV HBM ESD structure
■
Meets ISO 10605 ESD and AEC-Q100 compliance
■
Backward compatible mode with DS90C241/DS90C124
■
SETUP/THOLD
between RCLK and RDATA on
DS90UR241/DS90UR124 5-43 MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
January 8, 2008
Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2008 National Semiconductor Corporation 201945 www.national.com
20194501
Absolute Maximum Ratings (Note )
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VDD)
LVCMOS Input Voltage −0.3V to (VDD +0.3V)
LVCMOS Output Voltage −0.3V to (V
LVDS Receiver Input Voltage −0.3V to +3.9V
LVDS Driver Output Voltage −0.3V to +3.9V
DS90UR241/DS90UR124
LVDS Output Short Circuit Duration 10 ms
Junction Temperature +150°C
Storage Temperature −65°C to +150°C
Lead Temperature
−0.3V to +4V
+0.3V)
DD
DS90UR124 − 64L TQFP
θ
θ
JA
JC
42.8 (4L*); 67.2 (2L*)°C/W
14.6°C/W
*JEDEC
ESD Rating (HBM)
ESD Rating (ISO10605)
RD = 2 kΩ, CS = 330 pF
Contact Discharge (D
Air Discharge (D
OUT+
RD = 2 kΩ, CS = 330 pF
Contact Discharge (R
Air Discharge (R
IN+
DS90UR241 meets ISO 10605
, D
OUT−
)
)
OUT+
, D
OUT−
DS90UR124 meets ISO 10605
, R
)
IN+
IN−
, R
)
IN−
(Soldering, 4 seconds) +260°C
Maximum Package Power Dissipation Capacity
Package De-rating:
1/θJA °C/W above +25°C
DS90UR241 − 48L TQFP
θ
θ
JA
JC
45.8 (4L*); 75.4 (2L*) °C/W
21.0°C/W
Recommended Operating Conditions
Min Nom Max Units
Supply Voltage (VDD) 3.0 3.3 3.6 V
Operating Free Air
Temperature (TA)
Clock Rate 5 43 MHz
Supply Noise ±100 mV
−40 +25 +105 °C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
LVCMOS DC SPECIFICATIONS
V
IH
V
IL
V
CL
I
IN
V
OH
V
OL
I
OS
I
OZ
High Level Input Voltage Tx: DIN[0:23], TCLK,
Low Level Input Voltage
Input Clamp Voltage ICL = −18 mA
TPWDNB, DEN, TRFB,
RAOFF, VODSEL,
RES0.
Rx: RPWDNB, RRFB,
REN, PTOSEL,
BISTEN, BISTM,
SLEW, RES0.
Input Current VIN = 0V or 3.6V Tx: DIN[0:23], TCLK,
TPWDNB, DEN, TRFB,
RAOFF, RES0.
Rx: RRFB, REN,
PTOSEL, BISTEN,
BISTM, SLEW, RES0.
Rx: RPWDNB −20 ±5 +20 µA
High Level Output Voltage IOH = −2 mA, SLEW = L
IOH = −4 mA, SLEW = H
Rx: R
[0:23], RCLK,
OUT
LOCK, PASS.
Low Level Output Voltage IOL = +2 mA, SLEW = L
IOL = +4 mA, SLEW = H
Output Short Circuit Current V
TRI-STATE® Output Current RPWDNB, REN = 0V,
OUT
V
OUT
= 0V
= 0V or V
DD
Rx: R
[0:23], RCLK,
OUT
LOCK, PASS.
2.0
V
DD
GND 0.8 V
−0.8 −1.5 V
−10 ±2 +10 µA
2.3 3.0
V
DD
GND 0.33 0.5 V
−40 −70 −110 mA
−30 ±0.4 +30 µA
≥±8 kV
±10 kV
±30 kV
±10 kV
±30 kV
P-P
V
V
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Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
LVDS DC SPECIFICATIONS
V
TH
V
TL
I
IN
V
OD
ΔV
V
OS
ΔV
I
OS
I
OZ
Differential Threshold High
VCM = +1.8V Rx: R
Voltage
Differential Threshold Low
Voltage
Input Current VIN = +2.4V, VDD = 3.6V
VIN = 0V, VDD = 3.6V
Output Differential Voltage
(D
)–(D
OUT+
Output Differential Voltage
OD
Unbalance
Offset Voltage
OUT−
)
RL = 100Ω, w/o preemphasis (Figure 10)
RL = 100Ω,
w/o pre-emphasis
RL = 100Ω,
w/o pre-emphasis
Offset Voltage Unbalance
OS
RL = 100Ω,
w/o pre-emphasis
Output Short Circuit Current D
= 0V, DIN = H,
OUT
TPWDNB = 2.4V
TRI-STATE Output Current TPWDNB = 0V,
D
= 0V OR V
OUT
TPWDNB = 2.4V, DEN = 0V
D
= 0V OR V
OUT
, R
IN+
IN−
+50 mV
−50 mV
±100 ±250 µA
±100 ±250 µA
VODSEL = L Tx: D
OUT+
, D
OUT−
380 500 630
VODSEL = H 500 900 1100
VODSEL = L
VODSEL = H
VODSEL = L
VODSEL = H
VODSEL = L
VODSEL = H
1 50 mV
1.00 1.25 1.50 V
3 50 mV
VODSEL = L −2.0 −5.0 −8.0
VODSEL = H −4.5 −7.9 −14.0
DD
DD
−15 ±1 +15 µA
−15 ±1 +15 µA
mV
mA
TPWDNB = 2.4V, DEN = 2.4V,
D
= 0V OR V
OUT
DD
−15 ±1 +15 µA
NO LOCK (NO TCLK)
SER/DES SUPPLY CURRENT (DVDD*, PVDD* AND AVDD* PINS) *DIGITAL, PLL, AND ANALOG VDDS
I
DDT
I
DDTZ
I
DDR
Serializer
Total Supply Current
(includes load current)
Serializer
Supply Current Power-down
Deserializer
Total Supply Current
(includes load current)
RL = 100Ω, PRE = OFF,
RAOFF = H, VODSEL = L
RL = 100Ω, PRE = 12 kΩ,
RAOFF = H, VODSEL = L
RL = 100Ω, PRE = OFF,
RAOFF = H, VODSEL = H
TPWDNB = 0V
(All other LVCMOS Inputs = 0V)
CL = 4 pF,
SLEW = H
f = 43 MHz,
CHECKER BOARD
Pattern (Figure 1)
f = 43 MHz,
RANDOM pattern
f = 43 MHz,
CHECKER BOARD
Pattern LVCMOS
60 85 mA
65 90 mA
66 90 mA
45 µA
85 105 mA
Output (Figure 2)
CL = 4 pF,
SLEW = H
f = 43 MHz,
RANDOM pattern
80 100 mA
LVCMOS Output
I
DDRZ
Deserializer
Supply Current Power-down
RPWDNB = 0V
(All other LVCMOS Inputs = 0V,
R
IN+/RIN-
= 0V)
50 µA
DS90UR241/DS90UR124
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Serializer Input Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
t
TCP
t
TCIH
t
TCIL
t
CLKT
t
JIT
DS90UR241/DS90UR124
Transmit Clock Period (Figure 5)
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition Time (Note 8), (Figure 4)
TCLK Input Jitter (Note 9)
23.25 T 200 ns
0.3T 0.5T 0.7T ns
0.3T 0.5T 0.7T ns
2.5 ns
±100 ps
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
t
LLHT
t
LHLT
t
DIS
t
DIH
t
HZD
t
LZD
t
ZHD
t
ZLD
t
PLD
t
SD
TxOUT_E_O TxOUT_Eye_Opening.
LVDS Low-to-High Transition Time
LVDS High-to-Low Transition Time
DIN (0:23) Setup to TCLK
DIN (0:23) Hold from TCLK
D
± HIGH to TRI-STATE Delay
OUT
D
± LOW to TRI-STATE Delay
OUT
D
± TRI-STATE to HIGH Delay
OUT
D
± TRI-STATE to LOW Delay
OUT
Serializer PLL Lock Time
Serializer Delay
TxOUT_E_O centered on (tBIT/)2
RL = 100Ω, VODSEL = L,
CL = 10 pF to GND, (Figure 3)
RL = 100Ω, CL = 10 pF to GND,
(Note 8), (Figure 5)
RL = 100Ω,
CL = 10 pF to GND,
(Note 5), (Figure 6)
RL = 100Ω
RL = 100Ω, PRE = OFF,
RAOFF = L, TRFB = H,
(Figure 8)
RL = 100Ω, PRE = OFF,
RAOFF = L, TRFB = L,
(Figure 8)
5 MHz–43 MHz,
RL = 100Ω, CL = 10 pF to GND,
RANDOM pattern
(Notes 9, 10, 13), (Figure 9)
245 550 ps
264 550 ps
4 ns
4 ns
10 15 ns
10 15 ns
75 150 ns
75 150 ns
10 ms
3.5T+2 3.5T+10 ns
3.5T+2 3.5T+10 ns
0.76 0.84 UI
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
t
RCP
t
RDC
t
CLH
t
CHL
t
CLH
t
CHL
t
ROS
t
ROH
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Receiver out Clock Period t
RCP
= t
TCP
,
PTOSEL = H
RCLK Duty Cycle PTOSEL = H,
SLEW = L
LVCMOS Low-to-High
Transition Time
LVCMOS High-to-Low
Transition Time
LVCMOS Low-to-High
Transition Time
LVCMOS High-to-Low
Transition Time
R
(0:7) Setup Data to
OUT
RCLK (Group 1)
R
(0:7) Hold Data to RCLK
OUT
CL = 4 pF
(lumped load),
SLEW = H
(Note 8)
CL = 4 pF
(lumped load),
SLEW = L
(Note 8)
PTOSEL = L,
SLEW = H,
(Figure 16)
(Group 1)
RCLK
(Figure 15)
R
[0:23],
OUT
RCLK, LOCK
R
[0:23],
OUT
RCLK, LOCK
R
[0:7] (0.35)*
OUT
23.25 T 200 ns
45 50 55 %
1.5 2.5 ns
1.5 2.5 ns
2.0 3.5 ns
2.0 3.5 ns
t
RCP
(0.35)*
t
RCP
(0.5*t
(0.5*t
RCP
RCP
)–3 UI
)–3 UI
ns
ns
Symbol Parameter Conditions Pin/Freq. Min Typ Max Units
t
ROS
t
ROH
t
ROS
t
ROH
t
ROS
t
ROH
t
ROS
t
ROH
t
ROS
t
ROH
t
HZR
t
LZR
t
ZHR
t
ZLR
t
DD
t
DSR
RxIN_TOL-L Receiver INput TOLerance
RxIN_TOL-R Receiver INput TOLerance
R
(8:15) Setup Data to
OUT
RCLK (Group 2)
R
(8:15) Hold Data to
OUT
PTOSEL = L,
SLEW = H,
(Figure 16)
RCLK (Group 2)
R
(16:23) Setup Data to
OUT
RCLK (Group 3)
R
(16:23) Setup Data to
OUT
RCLK (Group 3)
R
(0:7) Setup Data to
OUT
RCLK (Group 1)
R
(0:7) Hold Data to RCLK
OUT
PTOSEL = H,
SLEW = H,
(Figure 15)
(Group 1)
R
(8:15) Setup Data to
OUT
RCLK (Group 2)
R
(8:15) Hold Data to
OUT
RCLK (Group 2)
R
(16:23) Setup Data to
OUT
RCLK (Group 3)
R
(16:23) Setup Data to
OUT
RCLK (Group 3)
HIGH to TRI-STATE Delay PTOSEL = H,
LOW to TRI-STATE Delay
(Figure 14)
TRI-STATE to HIGH Delay
TRI-STATE to LOW Delay
Deserializer Delay PTOSEL = H,
(Figure 12)
Deserializer PLL Lock Time
(Notes 6, 8) 5 MHz 128k*T ms
from Powerdown
(Notes 7, 8, 10),
Left
(Figure 17)
(Notes 7, 8, 10),
Right
(Figure 17)
R
[8:15],
OUT
LOCK
R
[16:23] (0.35)*
OUT
R
[0:7] (0.35)*
OUT
R
[8:15],
OUT
LOCK
R
[16:23] (0.35)*
OUT
R
[0:23],
OUT
RCLK, LOCK
(0.35)*
t
RCP
(0.35)*
t
RCP
t
RCP
(0.35)*
t
RCP
t
RCP
(0.35)*
t
RCP
(0.35)*
t
RCP
(0.35)*
t
RCP
t
RCP
(0.35)*
t
RCP
(0.5*t
(0.5*t
(0.5*t
(0.5*t
(0.5*t
(0.5*t
(0.5*t
(0.5*t
(0.5*t
(0.5*t
RCP
RCP
RCP
RCP
RCP
RCP
RCP
RCP
RCP
RCP
)–3 UI
)–3 UI
)–3 UI
)–3 UI
)–2 UI
)+2 UI
)−1 UI
)+1 UI
)+1 UI
)–1 UI
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3 10 ns
3 10 ns
3 10 ns
3 10 ns
RCLK
[5+(5/56)]T+3.7
[5+(5/56)]T+8ns
43 MHz 128k*T ms
5 MHz–43 MHz
5 MHz–43 MHz
0.25 UI
0.25 UI
DS90UR241/DS90UR124
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 4: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD,
VTH and VTL which are differential voltages.
Note 5: When the Serializer output is tri-stated, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
Note 6: t
Note 7: RxIN_TOL is a measure of how much phase noise (jitter) the Deserializer can tolerate in the incoming data stream before bit errors occur. It is a
measurement in reference with the ideal bit position, please see National’s AN-1217 for detail.
Note 8: Specification is guaranteed by characterization and is not tested in production.
Note 9: t
Note 10: UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
Note 11: Figures 1, 2, 8, 12, 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
Note 12: Figures 5, 15, 16 show a rising edge data strobe (TCLK IN/RCLK OUT).
Note 13: TxOUT_E_O is affected by pre-emphasis value.
is the time required by the Deserializer to obtain lock when exiting powerdown mode.
DSR
(@BER of 10e-9) specifies the allowable jitter on TCLK. t
JIT
not included in TxOUT_E_O parameter.
JIT
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AC Timing Diagrams and Test Circuits
FIGURE 1. Serializer Input Checkerboard Pattern
20194502
20194503
FIGURE 2. Deserializer Output Checkerboard Pattern
FIGURE 3. Serializer LVDS Output Load and Transition Times
20194504
FIGURE 5. Serializer Setup/Hold Times
DS90UR241/DS90UR124
20194507
FIGURE 6. Serializer TRI-STATE Test Circuit and Delay
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20194508
DS90UR241/DS90UR124
20194509
FIGURE 7. Serializer PLL Lock Time, and TPWDNB TRI-STATE Delays
20194510
FIGURE 8. Serializer Delay
FIGURE 9. Transmitter Output Eye Opening (TxOUT_E_O)
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20194515
DS90UR241/DS90UR124
VOD = (D
OUT+
) – (D
OUT−
)
Differential output signal is shown as (D
FIGURE 11. Deserializer LVCMOS Output Load and Transition Times
OUT+
) – (D
), device in Data Transfer mode.
OUT−
FIGURE 10. Serializer VOD Diagram
20194517
20194505
FIGURE 12. Deserializer Delay
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20194511
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