National Semiconductor DS90LV049H Technical data
DS90LV049H
High Temperature 3V LVDS Dual Line Driver and
Receiver Pair
DS90LV049H High Temperature 3V LVDS Dual Line Driver and Receiver Pair
September 2005
General Description
The DS90LV049H is a dual CMOS flow-through differential
line driver-receiver pair designed for applications requiring
ultra low power dissipation, exceptional noise immunity, and
high data throughput. The device is designed to support data
rates in excess of 400 Mbps utilizing Low Voltage Differential
Signaling (LVDS) technology.
The DS90LV049H drivers accept LVTTL/LVCMOS signals
and translate them to LVDS signals. The receivers accept
LVDS signals and translate them to 3 V CMOS signals. The
LVDS input buffers have internal failsafe biasing that places
the outputs to a known H (high) state for floating receiver
inputs. In addition, the DS90LV049H supports a TRI-STATE
function for a low idle power state when the device is not in
use.
The EN and EN inputs are ANDed together and control the
TRI-STATE outputs. The enables are common to all four
gates.
Connection Diagram
Dual-In-Line
Features
n High Temperature +125˚C Operating Range
n Up to 400 Mbps switching rates
n Flow-through pinout simplifies PCB layout
n 50 ps typical driver channel-to-channel skew
n 50 ps typical receiver channel-to-channel skew
n 3.3 V single power supply design
n TRI-STATE output control
n Internal fail-safe biasing of receiver inputs
n Low power dissipation (70 mW at 3.3 V static)
n High impedance on LVDS outputs on power down
n Conforms to TIA/EIA-644-A LVDS Standard
n Available in low profile 16 pin TSSOP package
Functional Diagram
Order Number DS90LV049HMT
Order Number DS90LV049HMTX (Tape and Reel)
See NS Package Number MTC16
20161701
20161702
Truth Table
EN EN LVDS Out LVCMOS Out
L or Open L or Open OFF OFF
H L or Open ON ON
L or Open H OFF OFF
H H OFF OFF
© 2005 National Semiconductor Corporation DS201617 www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
DS90LV049H
Supply Voltage (V
LVCMOS Input Voltage (D
LVDS Input Voltage (R
Enable Input Voltage (EN, EN)
LVCMOS Output Voltage (R
) −0.3Vto+4V
DD
) −0.3Vto(VDD+ 0.3 V)
IN
IN+,RIN-
) −0.3 V to +3.9 V
−0.3Vto(VDD+ 0.3 V)
) −0.3Vto(VDD+ 0.3 V)
OUT
Lead Temperature Range
Soldering (4 sec.) +260˚C
Maximum Junction Temperature +150˚C
Maximum Package Power Dissipation
@
+25˚C
MTC Package 866 mW
Derate MTC Package 6.9 mW/˚C above +25˚C
ESD Rating
(HBM, 1.5 kΩ, 100 pF) ≥ 7kV
(MM, 0 Ω, 200 pF) ≥ 250 V
LVDS Output Voltage
(D
OUT+,DOUT-
LVCMOS Output Short Circuit
Current (R
LVDS Output Short Circuit
Current (D
LVDS Output Short Circuit
Current Duration(D
) −0.3 V to +3.9 V
) 100 mA
OUT
OUT+,DOUT−
)24mA
OUT+,DOUT−
) Continuous
Recommended Operating Conditions
Min Typ Max Units
Supply Voltage (V
Operating Free Air
Temperature (T
) +3.0 +3.3 +3.6 V
DD
) −40 +25 +125 ˚C
A
Storage Temperature Range −65˚C to +150˚C
Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 2, 4, 6)
Symbol Parameter Conditions Pin Min Typ Max Units
LVCMOS Input DC Specifications (Driver Inputs, ENABLE Pins)
V
IH
V
IL
I
IH
I
IL
V
CL
LVDS Output DC Specifications (Driver Outputs)
|V
OD
∆V
OD
V
OS
∆V
OS
I
OS
I
OSD
I
OFF
I
OZ
LVDS Input DC Specifications (Receiver Inputs)
V
TH
V
TL
V
CMR
I
IN
Input High Voltage
Input Low Voltage GND 0.8 V
Input High Current VIN=V
DD
Input Low Current VIN= GND −10 −0.1 +10 µA
D
EN
EN
IN
2.0 V
−10 1 +10 µA
Input Clamp Voltage ICL= −18 mA −1.5 −0.6 V
| Differential Output Voltage
Change in Magnitude of VODfor
Complementary Output States
Offset Voltage 1.125 1.23 1.375 V
R
= 100 Ω
L
(Figure 1)
Change in Magnitude of VOSfor
250 350 450 mV
1 35 |mV|
1 25 |mV|
Complementary Output States
Output Short Circuit Current
(Note 14)
Differential Output Short Circuit
Current (Note 14)
Power-off Leakage V
Output TRI-STATE Current EN=0VandEN=V
ENABLED,
D
IN=VDD,DOUT+
= GND, D
D
IN
ENABLED, V
=0Vor3.6V
OUT
=0VorOpen
V
DD
V
=0VorV
OUT
OUT−
OD
=0Vor
=0V
=0V
DD
D
D
OUT−
OUT+
−5.8 −9.0 mA
−5.8 −9.0 mA
−20
DD
−10
±
1 +20 µA
±
1 +10 µA
Differential Input High Threshold VCM= 1.2 V, 0.05 V, 2.35 V −15 35 mV
Differential Input Low Threshold
-100 −15 mV
Common-Mode Voltage Range VID= 100 mV, VDD=3.3 V 0.05 3 V
R
IN+
R
IN-
−12
−10
±
4 +12 µA
±
1 +10 µA
Input Current
V
=3.6 V
DD
=0 V or 2.8 V
V
IN
V
=0 V
DD
=0Vor2.8Vor3.6V
V
IN
DD
V
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Electrical Characteristics (Continued)
Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 2, 4, 6)
Symbol Parameter Conditions Pin Min Typ Max Units
LVCMOS Output DC Specifications (Receiver Outputs)
V
OH
V
OL
I
OZ
Output High Voltage IOH= -0.4 mA, VID= 200 mV
Output Low Voltage IOL= 2 mA, VID= 200 mV 0.05 0.25 V
Output TRI-STATE Current Disabled, V
OUT
=0VorV
DD
R
OUT
2.7 3.3 V
-10
±
1 +10 µA
General DC Specifications
I
I
DD
DDZ
Power Supply Current (Note 3) EN = 3.3 V
TRI-State Supply Current EN=0V 15 25 mA
V
DD
21 35 mA
Switching Characteristics
VDD= +3.3V±10%, TA= −40˚C to +125˚C (Notes 4, 13)
Symbol Parameter Conditions Min Typ Max Units
LVDS Outputs (Driver Outputs)
t
PHLD
t
PLHD
t
SKD1
t
SKD2
t
SKD3
t
TLH
t
THL
t
PHZ
t
PLZ
t
PZH
t
PZL
f
MAX
LVCMOS Outputs (Receiver Outputs)
t
PHL
t
PLH
t
SK1
t
SK2
t
SK3
t
TLH
t
THL
t
PHZ
t
PLZ
t
PZH
t
PZL
f
MAX
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: V
V
OD
Note 3: Both, driver and receiver inputs are static. All LVDS outputs have 100 Ω load. All LVCMOS outputs are floating. None of the outputs have any lumped
capacitive load.
Note 4: All typical values are given for: V
Note 5: These parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage,
temperature) ranges.
Note 6: The DS90LV049H’s drivers are current mode devices and only function within datasheet specifications when a resistive load is applied to their outputs. The
typical range of the resistor values is 90 Ω to 110 Ω.
Note 7: t
edge and the negative going edge of the same driver channel.
Differential Propagation Delay High to Low
0.7 2 ns
Differential Propagation Delay Low to High 0.7 2 ns
Differential Pulse Skew |t
PHLD−tPLHD
(Notes 5, 7)
Differential Channel-to-Channel Skew
(Notes 5, 8)
|
= 100 Ω
R
L
(Figure 2 and Figure 3)
0 0.05 0.4 ns
0 0.05 0.5 ns
Differential Part-to-Part Skew (Notes 5, 9) 0 1.0 ns
Rise Time (Note 5) 0.2 0.4 1 ns
Fall Time (Note 5) 0.2 0.4 1 ns
Disable Time High to Z
Disable Time Low to Z 1.5 3 ns
Enable Time Z to High 1 3 6 ns
= 100 Ω
R
L
(Figure 4 and Figure 5)
1.5 3 ns
Enable Time Z to Low 1 3 6 ns
Maximum Operating Frequency (Note 16) 200 250 MHz
Propagation Delay High to Low
0.5 2 3.5 ns
Propagation Delay Low to High 0.5 2 3.5 ns
Pulse Skew |t
PHL−tPLH
Channel-to-Channel Skew (Note 11) 0 0.05 0.5 ns
| (Note 10) 0 0.05 0.4 ns
(Figure 6 and Figure 7)
Part-to-Part Skew (Note 12) 0 1.0 ns
Rise Time(Note 5) 0.3 0.9 1.4 ns
Fall Time(Note 5) 0.3 0.75 1.4 ns
Disable Time High to Z
Disable Time Low to Z 3 5.4 8 ns
Enable Time Z to High 2.5 4.6 7 ns
(Figure 8 and Figure 9)
3 5.6 8 ns
Enable Time Z to Low 2.5 4.6 7 ns
Maximum Operating Frequency (Note 17) 200 250 MHz
and ∆VOD.
= +3.3 V, TA= +25˚C.
DD
or differential pulse skew is defined as |t
SKD1
PHLD−tPLHD
|. It is the magnitude difference in the differential propagation delays between the positive going
TH,VTL
DS90LV049H
,
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