DS90LV049H
High Temperature 3V LVDS Dual Line Driver and
Receiver Pair
DS90LV049H High Temperature 3V LVDS Dual Line Driver and Receiver Pair
September 2005
General Description
The DS90LV049H is a dual CMOS flow-through differential
line driver-receiver pair designed for applications requiring
ultra low power dissipation, exceptional noise immunity, and
high data throughput. The device is designed to support data
rates in excess of 400 Mbps utilizing Low Voltage Differential
Signaling (LVDS) technology.
The DS90LV049H drivers accept LVTTL/LVCMOS signals
and translate them to LVDS signals. The receivers accept
LVDS signals and translate them to 3 V CMOS signals. The
LVDS input buffers have internal failsafe biasing that places
the outputs to a known H (high) state for floating receiver
inputs. In addition, the DS90LV049H supports a TRI-STATE
function for a low idle power state when the device is not in
use.
The EN and EN inputs are ANDed together and control the
TRI-STATE outputs. The enables are common to all four
gates.
Connection Diagram
Dual-In-Line
Features
n High Temperature +125˚C Operating Range
n Up to 400 Mbps switching rates
n Flow-through pinout simplifies PCB layout
n 50 ps typical driver channel-to-channel skew
n 50 ps typical receiver channel-to-channel skew
n 3.3 V single power supply design
n TRI-STATE output control
n Internal fail-safe biasing of receiver inputs
n Low power dissipation (70 mW at 3.3 V static)
n High impedance on LVDS outputs on power down
n Conforms to TIA/EIA-644-A LVDS Standard
n Available in low profile 16 pin TSSOP package
Functional Diagram
Order Number DS90LV049HMT
Order Number DS90LV049HMTX (Tape and Reel)
See NS Package Number MTC16
20161701
20161702
Truth Table
EN EN LVDS Out LVCMOS Out
L or Open L or Open OFF OFF
H L or Open ON ON
L or Open H OFF OFF
H H OFF OFF
© 2005 National Semiconductor Corporation DS201617 www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
DS90LV049H
Supply Voltage (V
LVCMOS Input Voltage (D
LVDS Input Voltage (R
Enable Input Voltage (EN, EN)
LVCMOS Output Voltage (R
) −0.3Vto+4V
DD
) −0.3Vto(VDD+ 0.3 V)
IN
IN+,RIN-
) −0.3 V to +3.9 V
−0.3Vto(VDD+ 0.3 V)
) −0.3Vto(VDD+ 0.3 V)
OUT
Lead Temperature Range
Soldering (4 sec.) +260˚C
Maximum Junction Temperature +150˚C
Maximum Package Power Dissipation
@
+25˚C
MTC Package 866 mW
Derate MTC Package 6.9 mW/˚C above +25˚C
ESD Rating
(HBM, 1.5 kΩ, 100 pF) ≥ 7kV
(MM, 0 Ω, 200 pF) ≥ 250 V
LVDS Output Voltage
(D
OUT+,DOUT-
LVCMOS Output Short Circuit
Current (R
LVDS Output Short Circuit
Current (D
LVDS Output Short Circuit
Current Duration(D
) −0.3 V to +3.9 V
) 100 mA
OUT
OUT+,DOUT−
)24mA
OUT+,DOUT−
) Continuous
Recommended Operating Conditions
Min Typ Max Units
Supply Voltage (V
Operating Free Air
Temperature (T
) +3.0 +3.3 +3.6 V
DD
) −40 +25 +125 ˚C
A
Storage Temperature Range −65˚C to +150˚C
Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 2, 4, 6)
Symbol Parameter Conditions Pin Min Typ Max Units
LVCMOS Input DC Specifications (Driver Inputs, ENABLE Pins)
V
IH
V
IL
I
IH
I
IL
V
CL
LVDS Output DC Specifications (Driver Outputs)
|V
OD
∆V
OD
V
OS
∆V
OS
I
OS
I
OSD
I
OFF
I
OZ
LVDS Input DC Specifications (Receiver Inputs)
V
TH
V
TL
V
CMR
I
IN
Input High Voltage
Input Low Voltage GND 0.8 V
Input High Current VIN=V
DD
Input Low Current VIN= GND −10 −0.1 +10 µA
D
EN
EN
IN
2.0 V
−10 1 +10 µA
Input Clamp Voltage ICL= −18 mA −1.5 −0.6 V
| Differential Output Voltage
Change in Magnitude of VODfor
Complementary Output States
Offset Voltage 1.125 1.23 1.375 V
R
= 100 Ω
L
(Figure 1)
Change in Magnitude of VOSfor
250 350 450 mV
1 35 |mV|
1 25 |mV|
Complementary Output States
Output Short Circuit Current
(Note 14)
Differential Output Short Circuit
Current (Note 14)
Power-off Leakage V
Output TRI-STATE Current EN=0VandEN=V
ENABLED,
D
IN=VDD,DOUT+
= GND, D
D
IN
ENABLED, V
=0Vor3.6V
OUT
=0VorOpen
V
DD
V
=0VorV
OUT
OUT−
OD
=0Vor
=0V
=0V
DD
D
D
OUT−
OUT+
−5.8 −9.0 mA
−5.8 −9.0 mA
−20
DD
−10
±
1 +20 µA
±
1 +10 µA
Differential Input High Threshold VCM= 1.2 V, 0.05 V, 2.35 V −15 35 mV
Differential Input Low Threshold
-100 −15 mV
Common-Mode Voltage Range VID= 100 mV, VDD=3.3 V 0.05 3 V
R
IN+
R
IN-
−12
−10
±
4 +12 µA
±
1 +10 µA
Input Current
V
=3.6 V
DD
=0 V or 2.8 V
V
IN
V
=0 V
DD
=0Vor2.8Vor3.6V
V
IN
DD
V
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Electrical Characteristics (Continued)
Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 2, 4, 6)
Symbol Parameter Conditions Pin Min Typ Max Units
LVCMOS Output DC Specifications (Receiver Outputs)
V
OH
V
OL
I
OZ
Output High Voltage IOH= -0.4 mA, VID= 200 mV
Output Low Voltage IOL= 2 mA, VID= 200 mV 0.05 0.25 V
Output TRI-STATE Current Disabled, V
OUT
=0VorV
DD
R
OUT
2.7 3.3 V
-10
±
1 +10 µA
General DC Specifications
I
I
DD
DDZ
Power Supply Current (Note 3) EN = 3.3 V
TRI-State Supply Current EN=0V 15 25 mA
V
DD
21 35 mA
Switching Characteristics
VDD= +3.3V±10%, TA= −40˚C to +125˚C (Notes 4, 13)
Symbol Parameter Conditions Min Typ Max Units
LVDS Outputs (Driver Outputs)
t
PHLD
t
PLHD
t
SKD1
t
SKD2
t
SKD3
t
TLH
t
THL
t
PHZ
t
PLZ
t
PZH
t
PZL
f
MAX
LVCMOS Outputs (Receiver Outputs)
t
PHL
t
PLH
t
SK1
t
SK2
t
SK3
t
TLH
t
THL
t
PHZ
t
PLZ
t
PZH
t
PZL
f
MAX
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: V
V
OD
Note 3: Both, driver and receiver inputs are static. All LVDS outputs have 100 Ω load. All LVCMOS outputs are floating. None of the outputs have any lumped
capacitive load.
Note 4: All typical values are given for: V
Note 5: These parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage,
temperature) ranges.
Note 6: The DS90LV049H’s drivers are current mode devices and only function within datasheet specifications when a resistive load is applied to their outputs. The
typical range of the resistor values is 90 Ω to 110 Ω.
Note 7: t
edge and the negative going edge of the same driver channel.
Differential Propagation Delay High to Low
0.7 2 ns
Differential Propagation Delay Low to High 0.7 2 ns
Differential Pulse Skew |t
PHLD−tPLHD
(Notes 5, 7)
Differential Channel-to-Channel Skew
(Notes 5, 8)
|
= 100 Ω
R
L
(Figure 2 and Figure 3)
0 0.05 0.4 ns
0 0.05 0.5 ns
Differential Part-to-Part Skew (Notes 5, 9) 0 1.0 ns
Rise Time (Note 5) 0.2 0.4 1 ns
Fall Time (Note 5) 0.2 0.4 1 ns
Disable Time High to Z
Disable Time Low to Z 1.5 3 ns
Enable Time Z to High 1 3 6 ns
= 100 Ω
R
L
(Figure 4 and Figure 5)
1.5 3 ns
Enable Time Z to Low 1 3 6 ns
Maximum Operating Frequency (Note 16) 200 250 MHz
Propagation Delay High to Low
0.5 2 3.5 ns
Propagation Delay Low to High 0.5 2 3.5 ns
Pulse Skew |t
PHL−tPLH
Channel-to-Channel Skew (Note 11) 0 0.05 0.5 ns
| (Note 10) 0 0.05 0.4 ns
(Figure 6 and Figure 7)
Part-to-Part Skew (Note 12) 0 1.0 ns
Rise Time(Note 5) 0.3 0.9 1.4 ns
Fall Time(Note 5) 0.3 0.75 1.4 ns
Disable Time High to Z
Disable Time Low to Z 3 5.4 8 ns
Enable Time Z to High 2.5 4.6 7 ns
(Figure 8 and Figure 9)
3 5.6 8 ns
Enable Time Z to Low 2.5 4.6 7 ns
Maximum Operating Frequency (Note 17) 200 250 MHz
and ∆VOD.
= +3.3 V, TA= +25˚C.
DD
or differential pulse skew is defined as |t
SKD1
PHLD−tPLHD
|. It is the magnitude difference in the differential propagation delays between the positive going
TH,VTL
DS90LV049H
,
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Switching Characteristics (Continued)
Note 8: t
the same device.
Note 9: t
specified differential propagation delays. This specification applies to devices at the same V
DS90LV049H
Note 10: t
going edge of the same receiver channel.
Note 11: t
Note 12: t
propagation delays. This specification applies to devices at the same V
Note 13: Generator waveform for all tests unless otherwise specified:f=1MHz, Z
Note 14: Output short circuit current (I
Note 15: All input voltages are for one channel unless otherwise specified. Other inputs are set to GND.
Note 16: f
switching.
Note 17: f
>
2.7 V, V
or differential channel-to-channel skew is defined as the magnitude difference in the differential propagation delays between two driver channels on
SKD2
or differential part-to-part skew is defined as |t
SKD3
or pulse skew is defined as |t
SK1
or channel-to-channel skew is defined as the magnitude difference in the propagation delays between two receiver channels on the same device.
SK2
or part-to-part skew is defined as |t
SK3
generator input conditions: tr=t
MAX
generator input conditions: tr=t
MAX
<
0.25 V, all channels switching.
OL
PHL−tPLH
) is specified as magnitude only, minus sign indicates direction only.
OS
<
1 ns (0% to 100%), 50% duty cycle,0Vto3V.Output Criteria: duty cycle = 45%/55%, V
f
<
f
PLHD Max−tPLHD Min
|. It is the magnitude difference in the propagation delays between the positive going edge and the negative
PLH Max−tPLH Min
|or|t
1 ns (0% to 100%), 50% duty cycle, VID= 200 mV, VCM= 1.2 V . Output Criteria: duty cycle = 45%/55%, V
|or|t
PHLD Max−tPHLD Min
PHL Max−tPHL Min
and within 5˚C of each other within the operating temperature range.
DD
=50Ω,tr≤ 1 ns, and tf≤ 1 ns.
O
Parameter Measurement Information
and within 5˚C of each other within the operating temperature range.
DD
|. It is the difference between the minimum and maximum specified
>
250 mV, all channels
OD
|. It is the difference between the minimum and maximum
OH
20161703
FIGURE 1. Driver VODand VOSTest Circuit
FIGURE 2. Driver Propagation Delay and Transition Time Test Circuit
20161704
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Parameter Measurement Information (Continued)
FIGURE 3. Driver Propagation Delay and Transition Time Waveforms
DS90LV049H
20161705
FIGURE 4. Driver TRI-STATE Delay Test Circuit
20161706
www.national.com5
Parameter Measurement Information (Continued)
DS90LV049H
FIGURE 5. Driver TRI-STATE Delay Waveform
20161707
FIGURE 6. Receiver Propagation Delay and Transition Time Test Circuit
FIGURE 7. Receiver Propagation Delay and Transition Time Waveforms
www.national.com 6
20161709
20161710
Parameter Measurement Information (Continued)
FIGURE 8. Receiver TRI-STATE Delay Test Circuit
DS90LV049H
20161711
Typical Application
20161714
FIGURE 9. Receiver TRI-STATE Delay Waveforms
20161708
FIGURE 10. Point-to-Point Application
www.national.com7
Applications Information
General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner’s Manual (lit #550062-003), AN-805,
DS90LV049H
AN-808, AN-903, AN-916, AN-971, AN-977.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 10. This configuration provides a clean signaling
environment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media
which may be a standard twisted pair cable, a parallel pair
cable, or simply PCB traces. Typically, the characteristic
differential impedance of the media is in the range of 100 Ω.
A termination resistor of 100 Ω (selected to match the media), and is located as close to the receiver input pins as
possible. The termination resistor converts the driver output
current (current mode) into a voltage that is detected by the
receiver. Other configurations are possible such as a multireceiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities
as well as ground shifting, noise margin limits, and total
termination loading must be taken into account.
The TRI-STATE function allows the device outputs to be
disabled, thus obtaining an even lower power state when the
transmission of data is not required.
The DS90LV049H has a flow-through pinout that allows for
easy PCB layout. The LVDS signals on one side of the
device easily allows for matching electrical lengths of the
differential pair trace lines between the driver and the receiver as well as allowing the trace lines to be close together
to couple noise as common-mode. Noise isolation is
achieved with the LVDS signals on one side of the device
and the TTL signals on the other side.
POWER DECOUPLING RECOMMENDATIONS
Bypass capacitors must be used on power pins. Use high
frequency ceramic (surface mount is recommended) 0.1 µF
and 0.001 µF capacitors in parallel at the power supply pin
with the smallest value capacitor closest to the device supply
pin. Additional scattered capacitors over the printed circuit
board will improve decoupling. Multiple vias should be used
to connect the decoupling capacitors to the power planes. A
10 µF (35 V) or greater solid tantalum capacitor should be
connected at the power entry point on the printed circuit
board between the supply and ground.
PC BOARD CONSIDERATIONS
Use at least 4 PCB layers (top to bottom); LVDS signals,
ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL
may couple onto the LVDS lines. It is best to put TTL and
LVDS signals on different layers which are isolated by a
power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side)
connectors as possible.
DIFFERENTIAL TRACES
Use controlled impedance traces which match the differential impedance of your transmission medium (i.e. cable) and
termination resistor. Run the differential pair trace lines as
close together as possible as soon as they leave the IC
(stubs should be
reflections and ensure noise is coupled as common-mode.
In fact, we have seen that differential signals which are 1 mm
apart radiate far less noise than traces 3 mm apart since
<
10 mm long). This will help eliminate
magnetic field cancellation is much better with the closer
traces. In addition, noise induced on the differential lines is
much more likely to appear as common-mode which is rejected by the receiver.
Match electrical lengths between traces to reduce skew.
Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field
cancellation benefits of differential signals and EMI will result. (Note the velocity of propagation, v = c/Er where c (the
speed of light) = 0.2997 mm/ps or 0.0118 in/ps). Do not rely
solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and
provide isolation for the differential lines. Minimize the number or vias and other discontinuities on the line.
Avoid 90˚ turns (these cause impedance discontinuities).
Use arcs or 45˚ bevels.
Within a pair of traces, the distance between the two traces
should be minimized to maintain common-mode rejection of
the receivers. On the printed circuit board, this distance
should remain constant to avoid discontinuities in differential
impedance. Minor violations at connection points are allowable.
TERMINATION
Use a termination resistor which best matches the differential impedance or your transmission line. The resistor should
be between 90 Ω and 130 Ω. Remember that the current
mode outputs need the termination resistor to generate the
differential voltage. LVDS will not work without resistor termination. Typically, connecting a single resistor across the
pair at the receiver end will suffice.
Surface mount 1% to 2% resistors are best. PCB stubs,
component lead, and the distance from the termination to the
receiver inputs should be minimized. The distance between
the termination resistor and the receiver should be
(12 mm MAX).
PROBING LVDS TRANSMISSION LINES
Always use high impedance (
<
2 pF) scope probes with a wide bandwidth (1 GHz)
(
scope. Improper probing will give deceiving results.
CABLES AND CONNECTORS, GENERAL COMMENTS
When choosing cable and connectors for LVDS it is important to remember:
Use controlled impedance media. The cables and connectors you use should have a matched differential impedance
of about 100 Ω. They should not introduce major impedance
discontinuities.
Balanced cables (e.g. twisted pair) are usually better than
unbalanced cables (ribbon cable, simple coax.) for noise
reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to
pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver.
FAIL-SAFE FEATURE
An LVDS receiver is a high gain, high speed device that
amplifies a small differential signal (20 mV) to CMOS logic
levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing
as a valid signal.
>
100 kΩ), low capacitance
<
10 mm
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Applications Information (Continued)
The receiver’s internal fail-safe circuitry is designed to
source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for
floating receiver inputs.
The DS90LV049H has two receivers, and if an application
requires a single receiver, the unused receiver inputs should
be left OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high value
pull up and pull down current sources to set the output to a
HIGH state. This internal circuitry will guarantee a HIGH,
stable output state for open inputs.
Pin Descriptions
Pin No. Name Description
10, 11 D
6, 7 D
5, 8 D
2, 3 R
1, 4 R
14, 15 R
OUT+
OUT−
IN+
IN-
OUT
9, 16 EN, EN
12 V
DD
13 GND Ground pin.
Driver input pins, LVCMOS levels. There is a pull-down current
IN
source present.
Non-inverting driver output pins, LVDS levels.
Inverting driver output pins, LVDS levels.
Non-inverting receiver input pins, LVDS levels. There is a pull-up
current source present.
Inverting receiver input pins, LVDS levels. There is a pull-down
current source present.
Receiver output pins, LVCMOS levels.
Enable and Disable pins. There are pull-down current sources
present at both pins.
Power supply pin.
DS90LV049H
External lower value pull up and pull down resistors (for a
stronger bias) may be used to boost fail-safe in the presence
of higher noise levels. The pull up and pull down resistors
should be in the 5 kΩ to 15 kΩ range to minimize loading and
waveform distortion to the driver. The common-mode bias
point should be set to approximately 1.2 V (less than 1.75 V)
to be compatible with the internal circuitry.
For more information on failsfe biasing of LVDS interfaces
please refer to AN-1194.
Typical Performance Curves
Differential Output Voltage
vs Load Resistor
20161719
Power Supply Current
vs Frequency
20161721
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead (0.100" Wide) Molded Thin Shrink Small Outline Package, JEDEC
Order Number DS90LV049HMT
Order Number DS90LV049HMTX (Tape and Reel)
NS Package Number MTC16
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
DS90LV049H High Temperature 3V LVDS Dual Line Driver and Receiver Pair
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
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provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
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