National Semiconductor DS90LV018A Technical data

DS90LV018A 3V LVDS Single CMOS Differential Line Receiver

January 2003

General Description

The DS90LV018A is a single CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.

The DS90LV018A accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The receiver also supports open, shorted and terminated (100Ω) input fail-safe. The receiver output will be HIGH for all fail-safe conditions. The DS90LV018A has a flow-through design for easy PCB layout.

The DS90LV018A and companion LVDS line driver provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications.

Connection Diagram

SOIC

10007801

Order Number DS90LV018ATM

See NS Package Number M08A

Features

n>400 Mbps (200 MHz) switching rates n 50 ps differential skew (typical) n 2.5 ns maximum propagation delay n 3.3V power supply design n Flow-through pinout n Power down high impedance on LVDS inputs n Low Power design (18mW n Interoperable with existing 5V LVDS networks n Accepts small swing (350 mV typical) differential signal

levels

n Supports open, short and terminated input fail-safe n Conforms to ANSI/TIA/EIA-644 Standard n Industrial temperature operating range

(−40˚C to +85˚C)

n Available in SOIC package

3.3V static)

Truth Table

INPUTS OUTPUT

+]−[RIN−] R

VID≥ 0.1V H

≤ −0.1V L

Full Fail-safe

OPEN/SHORT H

or Terminated

OUT

Functional Diagram

10007802

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

DS90LV018A

Supply Voltage (V

Input Voltage (R

Output Voltage (R

Maximum Package Power Dissipation

M Package 1025 mW

Derate M Package 8.2 mW/˚C above +25˚C

Storage Temperature Range −65˚C to +150˚C

Lead Temperature Range Soldering

) −0.3V to +4V

+, RIN−) −0.3V to +3.9V

) −0.3V to (VCC+ 0.3V)

OUT

+25˚C

Maximum Junction Temperature +150˚C

ESD Rating (Note 4)

(HBM 1.5 kΩ, 100 pF) ≥ 7kV

(EIAJ 0Ω, 200 pF) ≥ 500 V

Recommended Operating

Conditions

Min Typ Max Units

Supply Voltage (V

) +3.0 +3.3 +3.6 V

Receiver Input Voltage GND 3.0 V

Operating Free Air

Temperature (T

) −40 25 +85 ˚C

(4 sec.) +260˚C

Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 2, 3)

Symbol Parameter Conditions Pin Min Typ Max Units

Differential Input High Threshold VCM= +1.2V, 0V, 3V (Note 11) RIN+, +100 mV

Differential Input Low Threshold RIN− −100 mV

Input Current VIN= +2.8V VCC= 3.6V or 0V −10

= 0V −10

= +3.6V VCC= 0V -20 +20 µA

Output High Voltage IOH= −0.4 mA, VID= +200 mV R

= −0.4 mA, Inputs terminated 2.7 3.1 V

= −0.4 mA, Inputs shorted 2.7 3.1 V

2.7 3.1 V

OUT

1 +10 µA

Output Low Voltage IOL= 2 mA, VID= −200 mV 0.3 0.5 V

Output Short Circuit Current V

= 0V (Note 5) −15 −50 −100 mA

OUT

Input Clamp Voltage ICL= −18 mA −1.5 −0.8 V

No Load Supply Current Inputs Open V

5.4 9 mA

Switching Characteristics

VCC= +3.3V±10%, TA= −40˚C to +85˚C (Notes 6, 7)

Symbol Parameter Conditions Min Typ Max Units

PHLD

PLHD

SKD1

SKD3

SKD4

TLH

THL

MAX

Differential Propagation Delay High to Low CL= 15 pF 1.0 1.6 2.5 ns

Differential Propagation Delay Low to High VID= 200 mV 1.0 1.7 2.5 ns

Differential Pulse Skew |t

PHLD−tPLHD

| (Note 8) (Figure 1 and Figure 2) 0 50 400 ps

Differential Part to Part Skew (Note 9) 0 1.0 ns

Differential Part to Part Skew (Note 10) 0 1.5 ns

Rise Time 325 800 ps

Fall Time 225 800 ps

Maximum Operating Frequency (Note 12) 200 250 MHz

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified (such as V

Note 3: All typicals are given for: V

Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF) ≥ 7kV

EIAJ (0Ω, 200 pF) ≥ 500V

Note 5: Output short circuit current (I exceed maximum junction temperature specification.

Note 6: C

Note 7: Generator waveform for all tests unless otherwise specified:f=1MHz, Z

Note 8: t

Note 9: t

and within 5˚C of each other within the operating temperature range.

SKD1

SKD3

includes probe and jig capacitance.

is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel.

, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same V

= +3.3V and TA= +25˚C.

) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not

=50Ω,trand tf(0% to 100%) ≤ 3 ns for RIN.

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Switching Characteristics (Continued)

Note 10: t

recommended operating temperature and voltage ranges, and across process distribution. t

Note 11: V than 100 mV when V

Note 12: f cycle, V

, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the

SKD4

is always higher than RIN+ and RIN− voltage. RIN+ and RIN− are allowed to have voltage range −0.05V to +3.05V. VIDis not allowed to be greater

MAX

(max 0.4V), VOH(min 2.7V), load = 15 pF (stray plus probes).

=0Vor3V.

generator input conditions: tr=t

1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35V peak to peak). Output criteria: 60%/40% duty

Parameter Measurement Information

FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit

is defined as |Max − Min| differential propagation delay.

SKD4

10007803

DS90LV018A

FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms

Typical Application

Balanced System

FIGURE 3. Point-to-Point Application

Applications Information

General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner’s Manual (lit #550062-001), AN808, AN1035, AN977, AN971, AN916, AN805, AN903.

LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 3. This configuration provides a clean signaling environment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic

10007804

10007805

impedance of the media is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to the receiver input pins as possible. The termination resistor converts the driver output (current mode) into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account.

The DS90LV018A differential line receiver is capable of de-

tecting signals as low as 100 mV, over a

1V common-mode

range centered around +1.2V. This is related to the driver

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