National Semiconductor DS90LV018A Technical data

DS90LV018A
3V LVDS Single CMOS Differential Line Receiver

DS90LV018A 3V LVDS Single CMOS Differential Line Receiver

January 2003

General Description

The DS90LV018A is a single CMOS differential line receiver
designed for applications requiring ultra low power dissipa­tion, low noise and high data rates. The device is designed to
support data rates in excess of 400 Mbps (200 MHz) utilizing
Low Voltage Differential Signaling (LVDS) technology.

The DS90LV018A accepts low voltage (350 mV typical) dif­ferential input signals and translates them to 3V CMOS
output levels. The receiver also supports open, shorted and
terminated (100Ω) input fail-safe. The receiver output will be
HIGH for all fail-safe conditions. The DS90LV018A has a
flow-through design for easy PCB layout.

The DS90LV018A and companion LVDS line driver provide a
new alternative to high power PECL/ECL devices for high
speed point-to-point interface applications.

Connection Diagram

SOIC

10007801

Order Number DS90LV018ATM

See NS Package Number M08A

Features

n>400 Mbps (200 MHz) switching rates
n 50 ps differential skew (typical)
n 2.5 ns maximum propagation delay
n 3.3V power supply design
n Flow-through pinout
n Power down high impedance on LVDS inputs
n Low Power design (18mW
n Interoperable with existing 5V LVDS networks
n Accepts small swing (350 mV typical) differential signal

levels

n Supports open, short and terminated input fail-safe
n Conforms to ANSI/TIA/EIA-644 Standard
n Industrial temperature operating range

(−40˚C to +85˚C)

n Available in SOIC package

@

3.3V static)

Truth Table

INPUTS OUTPUT

[R

+]−[RIN−] R

IN

VID≥ 0.1V H

V

≤ −0.1V L

ID

Full Fail-safe

OPEN/SHORT H

or Terminated

OUT

Functional Diagram

10007802

© 2003 National Semiconductor Corporation DS100078 www.national.com

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

DS90LV018A

Supply Voltage (V

Input Voltage (R

Output Voltage (R

Maximum Package Power Dissipation

M Package 1025 mW

Derate M Package 8.2 mW/˚C above +25˚C

Storage Temperature Range −65˚C to +150˚C

Lead Temperature Range Soldering

) −0.3V to +4V

CC

+, RIN−) −0.3V to +3.9V

IN

) −0.3V to (VCC+ 0.3V)

OUT

@

+25˚C

Maximum Junction Temperature +150˚C

ESD Rating (Note 4)

(HBM 1.5 kΩ, 100 pF) ≥ 7kV

(EIAJ 0Ω, 200 pF) ≥ 500 V

Recommended Operating

Conditions

Min Typ Max Units

Supply Voltage (V

) +3.0 +3.3 +3.6 V

CC

Receiver Input Voltage GND 3.0 V

Operating Free Air

Temperature (T

) −40 25 +85 ˚C

A

(4 sec.) +260˚C

Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 2, 3)

Symbol Parameter Conditions Pin Min Typ Max Units

V

TH

V

TL

I

IN

V

OH

V

OL

I

OS

V

CL

I

CC

Differential Input High Threshold VCM= +1.2V, 0V, 3V (Note 11) RIN+, +100 mV

Differential Input Low Threshold RIN− −100 mV

Input Current VIN= +2.8V VCC= 3.6V or 0V −10

V

= 0V −10

IN

V

= +3.6V VCC= 0V -20 +20 µA

IN

Output High Voltage IOH= −0.4 mA, VID= +200 mV R

I

= −0.4 mA, Inputs terminated 2.7 3.1 V

OH

I

= −0.4 mA, Inputs shorted 2.7 3.1 V

OH

2.7 3.1 V

OUT

±

1 +10 µA

±

1 +10 µA

Output Low Voltage IOL= 2 mA, VID= −200 mV 0.3 0.5 V

Output Short Circuit Current V

= 0V (Note 5) −15 −50 −100 mA

OUT

Input Clamp Voltage ICL= −18 mA −1.5 −0.8 V

No Load Supply Current Inputs Open V

CC

5.4 9 mA

Switching Characteristics

VCC= +3.3V±10%, TA= −40˚C to +85˚C (Notes 6, 7)

Symbol Parameter Conditions Min Typ Max Units

t

PHLD

t

PLHD

t

SKD1

t

SKD3

t

SKD4

t

TLH

t

THL

f

MAX

Differential Propagation Delay High to Low CL= 15 pF 1.0 1.6 2.5 ns

Differential Propagation Delay Low to High VID= 200 mV 1.0 1.7 2.5 ns

Differential Pulse Skew |t

PHLD−tPLHD

| (Note 8) (Figure 1 and Figure 2) 0 50 400 ps

Differential Part to Part Skew (Note 9) 0 1.0 ns

Differential Part to Part Skew (Note 10) 0 1.5 ns

Rise Time 325 800 ps

Fall Time 225 800 ps

Maximum Operating Frequency (Note 12) 200 250 MHz

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise
specified (such as V

Note 3: All typicals are given for: V

Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF) ≥ 7kV

EIAJ (0Ω, 200 pF) ≥ 500V

Note 5: Output short circuit current (I
exceed maximum junction temperature specification.

Note 6: C

Note 7: Generator waveform for all tests unless otherwise specified:f=1MHz, Z

Note 8: t

Note 9: t

and within 5˚C of each other within the operating temperature range.

L

SKD1

SKD3

).

ID

includes probe and jig capacitance.

is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel.

, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same V

= +3.3V and TA= +25˚C.

CC

) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not

OS

=50Ω,trand tf(0% to 100%) ≤ 3 ns for RIN.

O

CC

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Switching Characteristics (Continued)

Note 10: t

recommended operating temperature and voltage ranges, and across process distribution. t

Note 11: V
than 100 mV when V

Note 12: f
cycle, V

, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the

SKD4

is always higher than RIN+ and RIN− voltage. RIN+ and RIN− are allowed to have voltage range −0.05V to +3.05V. VIDis not allowed to be greater

CC

MAX

(max 0.4V), VOH(min 2.7V), load = 15 pF (stray plus probes).

OL

=0Vor3V.

CM

generator input conditions: tr=t

<

1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35V peak to peak). Output criteria: 60%/40% duty

f

Parameter Measurement Information

FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit

is defined as |Max − Min| differential propagation delay.

SKD4

10007803

DS90LV018A

FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms

Typical Application

Balanced System

FIGURE 3. Point-to-Point Application

Applications Information

General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner’s Manual (lit #550062-001), AN808,
AN1035, AN977, AN971, AN916, AN805, AN903.

LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 3. This configuration provides a clean signaling
environment for the fast edge rates of the drivers. The re­ceiver is connected to the driver through a balanced media
which may be a standard twisted pair cable, a parallel pair
cable, or simply PCB traces. Typically the characteristic

10007804

10007805

impedance of the media is in the range of 100Ω. A termina­tion resistor of 100Ω should be selected to match the media,
and is located as close to the receiver input pins as possible.
The termination resistor converts the driver output (current
mode) into a voltage that is detected by the receiver. Other
configurations are possible such as a multi-receiver configu­ration, but the effects of a mid-stream connector(s), cable
stub(s), and other impedance discontinuities as well as
ground shifting, noise margin limits, and total termination
loading must be taken into account.

The DS90LV018A differential line receiver is capable of de-

±

tecting signals as low as 100 mV, over a

1V common-mode

range centered around +1.2V. This is related to the driver

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Applications Information (Continued)

offset voltage which is typically +1.2V. The driven signal is
centered around this voltage and may shift
center point. The

DS90LV018A

potential difference between the driver’s ground reference
and the receiver’s ground reference, the common-mode ef­fects of coupled noise, or a combination of the two. The AC
parameters of both receiver input pins are optimized for a
recommended operating input voltage range of 0V to +2.4V
(measured from each pin to ground). The device will still
operate for receivers input voltages up to V

will turn on the ESD protection circuitry which will clamp

V

CC

the bus voltages.

POWER DECOUPLING RECOMMENDATIONS

Bypass capacitors must be used on power pins. Use high
frequency ceramic (surface mount is recommended) 0.1µF
and 0.001µF capacitors in parallel at the power supply pin
with the smallest value capacitor closest to the device supply
pin. Additional scattered capacitors over the printed circuit
board will improve decoupling. Multiple vias should be used
to connect the decoupling capacitors to the power planes. A
10µF (35V) or greater solid tantalum capacitor should be
connected at the power entry point on the printed circuit
board between the supply and ground.

PC BOARD CONSIDERATIONS

Use at least 4 PCB board layers (top to bottom): LVDS
signals, ground, power, TTL signals.

Isolate TTL signals from LVDS signals, otherwise the TTL
signals may couple onto the LVDS lines. It is best to put TTL
and LVDS signals on different layers which are isolated by a
power/ground plane(s).

Keep drivers and receivers as close to the (LVDS port side)
connectors as possible.

DIFFERENTIAL TRACES

Use controlled impedance traces which match the differen­tial impedance of your transmission medium (ie. cable) and
termination resistor. Run the differential pair trace lines as
close together as possible as soon as they leave the IC
(stubs should be
reflections and ensure noise is coupled as commo-mode. In
fact, we have seen that differential signals which are 1mm
apart radiate far less noise than traces 3mm apart since
magnetic field cancellation is much better with the closer
traces. In addition, noise induced on the differential lines is
much more likely to appear as common-mode which is re­jected by the receiver.

Match electrical lengths between traces to reduce skew.
Skew between the signals of a pair means a phase differ­ence between signals which destroys the magnetic field
cancellation benefits of differential signals and EMI will re­sult! (Note that the velocity of propagation,v=c/E
(the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not
rely solely on the autoroute function for differential traces.
Carefully review dimensions to match differential impedance
and provide isolation for the differential lines. Minimize the
number of vias and other discontinuities on the line.

Avoid 90˚ turns (these cause impedance discontinuities).
Use arcs or 45˚ bevels.

Within a pair of traces, the distance between the two traces
should be minimized to maintain common-mode rejection of
the receivers. On the printed circuit board, this distance

±

1V shifting may be the result of a ground

<

10mm long). This will help eliminate

±

1V around this

, but exceeding

CC

where c

r

should remain constant to avoid discontinuities in differential
impedance. Minor violations at connection points are allow­able.

TERMINATION

Use a termination resistor which best matches the differen­tial impedance or your transmission line. The resistor should
be between 90Ω and 130Ω. Remember that the current
mode outputs need the termination resistor to generate the
differential voltage. LVDS will not work without resistor ter­mination. Typically, connecting a single resistor across the
pair at the receiver end will suffice.

Surface mount 1% - 2% resistors are the best. PCB stubs,
component lead, and the distance from the termination to the
receiver inputs should be minimized. The distance between
the termination resistor and the receiver should be
(12mm MAX).

FAIL-SAFE FEATURE

The LVDS receiver is a high gain, high speed device that
amplifies a small differential signal (20mV) to CMOS logic
levels. Due to the high gain and tight threshold of the re­ceiver, care should be taken to prevent noise from appearing
as a valid signal.

The receiver’s internal fail-safe circuitry is designed to
source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for
floating, terminated or shorted receiver inputs.

1. Open Input Pins. The DS90LV018A is a single receiver
device. Do not tie the receiver inputs to ground or any
other voltages. The input is biased by internal high value
pull up and pull down resistors to set the output to a
HIGH state. This internal circuitry will guarantee a HIGH,
stable output state for open inputs.

2. Terminated Input. If the driver is disconnected (cable
unplugged), or if the driver is in a power-off condition,
the receiver output will again be in a HIGH state, even
with the end of cable 100Ω termination resistor across
the input pins. The unplugged cable can become a
floating antenna which can pick up noise. If the cable
picks up more than 10mV of differential noise, the re­ceiver may see the noise as a valid signal and switch. To
insure that any noise is seen as common-mode and not
differential, a balanced interconnect should be used.
Twisted pair cable will offer better balance than flat
ribbon cable.

3. Shorted Inputs. If a fault condition occurs that shorts
the receiver inputs together, thus resulting in a 0V differ­ential input voltage, the receiver output will remain in a
HIGH state. Shorted input fail-safe is not supported
across the common-mode range of the device (GND to

2.4V). It is only supported with inputs shorted and no
external common-mode voltage applied.

External lower value pull up and pull down resistors (for a
stronger bias) may be used to boost fail-safe in the presence
of higher noise levels. The pull up and pull down resistors
should be in the 5kΩ to 15kΩ range to minimize loading and
waveform distortion to the driver. The common-mode bias
point should be set to approximately 1.2V (less than 1.75V)
to be compatible with the internal circuitry.

PROBING LVDS TRANSMISSION LINES

>

Always use high impedance (

<

2 pF) scope probes with a wide bandwidth (1 GHz)

(
scope. Improper probing will give deceiving results.

100kΩ), low capacitance

<

10mm

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Applications Information (Continued)

CABLES AND CONNECTORS, GENERAL COMMENTS

When choosing cable and connectors for LVDS it is impor­tant to remember:

Use controlled impedance media. The cables and connec­tors you use should have a matched differential impedance
of about 100Ω. They should not introduce major impedance
discontinuities.

Balanced cables (e.g. twisted pair) are usually better than
unbalanced cables (ribbon cable, simple coax) for noise

Pin Descriptions

Pin No. Name Description

1R

2R

7R

8V

5 GND Ground pin

3, 4, 6 NC No connection

- Inverting receiver input pin

IN

+ Non-inverting receiver input pin

IN

Receiver output pin

OUT

Power supply pin, +3.3V±0.3V

CC

Ordering Information

Operating Package Type/ Order Number

Temperature Number

−40˚C to +85˚C SOP/M08A DS90LV018ATM

reduction and signal quality. Balanced cables tend to gener­ate less EMI due to field canceling effects and also tend to
pick up electromagnetic radiation a common-mode (not dif­ferential mode) noise which is rejected by the receiver.

<

For cable distances
work effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3
(category 3) twisted pair cable works well, is readily available
and relatively inexpensive.

0.5M, most cables can be made to

DS90LV018A

Typical Performance Characteristics

Output High Voltage vs

Power Supply Voltage

10007807

Output Low Voltage vs

Power Supply Voltage

10007808

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Typical Performance Characteristics (Continued)

DS90LV018A

Output Short Circuit Current vs

Power Supply Voltage

Power Supply Current

vs Frequency

10007809

Differential Transition Voltage vs

Power Supply Voltage

10007810

Power Supply Current vs

Ambient Temperature

Differential Propagation Delay vs

Power Supply Voltage

10007813 10007814

10007811

10007812

Differential Propagation Delay vs

Ambient Temperature

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Typical Performance Characteristics (Continued)

DS90LV018A

Differential Skew vs

Power Supply Voltage

10007815 10007816

Differential Propagation Delay vs

Differential Input Voltage

Differential Skew vs

Ambient Temperature

Differential Propagation Delay vs

Common-Mode Voltage

Transition Time vs

Power Supply Voltage

10007817 10007818

Transition Time vs

Ambient Temperature

10007819 10007820

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Typical Performance Characteristics (Continued)

DS90LV018A

Differential Propagation Delay

vs Load

Differential Propagation Delay

vs Load

Transition Time

vs Load

10007823

10007822

Transition Time

vs Load

10007821

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10007824

Physical Dimensions inches (millimeters)

unless otherwise noted

DS90LV018A 3V LVDS Single CMOS Differential Line Receiver

8-Lead (0.150" Wide) Molded Small Outline Package, JEDEC

Order Number DS90LV018ATM

NS Package Number M08A

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