National Semiconductor DS90CR483A Technical data

DS90CR483A / DS90CR484A
48-Bit LVDS Channel Link SER/DES – 33 - 112 MHz

General Description

The DS90CR483A transmitter converts 48 bits of CMOS/TTL
data into eight LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in par­allel with the data streams over a ninth LVDS link. Every cycle
of the transmit clock 48 bits of input data are sampled and
transmitted. The DS90CR484A receiver converts the LVDS
data streams back into 48 bits of CMOS/TTL data. At a trans­mit clock frequency of 112MHz, 48 bits of TTL data are
transmitted at a rate of 672Mbps per LVDS data channel. Us­ing a 112MHz clock, the data throughput is 5.38Gbit/s (672M­bytes/s).

The multiplexing of data lines provides a substantial cable re­duction. Long distance parallel single-ended buses typically
require a ground wire per active signal (and have very limited
noise rejection capability). Thus, for a 48-bit wide data and
one clock, up to 98 conductors are required. With this Channel
Link chipset as few as 19 conductors (8 data pairs, 1 clock
pair and a minimum of one ground) are needed. This provides
an 80% reduction in cable width, which provides a system
cost savings, reduces connector physical size and cost, and
reduces shielding requirements due to the cables' smaller
form factor.

The 48 CMOS/TTL inputs can support a variety of signal
combinations. For example, 6 8-bit words or 5 9-bit (byte +
parity) and 3 controls.

The DS90CR483A/DS90CR484A chipset is improved over
prior generations of Channel Link devices and offers higher
bandwidth support and longer cable drive with three areas of
enhancement. To increase bandwidth, the maximum clock
rate is increased to 112 MHz and 8 serialized LVDS outputs
are provided. Cable drive is enhanced with a user selectable

pre-emphasis feature that provides additional output current
during transitions to counteract cable loading effects. Option­al DC balancing on a cycle-to-cycle basis, is also provided to
reduce ISI (Inter-Symbol Interference). With pre-emphasis
and DC balancing, a low distortion eye-pattern is provided at
the receiver end of the cable. A cable deskew capability has
been added to deskew long cables of pair-to-pair skew of up
to +/−1 LVDS data bit time (up to 80 MHz Clock Rate). These
three enhancements allow cables 5+ meters in length to be
driven.

The chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.

For more details, please refer to the “Applications Informa­tion” section of this datasheet.

Features

Up to 5.38 Gbits/sec bandwidth

■

33 MHz to 112 MHz input clock support

■

LVDS SER/DES reduces cable and connector size

■

Pre-emphasis reduces cable loading effects

■

DC balance data transmission provided by transmitter

■

reduces ISI distortion
Cable Deskew of +/−1 LVDS data bit time (up to 80 MHz

■

Clock Rate)
5V Tolerant TxIN and control input pins

■

Flow through pinout for easy PCB design

■

+3.3V supply voltage

■

Transmitter rejects cycle-to-cycle jitter

■

Conforms to ANSI/TIA/EIA-644-1995 LVDS Standard

■

Both devices are available in 100 lead TQFP package

■

DS90CR483A/DS90CR484A 48-Bit LVDS Channel Link SER/DES — 33 - 112 MHz

April 4, 2008

Generalized Block Diagrams

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© 2008 National Semiconductor Corporation 300592 www.national.com

Generalized Transmitter Block Diagram

DS90CR483A/DS90CR484A

Generalized Receiver Block Diagram

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Ordering Information

Order Number Function Package

DS90CR483AVJD Transmitter (Serializer) VJD100A

DS90CR484AVJD Receiver (Deserializer) VJD100A

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DS90CR483A/DS90CR484A

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (VCC)

CMOS/TTL Input Voltage −0.3V to +5.5V
LVCMOS/TTL Output

Voltage

−0.3V to (VCC + 0.3V)

LVDS Receiver Input
Voltage −0.3V to +3.6V

LVDS Driver Output
Voltage −0.3V to +3.6V

LVDS Output Short
Circuit Duration Continuous

Junction Temperature +150°C
Storage Temperature −65°C to +150°C
Lead Temperature
(Soldering, 4 sec.)
100L TQFP +260°C
Maximum Package Power Dissipation Capacity @ 25°

C
100 TQFP Package:
DS90CR483AVJD 2.3W

−0.3V to +4V

DS90CR484AVJD 2.3W
Package Derating:
DS90CR483AVJD 18.1mW/°C above +25°C
DS90CR484AVJD 18.1mW/°C above +25°C
ESD Rating:
DS90CR483A

(HBM, 1.5kΩ, 100pF) > 6 kV

(EIAJ, 0Ω, 200pF) > 300 V
DS90CR484A

(HBM, 1.5kΩ, 100pF) > 2 kV

(EIAJ, 0Ω, 200pF) > 200 V

Recommended Operating Conditions

Min Nom Max Units

Supply Voltage (VCC) 3.0 3.3 3.6 V

Operating Free Air
Temperature (T

A)

Receiver Input Range 0 2.4 V
Supply Noise Voltage 100 mV

Input Clock (TX) 33 112 MHz

−10 +25 +70 °C

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

CMOS/TTL DC SPECIFICATIONS

V

IH

V

IL

V

OH

V

OL

V

CL

I

IN

I

OS

High Level Input Voltage 2.0 V

Low Level Input Voltage GND 0.8 V

High Level Output
Voltage

IOH = −0.4 mA 2.7 3.3 V

IOH = −2mA 2.7 2.85 V

Low Level Output Voltage IOL = 2 mA 0.1 0.3 V

Input Clamp Voltage ICL = −18 mA −0.79 −1.5 V

Input Current VIN = 0.4V, 2.5V or V

CC

+1.8 +15 µA

VIN = GND −15 0 µA

Output Short Circuit

V

= 0V −120 mA

OUT

Current

p-p

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Symbol Parameter Conditions Min Typ Max Units

LVDS DRIVER DC SPECIFICATIONS

|VOD| Differential Output

RL = 100Ω

250 345 450 mV

Voltage

ΔV

OD

Change in VOD between

35 mV
Complimentary Output
States

V

OS

ΔV

OS

DS90CR483A/DS90CR484A

I

OS

Offset Voltage 1.125 1.25 1.375 V

Change in VOS between

35 mV
Complimentary Output
States

Output Short Circuit

V

= 0V, RL = 100Ω

OUT

−3.5 −5 mA

Current

I

OZ

Output TRI-STATE

PD = 0V, V

= 0V or V

OUT

CC

±1 ±10 µA
Current

LVDS RECEIVER DC SPECIFICATIONS

V

TH

Differential Input High

VCM = +1.2V +100 mV

Threshold

V

TL

Differential Input Low

−100 mV

Threshold

I

IN

Input Current VIN = +2.4V, VCC = 3.6V ±10 µA

VIN = 0V, VCC = 3.6V ±10 µA

TRANSMITTER SUPPLY CURRENT

ICCTW Transmitter Supply

Current
Worst Case

RL = 100Ω, CL = 5 pF,
BAL = High,
Worst Case Pattern

f = 33 MHz 91.4 140 mA

f = 66 MHz 106 160 mA

f = 112 MHz 155 210 mA

(Figures 1, 2)

ICCTZ Transmitter Supply

Current
Power Down

PD = Low 5 50 µA

Driver Outputs in TRI-STATE during power down
Mode

RECEIVER SUPPLY CURRENT

ICCRW Receiver Supply Current

Worst Case

ICCRZ Receiver Supply Current

Power Down

CL = 8 pF, BAL = High,
Worst Case Pattern
(Figures 1, 3)

f = 33 MHz 125 150 mA

f = 66 MHz 200 210 mA

f = 112 MHz 250 280 mA

PD = Low
Receiver Outputs stay low during power down mode.

20 100 µA

Recommended Transmitter Input Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Min Typ Max Units

TCIT TxCLK In Transition Time (Figure 4) 1.0 2.0 3.0 ns

TCIP High TxCLK In Period, PLLSEL = High Gear (Figure 5) 8.928 T 26.3 ns

TCIP Low TxCLK In Period, PLLSEL = Low Gear (Figure 5) 25 T 30.3 ns

TCIH TxCLK In High Time (Figure 5) 0.35T 0.5T 0.65T ns

TCIL TxCLK In Low Time (Figure 5) 0.35T 0.5T 0.65T ns

TXIT TxIN Transition Time 1.5 6.0 ns

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Transmitter Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Min Typ Max Units

LLHT LVDS Low-to-High Transition Time, (Figure 2),

PRE = 0.75V (disabled)

LVDS Low-to-High Transition Time, (Figure 2),
PRE = Vcc (max)

LHLT LVDS High-to-Low Transition Time, (Figure 2),

PRE = 0.75V (disabled)

LVDS High-to-Low Transition Time, (Figure 2),
PRE = Vcc (max)

TBIT Transmitter Bit Width 1/7 TCIP ns

TPPOS Transmitter Pulse Positions - Normalized f = 33 to 70

MHz

f = 70 to 112
MHz

TJCC Transmitter Jitter - Cycle-to-Cycle ((Note 8) 50 100 ps

TCCS TxOUT Channel to Channel Skew 40 ps

TSTC TxIN Setup to TxCLK IN, (Figure 5) 2.5 ns

THTC TxIN Hold to TxCLK IN, (Figure 5) 0 ns

TPDL Transmitter Propagation Delay - Latency, (Figure 7) 1.5(TCIP)+3.72 1.5(TCIP)+4.4 1.5(TCIP)+6.24 ns

TPLLS Transmitter Phase Lock Loop Set, (Figure 9) 10 ms

TPDD Transmitter Powerdown Delay, (Figure 11) 100 ns

0.14 0.7 ns

0.11 0.6 ns

0.16 0.8 ns

0.11 0.7 ns

−250 0 +250 ps

−200 0 +200 ps

DS90CR483A/DS90CR484A

Receiver Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Min Typ Max Units

CLHT CMOS/TTL Low-to-High Transition Time, (Figure 3), Rx

data out

CMOS/TTL Low-to-High Transition Time, (Figure 3), Rx
clock out

CHLT CMOS/TTL High-to-Low Transition Time, (Figure 3), Rx

data out

CMOS/TTL High-to-Low Transition Time, (Figure 3), Rx
clock out

RCOP RxCLK OUT Period, (Figure 6) 8.928 T 30.3 ns

RCOH RxCLK OUT High Time, (Figure 6),

(Note 4)

RCOL RxCLK OUT Low Time, (Figure 6),

(Note 4)

RSRC RxOUT Setup to RxCLK OUT, (Figure

6), (Note 4)

RHRC RxOUT Hold to RxCLK OUT, (Figure

6), (Note 4)

RPDL Receiver Propagation Delay - Latency, (Figure 8) 3(TCIP)+4.0 3(TCIP)+4.8 3(TCIP)+6.5 ns

RPLLS Receiver Phase Lock Loop Set, (Figure 10) 10 ms

RPDD Receiver Powerdown Delay, (Figure 12) 1 µs

f = 112 MHz 3.5 ns

f = 66 MHz 6.0 ns

f = 112 MHz 3.5 ns

f = 66 MHz 6.0 ns

f = 112 MHz 2.4 ns

f = 66 MHz 3.6 ns

f = 112 MHz 3.4 ns

f = 66 MHz 7.0 ns

2.0 ns

1.0 ns

2.0 ns

1.0 ns

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Chipset RSKM Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.(Notes 4, 7). See Applications Informa­tion section for more details on this parameter and how to apply it.

Symbol Parameter Min Typ Max Units

RSKM Receiver Skew Margin without Deskew

in non-DC Balance Mode, (Figure 13),
(Note 5)

RSKM Receiver Skew Margin without Deskew

DS90CR483A/DS90CR484A

in DC Balance Mode, (Figure 13),
(Note 5)

RSKMD Receiver Skew Margin with Deskew in

DC Balance, (Figure 14),
(Note 6)

RDR Receiver Deskew Range f = 80 MHz ±1 TBIT

RDSS Receiver Deskew Step Size f = 80 MHz 0.3TBIT ns

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.

Note 2: Typical values are given for VCC = 3.3V and T A = +25°C.

Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise

specified (except VTH, VTL, VOD and ΔVOD).

Note 4: The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges. This parameter is
functionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts have been bench tested to verify functional
performance.

Note 5: Receiver Skew Margin (RSKM) is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output pulse
positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS). This margin allows for LVDS interconnect skew,
inter-symbol interference (both dependent on type/length of cable) and clock jitter.

RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle, TJCC) + ISI (if any). See Applications Information section for more details.

Note 6: Receiver Skew Margin with Deskew (RSKMD) is defined as the valid data sampling region at the receiver inputs. The DESKEW function will constrain
the receiver’s sampling strobes to the middle half of the LVDS bit and removes (adjusts for) fixed interconnect skew. This margin (RSKMD) allows for inter-symbol
interference (dependent on type/length of cable), Transmitter Pulse Position (TPPOS) variance, and LVDS clock jitter (TJCC).

RSKMD ≥ ISI + TPPOS(variance) + source clock jitter (cycle to cycle). See Applications Information section for more details.

Note 7: Typical values for RSKM and RSKMD are applicable for fixed VCC and T A for the Transmitter and Receiver (both are assumed to be at the same V
and T A points).

Note 8: TJCC is a function of input clock quality and also PLLVCC noise. At 112MHz operation, with a +/−300ps input impulse at a 2us rate, TJCC has been
measured to be in the 70-80ps range (<100ps). With a nominal input clock quality (no input impulse jitter, jitter < 500kHz), TJCC is typically 50ps or less. For
RSKM/RSKMD calculations 100ps is typically used as the TJCC budget. See Clock Jitter discussion in the Applications Information section of this datasheet for
further information.

f = 112 MHz 170 ps

f = 100 MHz 170 240 ps

f = 85MHz 300 350 ps

f = 66MHz 300 350 ps

f = 112 MHz 170 ps

f = 100 MHz 170 200 ps

f = 85 MHz 250 300 ps

f = 66 MHz 250 300 ps

f = 50MHz 300 350 ps

f = 33 to 80 MHz 0.25TBIT ps

CC

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AC Timing Diagrams

FIGURE 1. “Worst Case” Test Pattern

Note 9: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.

DS90CR483A/DS90CR484A

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FIGURE 2. DS90CR483A (Transmitter) LVDS Output Load and Transition Times

FIGURE 3. DS90CR484A (Receiver) CMOS/TTL Output Load and Transition Times

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FIGURE 4. DS90CR483A (Transmitter) Input Clock Transition Time

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DS90CR483A/DS90CR484A

FIGURE 5. DS90CR483A (Transmitter) Setup/Hold and High/Low Times

FIGURE 6. DS90CR484A (Receiver) Setup/Hold and High/Low Times

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FIGURE 7. DS90CR483A (Transmitter) Propagation Delay - Latency

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