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DS90CR213/DS90CR214
21-Bit Channel Link—66 MHz
General Description
The DS90CR213 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. Aphase-locked transmitclock is transmitted in
parallel with the data streams over a fourth LVDSlink. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CR214 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 66MHz, 21bits ofTTL data are
transmitted at a rate of 462 Mbps per LVDS data channel.
Using a 66 MHz clock, the data throughput is 1.386 Gbit/s
(173 Mbytes/s).
The multiplexing of the data lines provides a substantial
cable reduction. Long distance parallel single-ended buses
typically require a ground wire per active signal (and have
very limited noise rejection capability).Thus, fora 21-bit wide
data and one clock, up to 44 conductors are required. With
the Channel Link chipset as few as 9 conductors (3 data
pairs, 1 clock pair and a minimum of one ground) are
needed. This provides an 80%reduction in required cable
Block Diagrams
July 1997
width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cable’s smaller form factor.
The 21 CMOS/TTL inputs can support a variety of signal
combinations. For example, 5 4-bit nibbles (byte + parity) or
2 9-bit (byte + 3 parity) and 1 control.
Features
n 66 MHz Clock Support
n Up to 173 Mbytes/s bandwidth
n Low power CMOS design (
n Power-down mode (
n Up to 1.386 Gbit/s data throughput
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n PLL requires no external components
n Low profile 48-lead TSSOP package
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS Standard
<
610 mW)
<
0.5 mW total)
DS90CR213/DS90CR214 21-Bit Channel Link—66 MHz
DS90CR213/DS90CR214
DS90CR213
DS012888-27
Order Number DS90CR213MTD
See NS Package Number MTD48
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS012888 www.national.com
Order Number DS90CR214MTD
See NS Package Number MTD48
DS90CR214
DS012888-1
1
PrintDate=1998/01/07 PrintTime=09:53:21 28561 ds012888 Rev. No. 5 cmserv
Proof 1
Pin Diagrams
DS90CR213
Typical Application
DS012888-21
DS90CR214
DS012888-22
DS012888-23
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor SalesOffice/
Distributors for availability and specifications.
Supply Voltage (V
CMOS/TTL Input Voltage −0.3V to (V
CMOS/TTL Output Voltage −0.3V to (V
LVDS Receiver Input Voltage −0.3V to (V
LVDS Driver Output Voltage −0.3V to (V
LVDS Output Short Circuit
Duration Continuous
Junction Temperature +150˚C
Storage Temperature −65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec) +260˚C
Maximum Package Power
Dissipation Capacity
MTD48 (TSSOP) Package:
DS90CR213
DS90CR214
) −0.3V to +6V
CC
CC
CC
CC
CC
+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)
@
25˚C
1.98W
1.89W
Package Derating:
DS90CR213 16 mW/˚C above +25˚C
DS90CR214 15 mW/˚C above +25˚C
ESD Rating (Note 4)
This device does not meet 2000V
Recommended Operating
Conditions
Supply Voltage (V
) 4.75 5.0 5.25 V
CC
Operating Free Air
Temperature (T
) −10 +25 +70 ˚C
A
Receiver Input Range 0 2.4 V
Supply Noise Voltage (V
Min Nom Max Units
) 100 mV
CC
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
CMOS/TTL DC SPECIFICATIONS
V
IH
V
IL
V
OH
V
OL
V
CL
I
IN
I
OS
LVDS DRIVER DC SPECIFICATIONS
V
OD
∆V
V
OS
∆V
I
OS
I
OZ
LVDS RECEIVER DC SPECIFICATIONS
V
TH
V
TL
I
IN
TRANSMITTER SUPPLY CURRENT
I
CCTW
I
CCTZ
High Level Input Voltage 2.0 V
Low Level Input Voltage GND 0.8 V
High Level Output Voltage I
Low Level Output Voltage I
Input Clamp Voltage I
Input Current V
Output Short Circuit Current V
Differential Output Voltage R
Change in VODbetween
OD
Complimentary Output States
=
−0.4 mA 3.8 4.9 V
OH
=
2 mA 0.1 0.3 V
OL
=
−18 mA −0.79 −1.5 V
CL
=
, GND, 2.5V or 0.4V
V
IN
CC
=
0V −120 mA
OUT
=
100Ω 250 290 450 mV
L
±
5.1
Offset Voltage 1.1 1.25 1.375 V
Change in Magnitude of V
OS
between Complimentary Output
OS
States
Output Short Circuit Current V
OUT
=
Output TRI-STATE®Current Powerdown=0V, V
Differential Input High Threshold V
=
CM
=
0V, R
100Ω −2.9 −5 mA
L
OUT
=
0V or V
±
CC
1
+1.2V +100 mV
Differential Input Low Threshold −100 mV
Input Current V
Transmitter Supply Current R
V
IN
IN
=
L
=
+2.4V, V
=
0V, V
100Ω,C
=
5.0V
CC
=
5.0V
CC
=
5 pF, f=32.5 MHz 49 63 mA
L
Worst Case Worst Case Pattern f=37.5 MHz 51 64 mA
(
Figure 1
and
Figure 2
)f=66 MHz 70 84 mA
Transmitter Supply Current Powerdown=Low
Power Down Driver Outputs in TRI-STATE under
125µA
Powerdown Mode
CC
±
10 µA
35 mV
35 mV
±
10 µA
±
10 µA
±
10 µA
P-P
V
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Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
RECEIVER SUPPLY CURRENT
I
CCRW
Receiver Supply Current C
=
8 pF, f=32.5 MHz 64 77 mA
L
Worst Case Worst Case Pattern f=37.5 MHz 70 85 mA
(
Figure 1
and
Figure 3
)f=66 MHz 110 140 mA
I
CCRZ
Receiver Supply Current Powerdown=Low
Power Down Receiver Outputs in Previous State during
110µA
Power Down Mode.
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF)
PLL V
All Other Pins ≥ 2000V
EIAJ (0Ω, 200 pF) ≥ 150V
Note 5: V
and ∆VOD).
OD
≥ 1000V
CC
previously referred as VCM.
OS
CC
=
5.0V and T
=
+25˚C.
A
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
Figure 2
LLHT LVDS Low-to-High Transition Time (
LHLT LVDS High-to-Low Transition Time (
TCIT TxCLK IN Transition Time (
Figure 4
TCCS TxOUT Channel-to-Channel Skew (Note 6) (
TPPos0 Transmitter Output Pulse Position for Bit 0 (
TPPos1 Transmitter Output Pulse Position for Bit 1 1.70 (1/7)Tclk 2.50 ns
TPPos2 Transmitter Output Pulse Position for Bit 2 3.60 (2/7)Tclk 4.50 ns
TPPos3 Transmitter Output Pulse Position for Bit 3 5.90 (3/7)Tclk 6.75 ns
TPPos4 Transmitter Output Pulse Position for Bit 4 8.30 (4/7)Tclk 9.00 ns
TPPos5 Transmitter Output Pulse Position for Bit 5 10.40 (5/7)Tclk 11.10 ns
TPPos6 Transmitter Output Pulse Position for Bit 6 12.70 (6/7)Tclk 13.40 ns
TCIP TxCLK IN Period (
TCIH TxCLK IN High Time (
TCIL TxCLK IN Low Time (
TSTC TxIN Setup to TxCLK IN (
THTC TxIN Hold to TxCLK IN (
TCCD TxCLK IN to TxCLK OUT Delay
TPLLS Transmitter Phase Lock Loop Set (
TPDD Transmitter Powerdown Delay (
Note 6: This limit based on bench characterization.
Figure 6
) 15 T 50 ns
Figure 6
) 0.35T 0.5T 0.65T ns
Figure 6
) 0.35T 0.5T 0.65T ns
Figure 6
) 5 3.5 ns
Figure 6
) 2.5 1.5 ns
@
25˚C, V
Figure 10
Figure 14
) 0.75 1.5 ns
Figure 2
) 0.75 1.5 ns
)8ns
Figure 5
) 350 ps
Figure 16
)
−0.30 0 0.30 ns
f=66 MHz
=
Figure 8
5.0V (
CC
) 3.5 8.5 ns
)10ms
) 100 ns
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
Figure 3
CLHT CMOS/TTL Low-to-High Transition Time (
CHLT CMOS/TTL High-to-Low Transition Time (
RSKM RxIN Skew Margin (Note 7) V
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=
5V,T
CC
A
PrintDate=1998/01/07 PrintTime=09:53:21 28561 ds012888 Rev. No. 5 cmserv Proof 4
) 2.5 4.0 ns
Figure 3
) 2.0 4.0 ns
=
25˚C(
Figure 17
)f=40 MHz 700 ps
f=66 MHz 600 ps
Receiver Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
Figure 7
RCOP RxCLK OUT Period (
RCOH RxCLK OUT High Time (
) 15 T 50 ns
Figure 7
)f
=
40 MHz 6 ns
f=66 MHz 4.3 5 ns
RCOL RxCLK OUT Low Time (
Figure 7
)f
=
40 MHz 10.5 ns
f=66 MHz 7.0 9 ns
RSRC RxOUT Setup to RxCLK OUT (
Figure 7
)f
=
40 MHz 4.5 ns
f=66 MHz 2.5 4.2 ns
RHRC RxOUT Hold to RxCLK OUT (
Figure 7
)f
=
40 MHz 6.5 ns
f=66 MHz 4 5.2 ns
RCCD RxCLK IN to RxCLK OUT Delay
RPLLS Receiver Phase Lock Loop Set (
RPDD Receiver Powerdown Delay (
Note 7: Receiver Skew Margin is definedas the valid data sampling region atthe receiver inputs. Thismargin takes into account for transmitter outputskew (TCCS)
and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle)
@
25˚C, V
Figure 11
Figure 15
=
Figure 9
5.0V (
CC
) 6.4 10.7 ns
)10ms
)1µs
AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern
DS012888-3
FIGURE 2. DS90CR213 (Transmitter) LVDS Output Load and Transition Times
DS012888-5
FIGURE 3. DS90CR214 (Receiver) CMOS/TTL Output Load and Transition Times
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DS012888-2
DS012888-4
DS012888-6
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AC Timing Diagrams (Continued)
FIGURE 4. DS90CR213 (Transmitter) Input Clock Transition Time
DS012888-7
Note 8: Measurements at V
Note 9: TCSS measured between earliest and latest LVDS edges.
Note 10: TxCLK Differential Low→High Edge
=
0V
diff
FIGURE 5. DS90CR213 (Transmitter) Channel-to-Channel Skew
FIGURE 6. DS90CR213 (Transmitter) Setup/Hold and High/Low Times
FIGURE 7. DS90CR214 (Receiver) Setup/Hold and High/Low Times
DS012888-8
DS012888-9
DS012888-10
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AC Timing Diagrams (Continued)
FIGURE 8. DS90CR213 (Transmitter) Clock In to Clock Out Delay
FIGURE 9. DS90CR214 (Receiver) Clock In to Clock Out Delay
DS012888-11
DS012888-12
FIGURE 10. DS90CR213 (Transmitter) Phase Lock Loop Set Time
DS012888-14
FIGURE 11. DS90CR214 (Receiver) Phase Lock Loop Set Time
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DS012888-13
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AC Timing Diagrams (Continued)
FIGURE 12. Seven Bits of LVDS in Once Clock Cycle
FIGURE 13. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR283)
DS012888-15
DS012888-16
DS012888-17
FIGURE 14. Transmitter Powerdown Delay
DS012888-18
FIGURE 15. Receiver Powerdown Delay
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AC Timing Diagrams (Continued)
FIGURE 16. Transmitter LVDS Output Pulse Position Measurement
DS012888-19
SW—Setup and Hold Time (Internal Data Sampling Window)
TCCS—Transmitter Output Skew
RSKM ≥ Cable Skew (Type, Length) + Source Clock Jitter (Cycle to Cycle)
Cable Skew—Typically 10 ps–40 ps per foot
DS012888-20
FIGURE 17. Receiver LVDS Input Skew Margin
DS90CR213 Pin Description—Channel Link Transmitter
Pin Name I/O No. Description
TxIN I 21 TTL level inputs.
TxOUT+ O 3 Positive LVDS differential data output.
TxOUT− O 3 Negative LVDS differentiaI data output.
TxCLK IN I 1 TTL level clock input. The rising edge acts as data strobe.
TxCLK OUT+ O 1 Positive LVDS differential clock output.
TxCLK OUT− O 1 Negative LVDS differential clock output.
PWR DOWN
V
CC
GND I 5 Ground pins for TTL inputs.
PrintDate=1998/01/07 PrintTime=09:53:22 28561 ds012888 Rev. No. 5 cmserv Proof 9
I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down.
I 4 Power supply pins for TTL inputs.
9 www.national.com
DS90CR213 Pin Description—Channel Link Transmitter (Continued)
Pin Name I/O No. Description
PLL V
CC
PLL GND I 2 Ground pins for PLL.
LVDS V
CC
LVDS GND I 3 Ground pins for LVDS outputs.
I 1 Power supply pin for PLL.
I 1 Power supply pin for LVDS outputs.
DS90CR214 Pin Description—Channel Link Receiver
Pin Name I/O No. Description
RxIN+ I 3 Positive LVDS differential data inputs.
RxIN− I 3 Negative LVDS differential data inputs.
RxOUT O 21 TTL level outputs.
RxCLK IN+ I 1 Positive LVDS differential clock input.
RxCLK IN− I 1 Negative LVDS differentiaI clock input.
RxCLK OUT O 1 TTL level clock output. The rising edge acts as data strobe.
PWR DOWN
V
CC
GND I 5 Ground pins for TTL outputs.
PLL V
CC
PLL GND I 2 Ground pin for PLL.
LVDS V
CC
LVDS GND I 3 Ground pins for LVDS inputs.
I 1 TTL Ievel input. Locks the previous receiver output state.
I 4 Power supply pins for TTL outputs.
I 1 Power supply for PLL.
I 1 Power supply pin for LVDS inputs.
Applications Information
The Channel Link devices are intended to be used in a wide
variety of data transmission applications. Depending upon
the application the interconnecting media may vary. For example, for lower data rate (clock rate) and shorter cable
<
lengths (
cal. For higher speed/long distance applications the media’s
performance becomes more critical. Certain cable constructions provide tighter skew (matched electrical length between the conductors and pairs).Twin-coax for example,has
been demonstrated at distances as great as 5 meters and
with the maximum data transfer of 1.38Gbit/s. Additional applications information can be found in the following National
Interface Application Notes:
AN-1041 Introduction to Channel Link
AN-1035 PCB Design Guidelines for LVDS and
AN-806 Transmission Line Theory
AN-905 Transmission Line Calculations and
AN-916 Cable Information
CABLES: A cable interface between the transmitter and receiver needs to support the differential LVDS pairs. The
21-bit CHANNEL LINK chipset (DS90CR213/214) requires
four pairs of signal wires and the 28-bit CHANNEL LINK
chipset (DS90CR283/284)requires five pairs of signalwires.
The ideal cable/connector interface would have a constant
100Ω differential impedance throughout the path. It is also
2m), the media electrical performance is less criti-
=
####
AN
Link Devices
Differential Impedance
Topic
recommended that cable skew remain below 350 ps (
MHz clock rate) to maintain a sufficient data sampling window at the receiver.
In addition to the four or five cable pairs that carry data and
clock, it is recommended to provide at least one additional
conductor (or pair) which connects ground between the
transmitter and receiver. This low impedance ground provides a common mode return path for thetwo devices.Some
of the more commonly used cable types for point-to-point applications include flat ribbon, flex, twisted pair and
Twin-Coax.Allare availablein avariety ofconfigurations and
options. Flat ribbon cable, flex and twisted pair generally perform well in short point-to-point applications while Twin-Coax
is good for short and long applications. When using ribbon
cable, it is recommended to place a ground line between
each differential pair to act as a barrier to noise coupling between adjacent pairs. For Twin-Coax cable applications, it is
recommended to utilize a shield on each cable pair. All extended point-to-point applications should also employ an
overall shield surrounding all cable pairs regardless of the
cable type. This overall shield results in improved transmission parameters such as faster attainable speeds, longer
distances between transmitter and receiver and reduced
problems associated with EMS or EMI.
The high-speed transport of LVDS signals has been demonstrated on several types of cables with excellent results.
However, the best overall performance has been seen when
using Twin-Coax cable. Twin-Coax has very low cable skew
and EMI due to its construction and double shielding. All of
the design considerations discussed here and listed in the
supplemental application notes provide the subsystem communications designer with many useful guidelines. It is rec-
@
66
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Applications Information (Continued)
ommended that the designer assess the tradeoffs of each
application thoroughly to arrive at a reliable and economical
cable solution.
BOARD LAYOUT: To obtain the maximum benefit from the
noise and EMI reductions of LVDS, attention should be paid
to the layout of differential lines. Lines of a differential pair
should always be adjacent to eliminate noise interference
from other signals and take full advantage of the noise canceling of the differential signals. The board designer should
also try to maintain equal length on signal traces for a given
differential pair. As with any high speed design, the impedance discontinuities should be limited (reduce the numbers
of vias and no 90 degree angles on traces). Any discontinuities which do occur on one signal line should be mirrored in
the other line of the differential pair. Care should be taken to
ensure thatthe differential trace impedance match the differential impedanceof the selected physical media (this impedance should also match the value of the termination resistor
that is connected across the differentialpair at the receiver’s
input). Finally, the location of the CHANNEL LINK TxOUT/
RxIN pins should be as close as possible to the board edge
so as to eliminate excessive pcb runs. All of these considerations will limit reflections and crosstalk which adversely effect high frequency performance and EMI.
UNUSED INPUTS: All unused inputs at the TxIN inputs of
the transmitter must be tied to ground. All unused outputs at
the RxOUT outputs of the receiver must then be left floating.
TERMINATION: Use of current mode drivers requires a terminating resistor across the receiver inputs. The CHANNEL
LINK chipset will normally require a single 100Ω resistor between the true and complement lines on each differential
pair of the receiver input. The actual value of the termination
resistor should be selected to match the differential mode
characteristic impedance (90Ω to 120Ω typical) of the cable.
Figure 18
shows an example. No additional pull-up or
pull-down resistors are necessary as with some other differential technologies such as PECL. Surface mount resistors
are recommended to avoidthe additionalinductance that accompanies leaded resistors. These resistors should be
placed as close as possible to the receiver input pins to reduce stubs and effectively terminate the differential lines.
DECOUPLING CAPACITORS: Bypassing capacitors are
needed to reduce the impact of switching noise which could
limit performance. For a conservative approach three
parallel-connected decouplingcapacitors (Multi-Layered Ceramic type in surface mount form factor) between each V
and the ground plane(s) are recommended. The three ca-
CC
pacitor values are 0.1 µF, 0.01µF and 0.001 µF.An example
is shown in
Figure 19
. The designer should employ wide
traces for power and ground and ensure each capacitor has
its own via to the ground plane. If board space is limiting the
number of bypass capacitors, the PLL V
the most filtering/bypassing. Next would be the LVDS V
pins and finally the logic VCCpins.
should receive
CC
CC
DS012888-24
FIGURE 18. LVDS Serialized Link Termination
width of 2.16 ns. Differential skew (∆t within one differential
pair), interconnect skew (∆t of one differential pair to another) and clock jitter will all reduce the available window for
sampling the LVDS serial data streams. Care must be taken
to ensure that the clock input to the transmitter be a clean
low noisesignal. Individual bypassing of each V
will minimizethe noise passed on to the PLL, thuscreating a
to ground
CC
low jitter LVDS clock. These measures provide more margin
for channel-to-channel skew and interconnect skew as a part
of the overall jitter/skew budget.
COMMON MODE vs. DIFFERENTIAL MODE NOISE MAR-
DS012888-25
FIGURE 19. CHANNEL LINK
Decoupling Configuration
CLOCK JITTER: The CHANNEL LINK devices employ a
PLLto generateand recoverthe clock transmitted across the
LVDS interface. The width of each bit in the serialized LVDS
data stream is one-seventh the clock period. For example, a
66 MHz clock has a period of 15 ns which results in a data bit
GIN: The typical signal swing for LVDS is 300 mV centered
at +1.2V. The CHANNEL LINK receiver supports a 100 mV
threshold therefore providing approximately 200 mV of differential noisemargin. Common mode protection isof more importance to the system’s operation due to the differential
data transmission. LVDS supports an input voltage range of
Ground to +2.4V. This allows for a
±
1.0V shifting of the center point due to ground potential differences and common
mode noise.
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Applications Information (Continued)
POWER SEQUENCING AND POWERDOWN MODE: Out-
puts of the CHANNEL LINK transmitter remain in TRI-STATE
until the power supply reaches 3V. Clock and data outputs
will begin to toggle 10 ms after V
the Powerdown pin is above2V.Either devicemay be placed
into a powerdown mode at any time by asserting the Powerdown pin (active low). Total power dissipation for each device will decrease to 5 µW (typical).
has reached 4.5V and
CC
The CHANNEL LINK chipset is designed to protect itself
from accidental loss of power to either the transmitter or receiver. If power to the transmit board is lost, the receiver
clocks (input and output)stop. The data outputs(RxOUT) retain the states they were in when the clocks stopped. When
the receiver board loses power, the receiver inputs are
shorted to V
(5 mA per input) by the fixed current mode drivers, thus
through an internal diode. Current is limited
CC
avoiding the potential for latchup when powering the device.
FIGURE 20. Single-Ended and Differential Waveforms
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DS012888-26
Book
Extract
End
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THIS PAGE IS IGNORED IN THE DATABOOK
13
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13
Proof 13
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Molded Thin Shrink Small Outline Package, JEDEC
NS Package Number MTD48
DS90CR213/DS90CR214 21-Bit Channel Link—66 MHz
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
PrintDate=1998/01/07 PrintTime=09:53:22 28561 ds012888 Rev. No. 5 cmserv Proof 14
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