National Semiconductor DS90CR213, DS90CR214 Technical data

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DS90CR213/DS90CR214
21-Bit Channel Link—66 MHz

General Description

The DS90CR213 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. Aphase-locked transmitclock is transmitted in
parallel with the data streams over a fourth LVDSlink. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CR214 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 66MHz, 21bits ofTTL data are
transmitted at a rate of 462 Mbps per LVDS data channel.
Using a 66 MHz clock, the data throughput is 1.386 Gbit/s
(173 Mbytes/s).

The multiplexing of the data lines provides a substantial
cable reduction. Long distance parallel single-ended buses
typically require a ground wire per active signal (and have
very limited noise rejection capability).Thus, fora 21-bit wide
data and one clock, up to 44 conductors are required. With
the Channel Link chipset as few as 9 conductors (3 data
pairs, 1 clock pair and a minimum of one ground) are
needed. This provides an 80%reduction in required cable

Block Diagrams

July 1997

width, which provides a system cost savings, reduces con­nector physical size and cost, and reduces shielding require­ments due to the cable’s smaller form factor.

The 21 CMOS/TTL inputs can support a variety of signal
combinations. For example, 5 4-bit nibbles (byte + parity) or
2 9-bit (byte + 3 parity) and 1 control.

Features

n 66 MHz Clock Support
n Up to 173 Mbytes/s bandwidth
n Low power CMOS design (
n Power-down mode (
n Up to 1.386 Gbit/s data throughput
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n PLL requires no external components
n Low profile 48-lead TSSOP package
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS Standard

<

610 mW)

<

0.5 mW total)

DS90CR213/DS90CR214 21-Bit Channel Link—66 MHz

DS90CR213/DS90CR214

DS90CR213

DS012888-27

Order Number DS90CR213MTD

See NS Package Number MTD48

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

© 1998 National Semiconductor Corporation DS012888 www.national.com

Order Number DS90CR214MTD

See NS Package Number MTD48

DS90CR214

DS012888-1

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PrintDate=1998/01/07 PrintTime=09:53:21 28561 ds012888 Rev. No. 5 cmserv

Proof 1

Pin Diagrams

DS90CR213

Typical Application

DS012888-21

DS90CR214

DS012888-22

DS012888-23

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PrintDate=1998/01/07 PrintTime=09:53:21 28561 ds012888 Rev. No. 5 cmserv Proof 2

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor SalesOffice/
Distributors for availability and specifications.

Supply Voltage (V
CMOS/TTL Input Voltage −0.3V to (V
CMOS/TTL Output Voltage −0.3V to (V
LVDS Receiver Input Voltage −0.3V to (V
LVDS Driver Output Voltage −0.3V to (V
LVDS Output Short Circuit

Duration Continuous
Junction Temperature +150˚C
Storage Temperature −65˚C to +150˚C
Lead Temperature

(Soldering, 4 sec) +260˚C
Maximum Package Power

Dissipation Capacity

MTD48 (TSSOP) Package:

DS90CR213
DS90CR214

) −0.3V to +6V

CC

CC
CC
CC
CC

+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)

@

25˚C

1.98W

1.89W

Package Derating:

DS90CR213 16 mW/˚C above +25˚C
DS90CR214 15 mW/˚C above +25˚C

ESD Rating (Note 4)

This device does not meet 2000V

Recommended Operating
Conditions

Supply Voltage (V

) 4.75 5.0 5.25 V

CC

Operating Free Air

Temperature (T

) −10 +25 +70 ˚C

A

Receiver Input Range 0 2.4 V
Supply Noise Voltage (V

Min Nom Max Units

) 100 mV

CC

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

CMOS/TTL DC SPECIFICATIONS

V

IH

V

IL

V

OH

V

OL

V

CL

I

IN

I

OS

LVDS DRIVER DC SPECIFICATIONS

V

OD

∆V

V

OS

∆V

I

OS

I

OZ

LVDS RECEIVER DC SPECIFICATIONS

V

TH

V

TL

I

IN

TRANSMITTER SUPPLY CURRENT

I

CCTW

I

CCTZ

High Level Input Voltage 2.0 V
Low Level Input Voltage GND 0.8 V
High Level Output Voltage I
Low Level Output Voltage I
Input Clamp Voltage I
Input Current V
Output Short Circuit Current V

Differential Output Voltage R
Change in VODbetween

OD

Complimentary Output States

=

−0.4 mA 3.8 4.9 V

OH

=

2 mA 0.1 0.3 V

OL

=

−18 mA −0.79 −1.5 V

CL

=

, GND, 2.5V or 0.4V

V

IN

CC

=

0V −120 mA

OUT

=

100Ω 250 290 450 mV

L

±

5.1

Offset Voltage 1.1 1.25 1.375 V
Change in Magnitude of V

OS

between Complimentary Output

OS

States
Output Short Circuit Current V

OUT

=

Output TRI-STATE®Current Powerdown=0V, V

Differential Input High Threshold V

=

CM

=

0V, R

100Ω −2.9 −5 mA

L

OUT

=

0V or V

±

CC

1

+1.2V +100 mV
Differential Input Low Threshold −100 mV
Input Current V

Transmitter Supply Current R

V

IN
IN

=

L

=

+2.4V, V

=

0V, V

100Ω,C

=

5.0V

CC

=

5.0V

CC

=

5 pF, f=32.5 MHz 49 63 mA

L

Worst Case Worst Case Pattern f=37.5 MHz 51 64 mA

(

Figure 1

and

Figure 2

)f=66 MHz 70 84 mA
Transmitter Supply Current Powerdown=Low
Power Down Driver Outputs in TRI-STATE under

125µA

Powerdown Mode

CC

±

10 µA

35 mV

35 mV

±

10 µA

±

10 µA

±

10 µA

P-P

V

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Electrical Characteristics (Continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

RECEIVER SUPPLY CURRENT

I

CCRW

Receiver Supply Current C

=

8 pF, f=32.5 MHz 64 77 mA

L

Worst Case Worst Case Pattern f=37.5 MHz 70 85 mA

(

Figure 1

and

Figure 3

)f=66 MHz 110 140 mA

I

CCRZ

Receiver Supply Current Powerdown=Low
Power Down Receiver Outputs in Previous State during

110µA

Power Down Mode.

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.

Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-

fied (except V
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF)

PLL V
All Other Pins ≥ 2000V
EIAJ (0Ω, 200 pF) ≥ 150V

Note 5: V

and ∆VOD).

OD

≥ 1000V

CC

previously referred as VCM.

OS

CC

=

5.0V and T

=

+25˚C.

A

Transmitter Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

Figure 2

LLHT LVDS Low-to-High Transition Time (
LHLT LVDS High-to-Low Transition Time (
TCIT TxCLK IN Transition Time (

Figure 4

TCCS TxOUT Channel-to-Channel Skew (Note 6) (
TPPos0 Transmitter Output Pulse Position for Bit 0 (
TPPos1 Transmitter Output Pulse Position for Bit 1 1.70 (1/7)Tclk 2.50 ns
TPPos2 Transmitter Output Pulse Position for Bit 2 3.60 (2/7)Tclk 4.50 ns
TPPos3 Transmitter Output Pulse Position for Bit 3 5.90 (3/7)Tclk 6.75 ns
TPPos4 Transmitter Output Pulse Position for Bit 4 8.30 (4/7)Tclk 9.00 ns
TPPos5 Transmitter Output Pulse Position for Bit 5 10.40 (5/7)Tclk 11.10 ns
TPPos6 Transmitter Output Pulse Position for Bit 6 12.70 (6/7)Tclk 13.40 ns
TCIP TxCLK IN Period (
TCIH TxCLK IN High Time (
TCIL TxCLK IN Low Time (
TSTC TxIN Setup to TxCLK IN (
THTC TxIN Hold to TxCLK IN (
TCCD TxCLK IN to TxCLK OUT Delay
TPLLS Transmitter Phase Lock Loop Set (
TPDD Transmitter Powerdown Delay (

Note 6: This limit based on bench characterization.

Figure 6

) 15 T 50 ns

Figure 6

) 0.35T 0.5T 0.65T ns

Figure 6

) 0.35T 0.5T 0.65T ns

Figure 6

) 5 3.5 ns

Figure 6

) 2.5 1.5 ns

@

25˚C, V

Figure 10

Figure 14

) 0.75 1.5 ns

Figure 2

) 0.75 1.5 ns

)8ns

Figure 5

) 350 ps

Figure 16

)

−0.30 0 0.30 ns

f=66 MHz

=

Figure 8

5.0V (

CC

) 3.5 8.5 ns

)10ms

) 100 ns

Receiver Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

Figure 3

CLHT CMOS/TTL Low-to-High Transition Time (
CHLT CMOS/TTL High-to-Low Transition Time (
RSKM RxIN Skew Margin (Note 7) V

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=

5V,T

CC

A

PrintDate=1998/01/07 PrintTime=09:53:21 28561 ds012888 Rev. No. 5 cmserv Proof 4

) 2.5 4.0 ns

Figure 3

) 2.0 4.0 ns

=

25˚C(

Figure 17

)f=40 MHz 700 ps

f=66 MHz 600 ps

Receiver Switching Characteristics (Continued)

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

Figure 7

RCOP RxCLK OUT Period (
RCOH RxCLK OUT High Time (

) 15 T 50 ns

Figure 7

)f

=

40 MHz 6 ns

f=66 MHz 4.3 5 ns

RCOL RxCLK OUT Low Time (

Figure 7

)f

=

40 MHz 10.5 ns

f=66 MHz 7.0 9 ns

RSRC RxOUT Setup to RxCLK OUT (

Figure 7

)f

=

40 MHz 4.5 ns

f=66 MHz 2.5 4.2 ns

RHRC RxOUT Hold to RxCLK OUT (

Figure 7

)f

=

40 MHz 6.5 ns

f=66 MHz 4 5.2 ns
RCCD RxCLK IN to RxCLK OUT Delay
RPLLS Receiver Phase Lock Loop Set (
RPDD Receiver Powerdown Delay (

Note 7: Receiver Skew Margin is definedas the valid data sampling region atthe receiver inputs. Thismargin takes into account for transmitter outputskew (TCCS)
and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter.

RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle)

@

25˚C, V

Figure 11

Figure 15

=

Figure 9

5.0V (

CC

) 6.4 10.7 ns

)10ms

)1µs

AC Timing Diagrams

FIGURE 1. “Worst Case” Test Pattern

DS012888-3

FIGURE 2. DS90CR213 (Transmitter) LVDS Output Load and Transition Times

DS012888-5

FIGURE 3. DS90CR214 (Receiver) CMOS/TTL Output Load and Transition Times

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DS012888-2

DS012888-4

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