National Semiconductor DS90CF581, DS90CF582 Technical data

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DS90CF581/DS90CF582
LVDS 24-Bit Color Flat Panel Display (FPD) Link

DS90CF581/DS90CF582 LVDS 24-Bit Color Flat Panel Display (FPD) Link

April 1996

General Description

The DS90CF581 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted
in parallel with the data streams over a fifth LVDS link. Every
cycle of the transmit clock 28 bits of input data are sampled
and transmitted. The DS90CF582 receiver converts the
LVDS data streams back into 28 bits of CMOS/TTL data. At
a transmit clock frequency of 40 MHz, 24 bits of RGB data
and 4 bits of LCD timing and control data (FPLINE,
FPFRAME, DRDY, CNTL) are transmitted at a rate of
280 Mbps per LVDS data channel. Using a 40 MHz clock,
the data throughput is 140 Megabytes per second. The
chipset is an ideal means to solve EMI and cable size prob­lems associated with wide, high speed TTL interfaces.

Block Diagrams

DS90CF581 DS90CF582

Features

Y

Up to 140 Megabyte/sec Bandwidth

Y

Narrow bus reduces cable size

Y

345 mV swing LVDS devices for low EMI

Y

Low power CMOS design

Y

Power-down mode

Y

PLL requires no external components

Y

Low profile 56-lead TSSOP package

Y

Falling edge data strobe

Y

Compatible with TIA/EIA-644 LVDS standard

Order Number DS90CF581MTD

See NS Package Number MTD56

Order Number DS90CF582MTD

See NS Package Number MTD56

Application

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C

1996 National Semiconductor Corporation RRD-B30M66/Printed in U. S. A.

TL/F/12486

TL/F/12486– 1

TL/F/12486– 2

Connection Diagrams

DS90CF581

DS90CF582

TL/F/12486– 3

TL/F/12486– 4

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Absolute Maximum Ratings (Note 1)

@

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (V

CC

)

CMOS/TTL Input Voltage

CMOS/TTL Output Voltage

LVDS Receiver Input Voltage

LVDS Driver Output Voltage

b

0.3 to (V

b

0.3 to (V

b

0.3 to (V

b

0.3 to (V

b

0.3 toa6V

a

CC

a

CC

a

CC

a

CC

0.3V)

0.3V)

0.3V)

0.3V)

LVDS Output Short Circuit Duration continuous

a

a

150§C

260§C

Junction Temperature

Storage Temperature Range

Lead Temperature (Soldering, 4 sec.)

b

65§Ctoa150§C

Maximum Package Power Dissipation

MTD56 (TSSOP) Package: DS90CF581 1.63W

DS90CF582 1.61W

Derate Package: DS90CF581 12.5 mW/§C abovea25§C

DS90CF582 12.4 mW/§C abovea25§C

This device does not meet 2000V ESD rating. (Note 4)

Recommended Operating
Conditions

Supply Voltage (V

Operating Free

Air Temperature (T

CC

Min Nom Max Units

) 4.5 5.0 5.5 V

)b10

A

a

25§C

a

a

25

70

Receiver Input Range 0 2.4 V

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

CMOS/TTL DC SPECIFICATIONS

V

IH

V

IL

V

OH

V

OL

V

CL

I

IN

I

OS

LVDS DRIVER DC SPECIFICATIONS

V

OD

DV

V

CM

DV

V

OH

V

OL

I

OS

IOZOutput TRI-STATEÉCurrent Power Downe0V, V

LVDS RECEIVER DC SPECIFICATIONS

V

TH

V

TL

I

IN

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of ‘‘Electrical Characteristics’’ specify conditions for device operation.

Note 2: Typical values are given for V

Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise

specified (except V

Note 4: ESD Rating: HBM (1.5 kX, 100 pF)

High Level Input Voltage 2.0 V

Low Level Input Voltage GND 0.8 V

High Level Output Voltage I

Low Level Output Voltage I

Input Clamp Voltage I

Input Current V

Output Short Circuit Current V

Differential Output Voltage R

Change in VODbetween

OD

Complimentary Output States

eb

0.4 mA 3.8 4.9 V

OH

e

2 mA 0.1 0.3 V

OL

eb

18 mA

CL

e

VCC, GND, 2.5V or 0.4V

IN

e

0V

OUT

e

100X 250 290 450 mV

L

b

0.79

g

5.1

Common Mode Voltage 1.1 1.25 1.375 V

Change in VCMbetween

CM

Complimentary Output States

High Level Output Voltage 1.3 1.6 V

Low Level Output Voltage 0.9 1.07 V

Output Short Circuit Current V

Differential Input High Threshold V

Differential Input Low Threshold

Input Current V

and DVOD).

OD

t

PLL V

CC

All other pins
EIAJ (0X, 200 pF)

1000V

t

CC

2000V

t

e

5.0V and T

150V

A

ea

e

OUT

ea

CM

ea

IN

e

V

IN

25§C.

e

0V, R

100X

L

1.2V

2.4V V

0V

OUT

e

0V or V

e

CC

CC

5.5V

b

2.9

g

b

100 mV

1

CC

b

1.5 V

g

10 mA

b

120 mA

35 mV

35 mV

b

5mA

g

10 mA

a

100 mV

g

10 mA

g

10 mA

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C

§

V

Electrical Characteristics (Continued)

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

TRANSMITTER SUPPLY CURRENT

I

CCTW

I

CCTG

I

CCTZ

Transmitter Supply Current, R
Worst Case Worst Case Pattern

Transmitter Supply Current, R
16 Grayscale Grayscale Pattern

L

L

e

100X,C

e

100X,C

Transmitter Supply Current, Power DowneLow
Power Down

e

5 pF, fe32.5 MHz 34 46 mA

L

(Figures 1, 3)

e

5 pF, fe32.5 MHz 27 42 mA

L

(Figures 2, 3)

fe37.5 MHz 36 48 mA

fe37.5 MHz 28 43 mA

110mA

RECEIVER SUPPLY CURRENT

I

CCRW

I

CCRG

I

CCRZ

Receiver Supply Current, C
Worst Case Worst Case Pattern

Receiver Supply Current, C
16 Grayscale 16 Grayscale Pattern

Receiver Supply Current, Power DowneLow
Power Down

e

8 pF, fe32.5 MHz 55 75 mA

L

e

8 pF, fe32.5 MHz 35 55 mA

L

(Figures 1, 4)

(Figures 2, 4)

fe37.5 MHz 60 80 mA

fe37.5 MHz 37 58 mA

110mA

Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

LLHT LVDS Low-to-High Transition Time

LHLT LVDS High-to-Low Transition Time

CLHT CMOS/TTL Low-to-High Transition Time

CHLT CMOS/TTL High-to-Low Transition Time

TCIT TxCLK IN Transition Time

TCCS TxOUT Channel-to-Channel Skew (Note A)

TSSPW Tx Sub-Symbol Pulse Width

RCCS RxIN Channel-to-Channel Skew (Note B) 700 ps

TCIP TxCLK IN Period

TCIH TxCLK IN High Time

TCIL TxCLK IN Low Time

TSTC TxIN Setup to TxCLK IN

THTC TxIN Hold to TxCLK IN

RCOP RxCLK OUT Period

Note A: This limit based on bench characterization.

Note B: This limit assumes a maximum cable skew of 350 ps.

(Figure 7)

(Figure 7)

(Figure 7)

(Figure 7)

(Figure 7)

(Figure 8)

(Figure 5)

(Figure 6)

(Figure 3)

(Figure 3)

(Figure 4)

(Figure 4)

0.75 1.5 ns

0.75 1.5 ns

3.5 6.5 ns

2.7 6.5 ns

(Figure 6)

fe20 MHz 5.5 7 8 ns

25 T 50 ns

0.35T 0.5T 0.65T ns

0.35T 0.5T 0.65T ns

8ns

2.5 2 ns

25 T 50 ns

8ns

350 ps

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Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified (Continued)

Symbol Parameter Min Typ Max Units

RCOH RxCLK OUT High Time

RCOL RxCLK OUT Low Time

RSRC RxOUT Setup to RxCLK OUT

RHRC RxOUT Hold to RxCLK OUT

TCCD TxCLK IN to TxCLK OUT Delay@25§C,

RCCD RxCLK IN to RxCLK OUT Delay@25§C,

TPLLS Transmitter Phase Lock Loop Set

RPLLS Receiver Phase Lock Loop Set

e

V

5.0V

e

5.0V

(Figure 9)

(Figure 10)

CC

V

CC

(Figure 8)

(Figure 8)

(Figure 8)

(Figure 8)

(Figure 11)

(Figure 12)

fe20 MHz 21.5 ns

fe40 MHz 10.5 ns

fe20 MHz 19 ns

fe40 MHz 6 ns

fe20 MHz 14 ns

fe40 MHz 4.5 ns

fe20 MHz 16 ns

fe40 MHz 6.5 ns

5 9.7 ns

7.6 11.9 ns

10 ms

10 ms

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AC Timing Diagrams

FIGURE 1. ‘‘WORST CASE’’ Test Pattern

TL/F/12486– 15

FIGURE 2. ‘‘16 GRAYSCALE’’ Test Pattern

TL/F/12486– 16

Note 1: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.

Note 2: The 16 grayscale test pattern tests device power consumption for a ‘‘typical’’ LCD display pattern. The test pattern approximates signal switching needed

to produce groups of 16 vertical stripes across the display.

Note 3:

Figure 1

and

Figure 2

show a falling edge data strobe (TxCLK IN/RxCLK OUT).

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AC Timing Diagrams (Continued)

TL/F/12486– 8

FIGURE 3. DS90CF581 (Transmitter) LVDS Output Load and Transition Timing

TL/F/12486– 10

FIGURE 4. DS90CF582 (Receiver) CMOS/TTL Output Load and Transition Timing

FIGURE 5. DS90CF581 (Transmitter) Input Clock Transition Time

TL/F/12486– 17

Note 1: Measurements at V

Note 2: TCCS measured between earliest and latest initial LVDS edges.

Note 3: TxCLK OUT Differential High

TxCLK OUT Differential Low

e

0V

diff

x

Low Edge for DS90CF561

x

High Edge for DS90CR561

TL/F/12486– 9

TL/F/12486– 11

TL/F/12486– 18

FIGURE 6. DS90CF581 (Transmitter) Channel-to-Channel Skew and Pulse Width

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AC Timing Diagrams (Continued)

FIGURE 7. DS90CF581 (Transmitter) Setup/Hold and High/Low Times

FIGURE 8. DS90CF582 (Receiver) Setup/Hold and High/Low Times

TL/F/12486– 19

FIGURE 9. DS90CF581 (Transmitter) Clock In to Clock Out Delay

TL/F/12486– 20

FIGURE 10. DS90CF582 (Receiver) Clock In to Clock Out Delay

TL/F/12486– 12

TL/F/12486– 13

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AC Timing Diagrams (Continued)

FIGURE 11. DS90CF581 (Transmitter) Phase Lock Loop Set Time

FIGURE 12. DS90CF582 (Receiver) Phase Lock Loop Set Time

TL/F/12486– 14

TL/F/12486– 21

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AC Timing Diagrams (Continued)

FIGURE 13. Seven Bits of LVDS in One Block Cycle

FIGURE 14. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CF581)

TL/F/12486– 22

TL/F/12486– 23

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DS90CF581 Pin DescriptionÐFPD Link Transmitter

Pin Name I/O No. Description

TxIN I 28 TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines (FPLINE, FPFRAME,

DRDY, CNTL). (Also referred to as HSYNC, VSYNC and DATA ENABLE)

a

TxOUT

TxOUT

b

O 4 Positive LVDS differential data output

O 4 Negative LVDS differential data output

FPSHIFT IN I 1 TTL level clock input. The falling edge acts as data strobe.

TxCLK OUTaO 1 Positive LVDS differential clock output

TxCLK OUTbO 1 Negative LVDS differential clock output

PWR DOWN I 1 TTL level input. Assertion (low input) TRI-STATE the outputs, ensuring low current at power down.

V

CC

I 4 Power supply pins for TTL inputs

GND I 5 Ground pins for TTL inputs

PLL V

CC

I 1 Power supply pin for PLL

PLL GND I 2 Ground pins for PLL

LVDS V

CC

I 1 Power supply pin for LVDS outputs

LVDS GND I 3 Ground pins for LVDS outputs

DS90CF582 Pin DescriptionÐFPD Link Receiver

Pin Name I/O No. Description

a

RxIN

b

RxIN

RxOUT O 28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines (FPLINE,

RxCLK IN

RxCLK IN

FPSHIFT OUT O 1 TTL level clock output. The falling edge acts as data strobe.

PWR DOWN I 1 TTL level input. Assertion (low input) maintains the receiver outputs in the previous state

V

CC

GND I 5 Ground pins for TTL outputs

PLL V

CC

PLL GND I 2 Ground pin for PLL

LVDS V

CC

LVDS GND I 3 Ground pins for LVDS inputs

I 4 Positive LVDS differential data inputs.

I 4 Negative LVDS differential data inputs.

FPFRAME, DRDY, CNTL). (Also referred to as HSYNC, VSYNC and DATA ENABLE)

a

I 1 Positive LVDS differential clock input

b

I 1 Negative LVDS differential clock input

I 4 Power supply pins for TTL outputs

I 1 Power supply pin for PLL

I 1 Power supply pin for LVDS inputs

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Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Molded Thin Shrink Small Outline Package, JEDEC

Order Number DS90CF581MTD or DS90CF582MTD

NS Package Number MTD56

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DS90CF581/DS90CF582 LVDS 24-Bit Color Flat Panel Display (FPD) Link

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

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Corporation Europe Hong Kong Ltd. Japan Ltd.

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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