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DS90C383B
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel
Display (FPD) Link-65 MHz
DS90C383B +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz
October 2005
General Description
The DS90C383B transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fifth LVDS link. Every
cycle of the transmit clock 28 bits of input data are sampled
and transmitted. At a transmit clock frequency of 65 MHz, 24
bits of RGB data and 3 bits of LCD timing and control data
(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455
Mbps per LVDS data channel. Using a 65 MHz clock, the
data throughput is 227 Mbytes/sec. The DS90C383B transmitter can be programmed for Rising edge strobe or Falling
edge strobe through a dedicated pin. A Rising edge or
Falling edge strobe transmitter will interoperate with a Falling
edge strobe Receiver (DS90CF386) without any translation
logic.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n No special start-up sequence required between
clock/data and /PD pins. Input signal (clock and data)
can be applied either before or after the device is
powered.
n Support Spread Spectrum Clocking up to 100kHz
frequency modulation & deviations of
spread or −5% down spread.
n "Input Clock Detection" feature will pull all LVDS pairs to
logic low when input clock is missing and when /PD pin
is logic high.
n 18 to 68 MHz shift clock support
n Best–in–Class Set & Hold Times on TxINPUTs
n Tx power consumption
Grayscale
n 40% Less Power Dissipation than BiCMOS Alternatives
n Tx Power-down mode
n Supports VGA, SVGA, XGA and Dual Pixel SXGA.
n Narrow bus reduces cable size and cost
n Up to 1.8 Gbps throughput
n Up to 227 Megabytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 56-lead TSSOP package
n Improved replacement for:
SN75LVDS83, DS90C383A
<
130 mW (typ)@65MHz
<
60µW (typ)
±
2.5% center
Block Diagram
DS90C383B
Order Number DS90C383BMT
See NS Package Number MTD56
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 2005 National Semiconductor Corporation DS200984 www.national.com
20098401
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
DS90C383B
Supply Voltage (V
CMOS/TTL Input Voltage −0.3V to (V
LVDS Driver Output Voltage −0.3V to (V
LVDS Output Short Circuit
Duration Continuous
Junction Temperature +150˚C
Storage Temperature −65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec) +260˚C
Maximum Package Power Dissipation Capacity
MTD56 (TSSOP) Package:
) −0.3V to +4V
CC
CC
CC
@
+ 0.3V)
+ 0.3V)
25˚C
ESD Rating
(HBM, 1.5 kΩ, 100 pF) 7 kV
(EIAJ, 0Ω, 200 pF) 500V
Recommended Operating
Conditions
Min Nom Max Units
Supply Voltage
(VCC)
Operating Free Air
Temperature (T
Supply Noise
Voltage (V
)
CC
TxCLKIN frequency 18 68 MHz
3.0 3.3 3.6 V
) −10 +25 +70 ˚C
A
200 mV
DS90C383B 1.63 W
Package Derating:
DS90C383B 12.5 mW/˚C above +25˚C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
CMOS/TTL DC SPECIFICATIONS
V
IH
V
IL
V
CL
I
IN
LVDS DC SPECIFICATIONS
V
OD
∆V
OD
V
OS
∆V
OS
I
OS
I
OZ
TRANSMITTER SUPPLY CURRENT
ICCTW Transmitter Supply Current
High Level Input Voltage 2.0 V
CC
Low Level Input Voltage GND 0.8 V
Input Clamp Voltage ICL= −18 mA −0.79 −1.5 V
Input Current VIN= 0.4V, 2.5V or V
V
= GND −10 0 µA
IN
CC
+1.8 +10 µA
Differential Output Voltage RL= 100Ω 250 345 450 mV
Change in VODbetween
35 mV
complimentary output states
Offset Voltage (Note 4) 1.13 1.25 1.38 V
Change in VOSbetween
35 mV
complimentary output states
Output Short Circuit Current V
Output TRI-STATE®Current Power Down = 0V,
Worst Case
= 0V, RL= 100Ω −3.5 −5 mA
OUT
±
1
V
=0VorV
OUT
R
L
C
L
= 100Ω,
= 5 pF,
CC
f = 25MHz 31 45 mA
±
10 µA
Worst Case Pattern
(Figures 1, 4 )" Typ "
f = 40MHz 37 50 mA
values are given for V
CC
= 3.6V and TA=
+25˚C, " Max " values
are given for V
3.6V and T
CC
= −10˚C
A
f = 65 MHz 48 60 mA
=
PP
V
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Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
TRANSMITTER SUPPLY CURRENT
ICCTG Transmitter Supply Current
16 Grayscale
R
L
C
L
= 100Ω,
= 5 pF,
16 Grayscale Pattern
(Figures 2, 4 )" Typ "
values are given for V
CC
= 3.6V and TA=
+25˚C, " Max " values
ICCTZ Transmitter Supply Current
Power Down
are given for V
3.6V and T
Power Down = Low
Driver Outputs in TRI-STATE under
CC
= −10˚C
A
Power Down Mode
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V
Note 4: V
OS
and ∆VOD).
OD
previously referred as VCM.
= 3.3V and TA= +25˚C unless specified otherwise.
CC
f = 25MHz 29 40 mA
f = 40MHz 33 45 mA
f = 65 MHz 39 50 mA
=
17 150 µA
DS90C383B
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
TCIT TxCLK IN Transition Time (Figure 5 ) 5ns
TCIP TxCLK IN Period (Figure 6 ) 14.7 T 50 ns
TCIH TxCLK IN High Time (Figure 6 ) 0.35T 0.5T 0.65T ns
TCIL TxCLK IN Low Time (Figure 6) 0.35T 0.5T 0.65T ns
TXIT TxIN, and Power Down pins Transition Time
TXPD Minimum pulse width for Power Down pin signal
1.5 6.0 ns
1us
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
LLHT LVDS Low-to-High Transition Time (Figure 4 ) 0.75 1.4 ns
LHLT LVDS High-to-Low Transition Time (Figure 4 ) 0.75 1.4 ns
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note
5)
TPPos1 Transmitter Output Pulse Position for Bit 1 2.00 2.20 2.40 ns
TPPos2 Transmitter Output Pulse Position for Bit 2 4.20 4.40 4.60 ns
TPPos3 Transmitter Output Pulse Position for Bit 3 6.39 6.59 6.79 ns
TPPos4 Transmitter Output Pulse Position for Bit 4 8.59 8.79 8.99 ns
TPPos5 Transmitter Output Pulse Position for Bit 5 10.79 10.99 11.19 ns
TPPos6 Transmitter Output Pulse Position for Bit 6 12.99 13.19 13.39 ns
f=65
MHz
−0.20 0 +0.20 ns
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Transmitter Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
DS90C383B
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note
5)
TPPos1 Transmitter Output Pulse Position for Bit 1 3.32 3.57 3.82 ns
TPPos2 Transmitter Output Pulse Position for Bit 2 6.89 7.14 7.39 ns
TPPos3 Transmitter Output Pulse Position for Bit 3 10.46 10.71 10.96 ns
TPPos4 Transmitter Output Pulse Position for Bit 4 14.04 14.29 14.54 ns
TPPos5 Transmitter Output Pulse Position for Bit 5 17.61 17.86 18.11 ns
TPPos6 Transmitter Output Pulse Position for Bit 6 21.18 21.43 21.68 ns
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note
5)
TPPos1 Transmitter Output Pulse Position for Bit 1 5.26 5.71 6.16 ns
TPPos2 Transmitter Output Pulse Position for Bit 2 10.98 11.43 11.88 ns
TPPos3 Transmitter Output Pulse Position for Bit 3 16.69 17.14 17.59 ns
TPPos4 Transmitter Output Pulse Position for Bit 4 22.41 22.86 23.31 ns
TPPos5 Transmitter Output Pulse Position for Bit 5 25.12 28.57 29.02 ns
TPPos6 Transmitter Output Pulse Position for Bit 6 33.84 34.29 34.74 ns
TSTC TxIN Setup to TxCLK IN (Figure 6 ) 2.5 ns
THTC TxIN Hold to TxCLK IN (Figure 6 ) 0.5 ns
TCCD TxCLK IN to TxCLK OUT Delay (Figure 7 ) 50% duty cycle
input clock is assumed, T
= 70˚C,and 25MHz for ” Max ”, VCC= 3.6V, R_FB = V
T
A
= −10˚C, and 65MHz for ” Min ”,
A
CC
TxCLK IN to TxCLK OUT Delay (Figure 7 ) 50% duty cycle
input clock is assumed, T
= 70˚C, and 25MHz for ” Max ”, VCC= 3.6V, R_FB = GND
T
A
= −10˚C, and 65MHz for ” Min ”,
A
SSCG
Spread Spectrum Clock support; Modulation frequency with a
linear profile(Note 6).
TPLLS Transmitter Phase Lock Loop Set (Figure 8 ) 10 ms
TPDD Transmitter Power Down Delay (Figure 10 ) 100 ns
Note 5: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This
parameter is functionality tested only on Automatic Test Equipment (ATE).
Note 6: Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the performance of tracking
Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLK− pins.
f=40
MHz
f=
25MHz
f=
25MHz
f=
40MHz
f=
65MHz
−0.25 0 +0.25 ns
−0.45 0 +0.45 ns
3.340 7.211 ns
3.011 6.062 ns
100kHz
±
2.5%/−5%
100kHz
±
2.5%/−5%
100kHz
±
2.5%/−5%
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AC Timing Diagrams
DS90C383B
20098404
FIGURE 1. “Worst Case” Test Pattern
20098405
FIGURE 2. “16 Grayscale” Test Pattern (Notes 7, 8, 9, 10)
Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 8: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 9: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 10: Recommended pin to signal mapping. Customer may choose to define differently.
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AC Timing Diagrams (Continued)
DS90C383B
FIGURE 3. DS90C383B (Transmitter) LVDS Output Load
FIGURE 4. DS90C383B (Transmitter) LVDS Transition Times
20098430
20098406
20098408
FIGURE 5. DS90C383B (Transmitter) Input Clock Transition Time
20098410
FIGURE 6. DS90C383B (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe)
20098412
FIGURE 7. DS90C383B (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe)
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AC Timing Diagrams (Continued)
FIGURE 8. DS90C383B (Transmitter) Phase Lock Loop Set Time
DS90C383B
20098414
FIGURE 9. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs
20098418
FIGURE 10. Transmitter Power Down Delay
20098417
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AC Timing Diagrams (Continued)
DS90C383B
20098426
FIGURE 11. Transmitter LVDS Output Pulse Position Measurement
DS90C383B Pin Description—FPD Link Transmitter
Pin Name I/O No. Description
TxIN I 28 TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
TxOUT+ O 4 Positive LVDS differentiaI data output.
TxOUT− O 4 Negative LVDS differential data output.
FPSHIFT IN I 1 TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
R_FB I 1 Programmable strobe select (See Table 1).
TxCLK OUT+ O 1 Positive LVDS differential clock output.
TxCLK OUT− O 1 Negative LVDS differential clock output.
PWR DOWN
V
CC
GND I 5 Ground pins for TTL inputs.
PLL V
CC
PLL GND I 2 Ground pins for PLL.
LVDS V
CC
LVDS GND I 3 Ground pins for LVDS outputs.
I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down. See Applications Information section.
I 3 Power supply pins for TTL inputs.
I 1 Power supply pin for PLL.
I 1 Power supply pin for LVDS outputs.
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Applications Information
The DS90C383B are backward compatible with the
DS90C383/DS90CF383, DS90C383A/DS90CF383A and
are a pin-for-pin replacement.
This device may also be used as a replacement for the
DS90CF583 (5V, 65MHz) and DS90CF581 (5V, 40MHz)
FPD-Link Transmitters with certain considerations/
modifications:
1. Change 5V power supply to 3.3V. Provide this supply to
, LVDS VCCand PLL VCCof the transmitter.
the V
CC
2. The DS90C383B transmitter input and control inputs
accept 3.3V LVTTL/LVCMOS levels. They are not 5V
tolerant.
3. To implement a falling edge device for the DS90C383B,
the R_FB pin (pin 17) may be tied to ground OR left
unconnected (an internal pull-down resistor biases this
pin low). Biasing this pin to Vcc implements a rising edge
device.
TRANSMITTER INPUT PINS
The TxIN and control input pins are compatible with LVCMOS and LVTTL levels. These pins are not 5V tolerant.
TRANSMITTER INPUT CLOCK/DATA SEQUENCING
The DS90C383B does not require any special requirement
for sequencing of the input clock/data and PD (PowerDown)
signal. The DS90C383B offers a more robust input sequencing feature where the input clock/data can be inserted after
the release of the PD signal. In the case where the clock/
data is stopped and reapplied, such as changing video mode
within Graphics Controller, it is not necessary to cycle the PD
signal. However, there are in certain cases where the PD
may need to be asserted during these mode changes. In
cases where the source (Graphics Source) may be supplying an unstable clock or spurious noisy clock output to the
LVDS transmitter, the LVDS Transmitter may attempt to lock
onto this unstable clock signal but is unable to do so due the
instability or quality of the clock source. The PD signal in
these cases should then be asserted once a stable clock is
applied to the LVDS transmitter. Asserting the PWR DOWN
pin will effectively place the device in reset and disable the
PLL, enabling the LVDS Transmitter into a power saving
standby mode. However, it is still generally a good practice
to assert the PWR DOWN pin or reset the LVDS transmitter
whenever the clock/data is stopped and reapplied but it is
not mandatory for the DS90C383B.
SPREAD SPECTRUM CLOCK SUPPORT
The DS90C383B can support Spread Spectrum Clocking
signal type inputs. The DS90C383B outputs will accurately
track Spread Spectrum Clock/Data inputs with modulation
frequencies of up to 100kHz (max.)with either center spread
±
2.5% or down spread -5% deviations.
of
POWER SOURCES SEQUENCE
In typical applications, it is recommended to have V
and PLL VCCfrom the same power source with three
V
CC
CC
, LVDS
separate de-coupling bypass capacitor groups. There is no
requirement on which VCC entering the device first.
DS90C383B
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Pin Diagram
DS90C383B
DS90C383B
20098423
Typical Application
TABLE 1. Programmable Transmitter (DS90C383B)
Pin Condition Strobe Status
R_FB R_FB = V
CC
Rising edge strobe
R_FB R_FB = GND or NC Falling edge strobe
20098403
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Physical Dimensions inches (millimeters) unless otherwise noted
DS90C383B +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz
56-Lead Molded Thin Shrink Small Outline Package, JEDEC
Order Number DS90C383BMT
NS Package Number MTD56
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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