National Semiconductor DS90C383A, DS90CF383A Technical data

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DS90C383A/DS90CF383A
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel
Display (FPD) Link-65 MHz
+3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD)
Link-65 MHz

July 1998

DS90C383A/DS90CF383A +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD)

Link-65 MHz, +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

1.0 General Description

The DS90C383A/DS90CF383A transmitter converts 28 bits
of CMOS/TTL data into four LVDS (Low Voltage Differential
Signaling) data streams. A phase-locked transmit clock is
transmitted in parallel with the data streams over a fifth
LVDS link. Every cycle of the transmit clock 28 bits of input
data are sampled and transmitted. At a transmit clock fre­quency of 65 MHz, 24 bits of RGB data and 3 bits of LCD
timing and control data (FPLINE, FPFRAME, DRDY) are
transmitted at a rate of 455 Mbps per LVDS data channel.
Using a 65 MHz clock, the data throughput is 227 Mbytes/
sec. The DS90C383A transmitter can be programmed for
Rising edge strobe or Falling edge strobe through a dedi­cated pin. The DS90CF383A is fixed as a Falling edge
strobe transmitter. A Rising edge or Falling edge strobe
transmitter will interoperate with a Falling edge strobe Re­ceiver (DS90CF384) without any translation logic.

This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.

3.0 Block Diagrams

DS90C383A/DS90CF383A

2.0 Features

n 20 to 65 MHz shift clock support
n Rejects

n Best–in–Class Set & Hold Times on TxINPUTs
n Tx power consumption

n

n Tx Power-down mode
n ESD rating
n Supports VGA, SVGA, XGA and Dual Pixel SXGA.
n Narrow bus reduces cable size and cost
n Up to 1.8 Gbps throughput
n Up to 227 Megabytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 56-lead TSSOP package
n Improved replacement for:

>

±

3ns Jitter from VGA chip with less than

225ps output Jitter

Grayscale

>

50%Less Power Dissipation than BiCMOS

Alternatives

SN75LVDS83 — DS90C383A
SN75LVDS81 — DS90CF383A

@

65MHz (TJCC)

<

130 mW (typ)@65MHz

<

>

7 kV (HBM),>500V (EIAJ)

200µW (max)

DS100100-1

Order Number DS90C383AMTD or DS90CF383AMTD

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

© 1999 National Semiconductor Corporation DS100100 www.national.com

See NS Package Number MTD56

4.0 Absolute Maximum Ratings (Note

1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V
CMOS/TTL Input Voltage −0.3V to (V
LVDS Driver Output Voltage −0.3V to (V
LVDS Output Short Circuit

Duration Continuous
Junction Temperature +150˚C
Storage Temperature −65˚C to +150˚C
Lead Temperature

(Soldering, 4 sec) +260˚C
Maximum Package Power Dissipation Capacity

MTD56 (TSSOP) Package:

DS90C383A/DS90CF383A 1.63 W

) −0.3V to +4V

CC

CC
CC

@

25˚C

+ 0.3V)
+ 0.3V)

Package Derating:

DS90C383A/DS90CF383A 12.5 mW/˚C above +25˚C

ESD Rating

>

(HBM, 1.5 kΩ, 100 pF)

(EIAJ, 0Ω, 200 pF)

>

7kV

500V

5.0 Recommended Operating
Conditions

Supply Voltage (V

) 3.0 3.3 3.6 V

CC

Operating Free Air

Temperature (T

) −10 +25 +70 ˚C

A

Receiver Input Range 0 2.4 V
Supply Noise Voltage (V
TxCLKIN frequency 18 68 MHz

Min Nom Max Units

) 100 mV

CC

PP

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

CMOS/TTL DC SPECIFICATIONS

V

IH

V

IL

V

CL

I

IN

LVDS DC SPECIFICATIONS

V

OD

∆V

V

OS

∆V

I

OS

I

OZ

TRANSMITTER SUPPLY CURRENT

ICCTW Transmitter Supply Current

ICCTG Transmitter Supply Current

ICCTZ Transmitter Supply Current

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.

Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-

fied (except V
Note 4: V

High Level Input Voltage 2.0 V
Low Level Input Voltage GND 0.8 V
Input Clamp Voltage ICL= −18 mA −0.79 −1.5 V
Input Current VIN= 0.4V, 2.5V or V

V

= GND −10 0 µA

IN

CC

+1.8 +10 µA

Differential Output Voltage RL= 100Ω 250 345 450 mV
Change in VODbetween

OD

complimentary output states
Offset Voltage (Note 4) 1.125 1.25 1.375 V
Change in VOSbetween

OS

complimentary output states
Output Short Circuit Current V
Output TRI-STATE®Current Power Down = 0V,

Worst Case

16 Grayscale

Power Down

= 0V, RL= 100Ω −3.5 −5 mA

OUT

V

=0VorV

OUT

R

= 100Ω,

L

= 5 pF,

C

L

Worst Case Pattern

CC

(Figures 1, 4)

R

= 100Ω,

L

= 5 pF,

C

L

16 Grayscale Pattern

(Figures 2, 4)

Power Down = Low

f = 32.5 MHz 31 43 mA
f = 37.5 MHz 33 45 mA
f = 65 MHz 39 52 mA
f = 32.5 MHz 23 35 mA
f = 37.5 MHz 28 40 mA
f = 65 MHz 33 45 mA

±

1

10 55 µA
Driver Outputs in TRI-STATE under
Power Down Mode

= 3.3V and TA= +25C.

CC

and ∆VOD).

OD

previously referred as VCM.

OS

CC

35 mV

35 mV

±

10 µA

V

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Recommended Transmitter Input Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

TCIT TxCLK IN Transition Time
TCIP TxCLK IN Period
TCIH TxCLK IN High Time
TCIL TxCLK IN Low Time

(Figure 6 )

(Figure 6 )

(Figure 6)

(Figure 5 )

14.7 T 55.6 ns

0.35T 0.5T 0.65T ns

0.35T 0.5T 0.65T ns

5ns

Transmitter Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

LLHT LVDS Low-to-High Transition Time
LHLT LVDS High-to-Low Transition Time
TPPos0 Transmitter Output Pulse Position for Bit 0
TPPos1 Transmitter Output Pulse Position for Bit 1 1.90 2.20 2.40 ns
TPPos2 Transmitter Output Pulse Position for Bit 2 4.10 4.40 4.60 ns
TPPos3 Transmitter Output Pulse Position for Bit 3 6.30 6.60 6.80 ns
TPPos4 Transmitter Output Pulse Position for Bit 4 8.50 8.80 9.00 ns
TPPos5 Transmitter Output Pulse Position for Bit 5 10.70 11.00 11.20 ns
TPPos6 Transmitter Output Pulse Position for Bit 6 12.90 13.20 13.40 ns
TPPos0 Transmitter Output Pulse Position for Bit 0
TPPos1 Transmitter Output Pulse Position for Bit 1 3.22 3.57 3.92 ns
TPPos2 Transmitter Output Pulse Position for Bit 2 6.79 7.14 7.49 ns
TPPos3 Transmitter Output Pulse Position for Bit 3 10.36 10.71 11.06 ns
TPPos4 Transmitter Output Pulse Position for Bit 4 13.93 14.28 14.63 ns
TPPos5 Transmitter Output Pulse Position for Bit 5 17.51 17.86 18.21 ns
TPPos6 Transmitter Output Pulse Position for Bit 6 21.08 21.43 21.78 ns
TPPos0 Transmitter Output Pulse Position for Bit 0
TPPos1 Transmitter Output Pulse Position for Bit 1 4.00 4.40 4.80 ns
TPPos2 Transmitter Output Pulse Position for Bit 2 8.40 8.80 9.20 ns
TPPos3 Transmitter Output Pulse Position for Bit 3 12.80 13.20 13.60 ns
TPPos4 Transmitter Output Pulse Position for Bit 4 17.20 17.60 18.00 ns
TPPos5 Transmitter Output Pulse Position for Bit 5 21.60 22.00 22.40 ns
TPPos6 Transmitter Output Pulse Position for Bit 6 26.00 26.40 26.80 ns
TSTC TxIN Setup to TxCLK IN
THTC TxIN Hold to TxCLK IN
TCCD TxCLK IN to TxCLK OUT Delay

TxCLK IN to TxCLK OUT Delay

TJCC Transmitter Jitter Cycle-to-Cycle

TPLLS Transmitter Phase Lock Loop Set
TPDD Transmitter Power Down Delay

Note 5: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This param­eter is functionality tested only on Automatic Test Equipment (ATE).

Note 6: The Limits are based onstatistical analysis of the device performance over process, voltage, and temperature ranges.Output jitter is measured with a cycle­to-cycle jitter of 3ns applied to the input clock signal. A jitter event of 3ns, represents worse case jump in the clock edge from most Graphics controller VGA chips
currently available. This parameter is used when calculating system margin (RSKM). See Figures 12, 13 and AN-1059.

(Figure 6 )

(Figure 6 )

(Figure 4 )
(Figure 4 )

(Figure 11 )

(Figure 11 )

(Figure 11 )

(Figure 7 )

TA=25˚C,VCC=3.3V 3 5.5 ns

(Figure 7 )

(Figures 12, 13 )

(Figure 8 )

(Figure 10 )

(Note 5) f=65 MHz −0.30 0 0.20 ns

(Note 5) f=40 MHz −0.35 0 0.35 ns

(Note 5) f=32.5

MHz

(Note 6) f=65 MHz 175 225 ps

f=40 MHz 240 380 ps

f=32.5

MHz

0.75 1.5 ns

0.75 1.5 ns

−0.40 0 0.40 ns

2.5 ns
0ns

3 7.0 ns

260 400 ps

10 ms

100 ns

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6.0 AC Timing Diagrams

DS100100-4

FIGURE 1. “Worst Case” Test Pattern

DS100100-5

FIGURE 2. “16 Grayscale” Test Pattern (Notes 7, 8, 9, 10)

Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 8: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed

to produce groups of 16 vertical stripes across the display.

Note 9:

Figures 1, 2

Note 10: Recommended pin to signal mapping. Customer may choose to define differently.

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show a falling edge data strobe (TxCLK IN/RxCLK OUT).

6.0 AC Timing Diagrams (Continued)

FIGURE 3. DS90C383A/DS90CF383A (Transmitter) LVDS Output Load

FIGURE 4. DS90C383A/DS90CF383A (Transmitter) LVDS Transition Times

FIGURE 5. DS90C383A/DS90CF383A (Transmitter) Input Clock Transition Time

DS100100-30

DS100100-6

DS100100-8

DS100100-10

FIGURE 6. DS90C383A/DS90CF383A (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe)

DS100100-12

FIGURE 7. DS90C383A/DS90CF383A (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe)

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6.0 AC Timing Diagrams (Continued)

FIGURE 8. DS90C383A/DS90CF383A (Transmitter) Phase Lock Loop Set Time

DS100100-14

FIGURE 9. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs

FIGURE 10. Transmitter Power Down Delay

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DS100100-17

DS100100-18

6.0 AC Timing Diagrams (Continued)

FIGURE 11. Transmitter LVDS Output Pulse Position Measurement

DS100100-26

FIGURE 12. TJCC Test Setup

DS100100-27

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6.0 AC Timing Diagrams (Continued)

DS100100-28

FIGURE 13. Timing Diagram of the Input cycle-to-cycle clock jitter

7.0 DS90C383A Pin Description—FPD Link Transmitter

Pin Name I/O No. Description

TxIN I 28 TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines —FPLINE,

TxOUT+ O 4 Positive LVDS differentiaI data output.
TxOUT− O 4 Negative LVDS differential data output.
FPSHIFT IN I 1 TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
R_FB I 1 Programmable strobe select (See Table 1).
TxCLK OUT+ O 1 Positive LVDS differential clock output.
TxCLK OUT− O 1 Negative LVDS differential clock output.
PWR DOWN

V

CC

I 1 TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at

I 3 Power supply pins for TTL inputs.
GND I 4 Ground pins for TTL inputs.
PLL V

CC

I 1 Power supply pin for PLL.
PLL GND I 2 Ground pins for PLL.
LVDS V

CC

I 1 Power supply pin for LVDS outputs.
LVDS GND I 3 Ground pins for LVDS outputs.

FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).

power down.

8.0 DS90CF383A Pin Description—FPD Link Transmitter

Pin Name I/O No. Description

TxIN I 28 TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines —FPLINE,

TxOUT+ O 4 Positive LVDS differential data output.
TxOUT− O 4 Negative LVDS differential data output.
FPSHIFT IN I 1 TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
TxCLK OUT+ O 1 Positive LVDS differential clock output.
TxCLK OUT− O 1 Negative LVDS differential clock output.
PWR DOWN

V

CC

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I 1 TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at

I 4 Power supply pins for TTL inputs.

FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).

power down.

8.0 DS90CF383A Pin Description—FPD Link Transmitter (Continued)

Pin Name I/O No. Description

GND I 4 Ground pins for TTL inputs.
PLL V

CC

PLL GND I 2 Ground pins for PLL.
LVDS V

CC

LVDS GND I 3 Ground pins for LVDS outputs.

I 1 Power supply pin for PLL.

I 1 Power supply pin for LVDS outputs.

9.0 Applications Information

The DS90C383A/DS90CF383A are backward compatible
with the DS90C383/DS90CF383 and are a pin-for-pin re­placement. The device (DS90C383A/DS90CF383A) utilizes
a different PLL architecture employing an internal 7X clock
for enhanced pulse position control.

This device (DS90C383A/DS90CF383A) also features re­duced variation of the TCCD parameter which is important
for dual pixel applications. (See AN-1084) TCCD variation
has been measured to be less than 250ps at 65MHz under
normal operating conditions.

This device may also be used as a replacement for the
DS90CF583 (5V, 65MHz) and DS90CF581 (5V, 40MHz)
FPD-Link Transmitters with certain considerations/
modifications:

1. Change 5V power supply to 3.3V. Provide this supply to
the V

, LVDS VCCand PLL VCCof the transmitter.

2. The DS90C383Atransmitter input and control inputs ac-

3. To implement a falling edge device for the DS90C383A,

CC

cept 3.3V TTL/CMOS levels. They are not 5V tolerant.

the R_FB pin (pin 17) may be tied to ground OR left un­connected (an internal pull-down resistor biases this pin
low). Biasing this pin to Vcc implements a rising edge
device.

10.0 Transmitter Clock Jitter Cycle-to-Cycle

Figures 12 and 13 illustrate the timing of the input clock rela­tive to the input data. The input clock (TxCLKin) is intention­ally shifted to the left −3ns and +3ns to the right when data
(Txin0-27) is high. This 3ns of cycle-to-cycle clock jitter is re-

peated at a period of 2µs, which is the period of the input
data (1µs high, 1µs low). At different operating frequencies
the N Cycle is changed to maintain the desired 3ns cycle-to­cycle jitter at 2µs period.

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11.0 Pin Diagram

DS90C383A

DS100100-23

DS90CF383A

DS100100-24

Application

TABLE 1. Programmable Transmitter (DS90C383A)

Pin Condition Strobe Status

R_FB R_FB = V

CC

R_FB R_FB = GND or NC Falling edge strobe

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DS100100-3

Rising edge strobe

12.0 Physical Dimensions inches (millimeters) unless otherwise noted

DS90C383A/DS90CF383A +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD)

Link-65 MHz, +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

56-Lead Molded Thin Shrink Small Outline Package, JEDEC

Order Number DS90C383AMTD, DS90CF383AMTD

NS Package Number MTD56

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accordance with instructions for use provided in the

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can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.

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