National Semiconductor DS90C2501 Technical data
查询DS90C2501供应商
DS90C2501
Transmitter with built-in scaler for LVDS Display
Interface (LDI)
DS90C2501 Transmitter with built-in scaler for LVDS Display Interface (LDI)
October 2003
General Description
The DS90C2501 is a highly integrated scaling IC with LVDS
transmitter with a scaled resolution up to SXGA+ for single
pixel input. The DS90C2501 is a video controller hub designed to be compatible with Graphic Memory Controller
Hub (GMCH). The input interface can be single or dual DVO
port (12 pin per port). The high quality cubic zoom engine
scales the input graphics into the desired/optimal output
resolution up to 1400x1050 resolution. Advanced video digital signal processing provides gamma correction, and dithering for the display output. A two-wire serial interface is
used to communicate with the host system. The dual high
speed LVDS channels supports single pixel in-single pixel
out, single pixel in-dual pixel out, and dual pixel in-dual pixel
out transmission modes. The DS90C2501 complies to Open
LDI standard, and can be paired up with DS90CF388 receiver or FPD8531x/FPD8731x series integrated timing controller or FPDLink LVDS receivers such as DS90CF364/
DS90CF384A/DS90CF384/DS90CF384A. The LVDS output
is similar to DS90C387 and DS90C387R. Thus, this transmitter can be paired up with DS90CF388, receiver of
112MHz LDI chipset or FPD-Link Receivers in non-DC Balance mode operation which provides GUI/LCD panel/mother
board vendors a wide choice of inter-operation with LVDS
based TFT panels.
This chip is an ideal solution to solve EMI and cable size
problems for high-resolution flat panel applications. It provides a reliable industry standard interface based on LVDS
technology that delivers the bandwidth needed for highresolution panels while maximizing bit times, and keeping
clock rates low to reduce EMI and shielding requirements.
For more details, please refer to the “Applications Information” section of this datasheet.
Features
n Complies with Open LDI and GMCH DVO specification
for digital display interfaces
n 25 to 65 MHz clock in single pixel in to single pixel out
operation.
n 50 to 130 MHz clock in single pixel in to dual pixel out
operation.
n Support 24bit/48bit color TFT LCD with Conventional
and Non-Conventional Color Mappings.
n Support 16bit/32bit color TFT LCD.
n Single pixel transmitter inputs support single pixel GUI
interface.
n Up scaling/panel fitting supports VGA to SXGA+ output
in single pixel input mode at 640x480
800x600
1400x1050
n Independent horizontal and vertical scaling.
n Support dithering (available for 6-bit color only),
programmable smoothing and anti-aliasing filter.
n Programmable digital sharpness, edge enhancement
and contrast control via gamma correction.
n Allow 2% at 200KHz spread spectrum clocking, rejects
cycle-to-cycle jitter (+/− 20% of input data bit time).
n Programmable LCD panel power sequencing.
n Support low voltage swing signal level (1V to 1.8V),
2.5V and 3.3V LVTTL level on CLKINP, CLKINM, D0 to
D23, DE, HSYNC and VSYNC pins
n Support 2.5V/3.3V LVTTL level on configuration pins
n Support 3.3V LVTTL level on GPIO pins
n Available in 10mm x 10mm x 1mm 128pin thermally
enhanced CSP package.
n Two-wire serial communication interface is active during
normal as well as power down mode and support data
rates up to 400KHz.
n TIA/EIA-644, Open LDI, DVO compliance.
@
60Hz, 1024x768@60Hz, 1280x1024@60Hz,
@
60Hz.
@
60Hz,
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
DVO is a registered trademark of Intel Corporation.
AGP or 4x AGP is a registered trademark of Intel Corporation.
© 2003 National Semiconductor Corporation DS200045 www.national.com
Block Diagram
DS90C2501
20004552
www.national.com 2
DS90C2501
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
Supply Voltage (V
CMOS/TTL Input Voltage −0.3V to V
CMOS/TTL Output
Voltage −0.3V to (V
LVDS Driver Output
) −0.3V to +2.8V
CC
) −0.3V to +3.6V
CC3V
+ 0.3V)
CC
CC3V
Typical Package Power Dissipation Capacity
and Max V
CC
128 CSP Package:
DS90C2501 1.8W
Maximum Operating Case Temperature: 97˚C
(measured at top center of package)
ESD Rating:
DS90C2501
(HBM, 1.5kΩ, 100pF)
(EIAJ, 0Ω, 200pF)
@
>
>
70˚C
2kV
250 V
Voltage −0.3V to (VCC+ 0.3V)
LVDS Output Short
Circuit Duration Continuous
Junction Temperature +150˚C
Storage Temperature −65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec.) +260˚C
Recommended Operating
Conditions
Min Nom Max Units
All Supply Voltage except
)
(V
CC3V
V
Supply Voltage 3.0 3.3 3.6 V
CC3V
2.250 2.5 2.750 V
Operating Free Air
Temperature (TA) 0 +25 +70 ˚C
Supply Noise Voltage (V
)
CC
100 mV
P-P
up to 33Mhz
DC Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
LVCMOS/LVTTL DC SPECIFICATIONS (All input pins when operate in LVTTL level except DUAL pin. Note: On ID0, ID1
pins have typical 30K ohm internal pull-down, and ID2 and ID3 pins have typical 3K ohm internal pull-down.)
V
IH
V
IL
V
CL
I
IN
LVCMOS/LVTTL DC SPECIFICATIONS for DUAL pin, pin35
V
DUAL High Level Input Voltage (for
IH
DUAL High Level Input Voltage (for
V
IM
DUAL High Level Input Voltage (for
V
IL
V
CL
I
IN
LVCMOS/LVTTL DC SPECIFICATIONS for MSEN, pin 98
V
OL
LVCMOS/LVTTL DC SPECIFICATIONS (Pin 62 to pin 69 when operate in 3.3V LVTTL level)
V
OH
V
OL
I
OS
High Level Input Voltage V
Low Level Input Voltage V
REF=VCC3V
REF=VCC3V
2.0 V
CC3V
-0.3 0.8 V
Input Clamp Voltage ICL= 18 mA -0.9 -1.5 V
Input Current VIN= 0.4V, or V
V
= GND −15 0 µA
IN
PD=V
CC3V
CC
2.0 V
+1.8 +15 µA
CC
dual pixel in to dual pixel
out).
PD=V
CC3V
1
⁄2VCC−0.1
1
⁄2V
1
CC
⁄2VCC+0.1 V
single pixel in to dual pixel
out).
PD=V
CC3V
0 0.4 V
single pixel in to single pixel
out).
Input Clamp Voltage ICL= 18 mA -0.9 -1.5 V
Input Current VIN= 0.4V, V
V
= Gnd -15 0 µA
IN
Low level Open Drain Output
IOL= 2 mA 0.1 0.3 V
CC
1.8 15 µA
Voltage
High Level Input Voltage IOL= 2 mA 2.2 2.95 V
Low Level Input Voltage 0.055 0.4 V
Output Short Circuit Current V
= 0V -50 −120 mA
OUT
V
V
www.national.com3
DC Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
DS90C2501
Low Voltage Level DC SPECIFICATIONS (pins D0 to D23, CLKINP, CLKINM, DE, HSYNC,VSYNC)
V
DDQ
V
ILSH
V
ILSL
V
REF
LVDS DRIVER DC SPECIFICATIONS (Output pins AnP, AnM, CLKnP and CLKnM)
V
OD
∆V
OD
V
OS
∆V
OS
I
OS
I
OZ
SUPPLY CURRENT
I
1 Transmitter Supply Current
CC
2 Transmitter Supply Current
I
CC
3 Transmitter Supply Current
I
CC
4 Transmitter Supply Current
I
CC
ICCTZ Transmitter Supply Current
Low Swing Voltage from GMCH 1 +1.8 V
Low Swing High Level Input
Voltage
Low Swing Low Level Input
Voltage
Differential Input Reference
V
REF
+
V
DDQ
100mV
0V
REF
100mV
0.475
1
⁄2V
DDQ
0.945 V
Voltage
Differential Output Voltage RL= 100Ω 250 345 450 mV
Change in VODbetween
335mV
Complimentary Output
States
Offset Voltage 1.125 1.32 1.475 V
Change in VOSbetween
1.5 35 mV
Complimentary Output
States
Output Short Circuit Current V
Output TRI-STATE Current PD = 0V, V
when data input and clock
input are at Low Swing level.
when data input and clock
input are at Low Swing level.
when data input and clock
input are at Low Swing level.
= 0V 0 −8.5 -15 mA
OUT
OUT
= 100Ω,CL=
R
L
5 pF, DUAL pin
= GND, BAL =
GND, one 12bit
input, Pattern
Figure 1
= 100Ω,CL=
R
L
5 pF, DUAL pin
1
⁄2VCC, BAL =
=
GND, one 12bit
input, Pattern
Figure 1
= 100Ω,CL=
R
L
5 pF, DUAL pin
= GND, BAL =
=0VorV
CC
f = 65MHz,
scaler off, 2.75V
supply
f = 65 MHz,
scaler off, 3.6V
supply
f = 108MHz,
scaler off, 2.75V
supply
f = 108 MHz,
scaler off, 3.6V
supply.
f = 65 MHz,
scaler on, 2.75V
supply
±
0.1
70 120 mA
38 90 mA
85 130 mA
75 130 mA
330 415 mA
±
10 µA
GND, one 12bit
input
when data input and clock
input are at Low Swing level.
= 100Ω,CL=
R
L
5 pF, DUAL pin
1
⁄2VCC, BAL =
=
f = 108 MHz,
scaler on, 2.75V
supply
483 610 mA
GND, one 12bit
input
75 µA
Power Down
PD = GND. TST1, TST2, TST3, ID0,
ID1, ID2, ID3, A0, A1, A2, RES1,
RES2, RES3, RES4 = GND, BAL =
GND.
V
-
V
www.national.com 4
Two-Wire Serial Communication Interface
Unless otherwise noted, below specifications apply for VCC3V pin = 3.0V to 3.6V.
Symbol Parameter Conditions Min Typ Max Units
V
(1) Logical“1”input voltage 2.1 V
IN
V
(0) Logical“0”input voltage 0.8 V
IN
V
OL
Serial Bus Low level output
IOL= 3mA 0.1 0.4 V
voltage
= 6mA 0.15 0.6 V
I
OL
Recommended DVO Port Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Min Typ Max Units
TCIT TxCLK IN Transition Time (Figure 4) DUAL = Gnd 0.8 1.2 2.4 ns
TCIP TxCLK IN Period (Figure 5) DUAL = Gnd 5.9 T 40 ns
TCIH TxCLK in High Time (Figure 5) 0.35T 0.5T 0.65T ns
TCIL TxCLK in Low Time (Figure 5) 0.35T 0.5T 0.65T ns
TXIT D0 to D23 Transition Time 1 ns
VDDQ Low Swing Voltage Amplitude from GMCH 1.0 1.8 V
DS90C2501
www.national.com5
AC Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Min Typ Max Units
DS90C2501
LLHT LVDS Low-to-High Transition Time (Figure 3). (Note 7) 0.14 0.8 ns
LHLT LVDS High-to-Low Transition Time (Figure 3). (Note 7) 0.11 0.8 ns
TBIT Transmitter Output Bit Width DUAL pin = V
Gnd
DUAL pin =
TCCS TxOUT Channel to Channel Skew 100 ps
TPPOS0 Transmitter Output Pulse Position for Bit 0
(previous cycle) from CLK1P rising edge
f = 65 MHz, DUAL pin
=V
CC
(Note 7).
TPPOS1 Transmitter Output Pulse Position for Bit1
(previous cycle) from CLK1P rising edge.
f = 65 MHz, DUAL pin
=V
CC
(Note 7)
TPPOS2 Transmitter Output Pulse Position for Bit2
from CLK1P rising edge. (Note 7)
TPPOS3 Transmitter Output Pulse Position for Bit3
from CLK1P rising edge. (Note 7)
TPPOS4 Transmitter Output Pulse Position for Bit4
from CLK1P rising edge. (Note 7)
TPPOS5 Transmitter Output Pulse Position for Bit5
from CLK1P rising edge. (Note 7)
TPPOS6 Transmitter Output Pulse Position for Bit6
from CLK1P rising edge. (Note 7)
f = 65 MHz, DUAL pin
=V
CC
f = 65 MHz, DUAL pin
=V
CC
f = 65 MHz, DUAL pin
=V
CC
f = 65 MHz, DUAL pin
=V
CC
f = 65 MHz, DUAL pin
=V
CC
TSTC DxIN Setup to CLKINP (Figure 6) (Note 7) 0.8 ns
THTC DxIN Hold to CLKINP (Figure 6) (Note 7) 0.8 ns
TJCC Transmitter Jitter Cycle-to-cycle (Note 4) f = 85 MHz, DUAL pin
= Gnd
f = 54 MHz, DUAL pin
=V
CC
TPLLS Transmitter Phase Lock Loop Set (Figure 7) (Note 7) 10 ms
TPDD Transmitter Powerdown Delay (Figure 8) (Note 7) 100 ns
Transmitter Input to Output Latency for
f = 170 MHz (Note 6) 1.5 TCIP
single in-to-dual out mode. Figure 9
or
CC
1
⁄2V
CC
1/7 TCIP ns
2/7 TCIP ns
−0.49 0 +0.49 ns
(1/7)TCIP
−0.49
(2/7)TCIP
−0.49
(3/7)TCIP
−0.49
(4/7)TCIP
−0.49
(5/7)TCIP
−0.49
(6/7)TCIP
−0.49
(1/7)TCIP (1/7)TCIP
+0.49
(2/7)TCIP (2/7)TCIP
+0.49
(3/7)TCIP (3/7)TCIP
+0.49
(4/7)TCIP (4/7)TCIP
+0.49
(5/7)TCIP (5/7)TCIP
+0.49
(6/7)TCIP (6/7)TCIP
+0.49
114 ps
114 ps
+4.1
ns
ns
ns
ns
ns
ns
ns
www.national.com 6
Two-Wire Serial Communication Interface Switching Characteristics
Unless otherwise noted, below specifications apply for VCC3V pin = +3.3V, load capacitance on output lines = 80 pF. Load capacitance on output lines can be up to 400pF provided that external pull-up is on board. The following parameters are the timing relationship between SCL and SDA signals related to the DS90C2501.
Symbol Parameter Min Typ Max Units
t
1
t
2
t
3
t
4
t
5
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V
Note 4: The limits are based on bench characterization of the device’s jitter response over the power supply voltage range. Output clock jitter is measured with a
cycle-to-cycle jitter of
calculating system margin as described in AN-1059.
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output pulse positions
(min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable) and clock jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle).
Note 6: From V = 1.25V of CLKINP to V
Note 7: Guaranteed by Design
SCL (Clock) Period 2.5
Data in Set-Up Time to SCL High 100 ns
Data Out Stable after SCL Low 0 ns
SDA Low Set-Up Time to SCL Low (Start Condition) 100 ns
SDA High Hold Time after SCL High (Stop Condition) 100 ns
= 2.5V and V
CC
and ∆VOD).
OD
±
20% data input bit time applied to the input clock signal while data inputs are switching (see figures 11 and 12). This parameter is used when
= 0V of CLK1P when EDGE pin = Gnd, DUAL pin = Gnd or VCCor1⁄2VCC, BAL pin= Gnd.
DIFF
= 3.3V at TA= +25˚C.
CC3V
2000
(Note 7)
µs
DS90C2501
AC Timing Diagrams
FIGURE 1. “Alternate High/Low” Test Pattern in 12-bit Input Mode (Note 8)
20004532
www.national.com7
AC Timing Diagrams (Continued)
DS90C2501
20004551
FIGURE 2. “16 Grayscale” Test Pattern in 12-bit Input Mode(Note 9)
Note 8: The “Alternate High/Low” test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 9: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
www.national.com 8
AC Timing Diagrams (Continued)
FIGURE 3. DS90C2501 (Transmitter) LVDS Output Load and Transition Times
FIGURE 4. DS90C2501 (Transmitter) Input Clock Transition Time
DS90C2501
20004512
20004514
FIGURE 5. DS90C2501 (Transmitter) Input Clock High/Low Times
FIGURE 6. Setup/Hold Times, V
20004554
= 0.900V, EDGE = Gnd, DUAL = VCC, BAL = Gnd
REF
20004555
www.national.com9
AC Timing Diagrams (Continued)
DS90C2501
FIGURE 7. DS90C2501 (Transmitter) Phase Lock Loop Set Time
20004519
FIGURE 8. Transmitter Power Down Delay
FIGURE 9. Transmitter Input to Output Lantency
20004521
20004553
www.national.com 10
AC Timing Diagrams (Continued)
DS90C2501
C —Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos —Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference) (Note 10)
Cable Skew — typically 10 ps– 40 ps per foot, media dependent
Note 10: ISI is dependent on interconnect length; may be zero
20004525
FIGURE 10. Receiver Skew Margin
20004508
FIGURE 11. Resistor Network for “DUAL” pin input - recommend using R1=R2=10kΩ±1% for single to dual mode
www.national.com11
DS90C2501 Pin Description
Pin Name Pin No. I/O Type Description
DVO INTERFACE
DS90C2501
D0–D23 17, 16,
15, 14,
13, 12, 9,
8, 7, 6, 5,
4, 32, 31,
30, 29,
28, 27,
26, 25,
I-LVTTL/ Low
Swing (See
signal
V
REF
description
for more
information
on Low
Swing)
24, 23,
22, 21
DE 3 I-LVTTL/ Low
Swing
HSYNC 2 I-LVTTL/ Low
Swing
VSYNC 1 I-LVTTL/ Low
Swing
CLKINP 10 I-LVTTL/ Low
Swing
Differential
CLKINM 11 I-LVTTL/ Low
Swing
Differential
HOST INTERFACE
RESETN
61 I-LVTTL 2.5 Active low RESET signal. Asserting RESETN will reset all internal logic and
S2CCLK 72 I-LVTTL3V This is the clock line for the two-wire serial communication interface. Normally
S2CDAT 71 I/O-LVTTL3V This is the data line for two-wire serial communication interface. A Pull-up
MSEN 98 O-LVTTL 2.5 Interrupt signal. This is an open drain output, a pull-up resistor is required.
PD
99 I-LVTTL 2.5 Power Down Signal. A logic “0” will place the device in power down mode per
CLOCK
REFCLK1 18 I-LVTTL3V Reference clock, — A 3V, 14.318 MHz clock is required for internal control
DVO Port RGB input data
When DUAL pin = GND inputs D0–D11 correspond to LVDS ports A0–A3.
1
When DUAL pin =
⁄2VCC, 1st pixel from D0– D11 corresponds to LVDS ports
A0–A3, 2nd pixel from D0– D11 corresponds to LVDS ports A4–A7.
When DUAL pin = V
, 1st pixel from D0– D11 corresponds to LVDS ports
CC
A0–A3, 2nd pixel from D12– D23 corresponds to LVDS ports A4–A7.
Note: Ports refer to the corresponding differential LVDS pin pairs. The port A nomenclature should not
be confused with the serial interface slave address pins AO-A2.
Display Data Enable. When High, input pixel data is valid to DS90C2501
when R_FDE bit = High (default). See RFDE register field for more
information .
Display Horizontal Sync input control signal.
Display Vertical Sync input control signal.
“Positive” differential pixel clock input. A differential clock is recommended for
applications 65 MHz or higher.
“Minus” differential pixel clock input. A differential clock is recommended for
applications 65 MHz or higher.
clear the Host Interface registers.
a pull-up resistor is required in the system.
resistor is normally required in the system.
Please refer to MDI, RSEN, TSEL and MSEL register fields in Register Field
Definitions for more information. This signal requires support from host
software.
Table 1 below.
When maximum power savings is desired, the PD pin or soft power down bit
(Reg 08h bit 0) should be used to power down the DS90C2501.
LVDS outputs of the device will be in TRI-STATE.
Scaling engine will be powered down, and retain all register values.
PLL will be powered down.
All data input pads will be powered down. V
circuit is powered down. The
REF
two-wire serial communication interface remains active and all register
contents will be retained.
All GPIO pins will be disabled (tri-state if programmed as an output).
ENAVDD, ENABKL, PWM, VSTALL and HIRQ pins remain active and can be
accessed through the two-wire serial communication interface.
and timing. This clock must be stable when the DS90C2501 is powered-up.
www.national.com 12
DS90C2501 Pin Description (Continued)
Pin Name Pin No. I/O Type Description
OPTION SELECTION
BAL 97 I-LVTTL 2.5 Tie this pin to GND.
DUAL 35 I-LVTTL 2.5 LVTTL level input.
Input = GND for single pixel in-to-single pixel out mode. LVDS output
channels A0 to A3 are enabled, A4 to A7 are CLK2 are disable.
Input = V
to A7, CLK1 and CLK2 are enable. Use a 10K typ. pull-up resistor.
Input =
A0 to A7, CLK1 and CLK2 are enabled. See register CFG1 (08h) BPASS field
for more information.
See Figure 11 for example interface circuit.
COLOR 34 I-LVTTL 2.5 LVTTL level input to select RGB to LVDS color mapping.
Tie to GND for 18-bit/36-bit LCD.
Tie to GND to select conventional color mapping for 24-bit/48-bit LCD.
Tie to Logic “1” to select non-conventional color mapping for 24-bit/48-bit
LCD.
A0, A1, A2 115, 116,
117
I-LVTTL 2.5 These are input pins to select the 2-wire Serial Communication Slave Device
Address Lower Bits.
EDGE 36 I-LVTTL 2.5 Selects primary clock edge E1.
Tie to Logic “1” to select Rising edge for E1.
Tie to ground to select Falling edge for E1.
PANEL INTERFACE
A0P, A1P,
A2P, A3P
55, 53,
51, 47
O-LVDS Positive LVDS differential data output.
When DUAL pin = GND, input to D0–D11 will be coming out of A0P to A3P.
For 6-bit color application, no connect for channel A3P.
When DUAL pin =
of A0P to A3P, and the second pixel going in D0–D11 will come out of A4P to
A7P. For 6-bit color application, no connect for channels A3P and A7P.
When DUAL pin = V
A0P to A3P, the second pixel going in D12–D23 will be coming out of A4P to
A7P. For 6-bit color application, no connect for channels A3P and A7P.
A0M, A1M,
A2M, A3M
56, 54,
52, 48
O-LVDS Negative LVDS differential data output.
When DUAL pin = GND, input to D0–D11 will be coming out of A0M to A3M.
For 6-bit color application, no connect for channel A3M.
When DUAL pin =
of A0M to A3M, and the second pixel going in D0–D11 will come out of A4M
to A7M. For 6-bit color application, no connect for channels A3M and A7M.
When DUAL pin = V
A0M to A3M, the second pixel going in D12–D23 will be coming out of A4M
to A7M. For 6-bit color application, no connect for channels A3M and A7M.
A4P, A5P,
A6P, A7P
45, 43,
41, 39
O-LVDS Positive LVDS differential data output for second pixel.
When DUAL pin = GND, input to D0–D11 will be coming out of A0P to A3P.
For 6-bit color application, no connect for channel A3P.
When DUAL pin =
of A0P to A3P, and the second pixel going in D0–D11 will come out of A4P to
A7P. For 6-bit color application, no connect for channels A3P and A7P.
When DUAL pin = V
A0P to A3P, the second pixel going in D12–D23 will be coming out of A4P to
A7P. For 6-bit color application, no connect for channels A3P and A7P.
for dual pixel in-to-dual pixel out mode. LVDS output channel A0
CC
1
⁄2VCCfor single pixel in-to-dual pixel out mode. LVDS output channel
1
⁄2VCC, the first pixel going in D0–D11 will be coming out
, the first pixel going in D0–D11 will be coming out of
CC
1
⁄2VCC, the first pixel going in D0–D11 will be coming out
, the first pixel going in D0–D11 will be coming out of
CC
1
⁄2VCC, the first pixel going in D0–D11 will be coming out
, the first pixel going in D0–D11 will be coming out of
CC
DS90C2501
www.national.com13
DS90C2501 Pin Description (Continued)
Pin Name Pin No. I/O Type Description
OPTION SELECTION
DS90C2501
A4M, A5M,
A6M, A7M
CLK1P 49 O-LVDS Positive LVDS differential clock output.
CLK1M 50 O-LVDS Negative LVDS differential clock output.
CLK2P 37 O-LVDS Additional positive LVDS differential clock output pin. Identical to CLK1P. No
CLK2M 38 O-LVDS Additional negative LVDS differential clock output pin. Identical to CLK1M. No
ID0, ID1, ID2,
ID3
ENAVDD 69 O-LVTTL 2.5 Output to control LCD panel power under software control. Typically, this
ENABKL 68 O-LVTTL 2.5 Output to control LCD panel back light power under software control.
MISCELLANEOUS/TEST
GPIO1,
GPIO2,
GPIO3
CLK_INV 114 I-LVTTL 2.5 This pin is used to invert the polarity of the incoming pixel CLK
RES2 70 I-LVTTL 2.5 This pin is used in production testing and should be tied to GND in normal
RES3 113 I-LVTTL 2.5 This pin is used in production testing and should be tied to GND in normal
RES4 100 I-LVTTL 2.5 This pin is used in production testing and should be tied to GND in normal
PWM 67 O-LVTTL 3V This signal was provided for legacy support and is no longer required. This
VSTALL 66 O-LVTTL 3V This signal was provided for legacy support and is no longer required. This
HIRQ 65 O-LVTTL 3V This signal was provided for legacy support and is no longer required. This
46, 44,
42, 40
O-LVDS Negative LVDS differential data output for second pixel.
When DUAL pin = GND, input to D0–D11 will be coming out of A0M to A3M.
For 6-bit color application, no connect for channel A3M.
1
When DUAL pin =
⁄2VCC, the first pixel going in D0–D11 will be coming out
of A0M to A3M, and the second pixel going in D0–D11 will come out of A4M
to A7M. For 6-bit color application, no connect for channels A3M and A7M.
When DUAL pin = V
, the first pixel going in D0–D11 will be coming out of
CC
A0M to A3M, the second pixel going in D12–D23 will be coming out of A4M
to A7M. For 6-bit color application, no connect for channels A3M and A7M.
connect if not used.
connect if not used.
57, 58,
59, 60
I-LVTTL 2.5 These four pins are used to select one out of 16 pre-determined LCD display
timing information. The values are from 0 to 15. This function requires support
from VBIOS or display driver. Tie these pins to GND when not in use. Tie
these four pins [ID3, ID2, ID1, ID0] to High or Low for selecting LCD panel.
ID0 is the LSB, and ID3 is the MSB. For example: 1000 will select the 9th
LCD panel.
A 4-bit register field [3:0] will be used to store the selected value for the host
to read. See PANEL field for more information.
output is used with a power switch such as a FET circuit to control LCD panel
(Note 11).
V
CC
Typically, this output is used to control the enable on a backlight inverter
(Note 11).
64, 63, 62 I/O-LVTTL 3V General purpose inputs or outputs referenced to GND.
When the device is powered up, this pin defaults to an input.
When the scaler is in the power down state these signals are tri-state if
programmed as outputs (Note 11).
(CLKINP/CLKINM). A logic 0 = Normal, Logic 1 = Invert.
operation.
operation.
operation.
pin should be left open in normal operation.
pin should be left open in normal operation.
pin should be left open in normal operation.
www.national.com 14
DS90C2501 Pin Description (Continued)
Pin Name Pin No. I/O Type Description
OPTION SELECTION
V
REF
TST1, TST2,
TST3
POWER (See Application Information for power supply decoupling requirements)
V
/DV
CC
CC
GND/DGND 33, 73,
3V 121, 127 PWR The VCC3V is required for internal logic and certain 3V I/O.
V
CC
GND3V 120, 126,
SPLLV
CC
SPLLGND 86, 88, 90 PWR Ground returns for scaler PLL circuitry.
PLLV
CC
PLLGND 91, 93, 95 PWR Ground returns for Tx PLL circuitry.
LVDSV
CC
LVDSGND 104, 108 PWR Ground return pins for LVDS output drivers.
LVDSV
3V 101, 103,
CC
LVDSGND3V 102, 106,
Note 11: When device power is applied, it is possible for these outputs to switch to a logic “1” momentarily as the 3.3V is rising and before 2.5V reaches at least
0.8V. During this brief period, the pad control logic could be non-deterministic, RESETN will have no effect. It is recommended these outputs are gated externally
if the system design requires them to remain in the inactive logic “0” state during power-on.
83 I-ANALOG This pin is never to be left floating and never tie to GND.
For LVTTL level data input, tie V
to VCC3V. When V
REF
>
1.8V, input data
REF
is set to LVTTL level.
For low voltage swing level data input, tie V
host interface) V
is from the host. When V
DDQ
REF
to1⁄2V
DDQ(VDDQ
<
=1.0V, indicates input
REF
provided by
data is in low voltage swing mode.
Input data = logic High = V
Input data = logic Low = V
+100 mV in low voltage swing level.
REF
−100 mV in low voltage swing level.
REF
19, 20, 85 I-LVTTL 2.5 These pins are used in production testing and should be tied to GND in
normal operation.
81, 82,
75, 77,
PWR Power supply pins (pin 75, 77, 81, 82, 96, 119, 123, and 125) for 2.5V LVTTL
inputs and digital circuitry.
96, 119,
123, 125
PWR GND or DGND reference for 2.5V TTL inputs and digital circuitry.
74, 76,
78, 79,
80, 84,
118, 122,
124
During power up stage, voltage readings on these pins must be higher than
2.5V pins.
PWR Ground return pins for V
3V powered logic.
CC
128
87, 89 PWR 2.5V power supply pins for scaler PLL circuitry. It is not recommended to
share this power with PLLV
.
CC
92, 94 PWR 2.5V power supply pins for Tx PLL circuitry. It is not recommended to share
this power with SPLLV
.
CC
105, 109 PWR Power supply pins for LVDS output drivers.
PWR 3V power supply pins for LVDS output drivers.
107, 111
During power up stage, voltage readings on these pins must be higher than
2.5V pins.
PWR Ground return pins for 3V LVDS outputs.
110, 112
DS90C2501
www.national.com15
Loading...