DS25CP152
3.125 Gbps LVDS 2x2 Crosspoint Switch
DS25CP152 3.125 Gbps LVDS 2x2 Crosspoint Switch
January 17, 2008
General Description
The DS25CP152 is a 3.125 Gbps 2x2 LVDS crosspoint switch
optimized for high-speed signal routing and switching over
lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal
integrity and noise immunity. The non-blocking architecture
allows connections of any input to any output or outputs.
Wide input common mode range allows the switch to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires a minimal
space on the board while the flow-through pinout allows easy
board layout. Each differential input and output is internally
terminated with a 100Ω resistor to lower device return losses,
reduce component count and further minimize board space.
Typical Application
Features
DC - 3.125 Gbps low jitter, low skew, low power operation
■
Pin configurable, fully differential, non-blocking
■
architecture
On-chip 100Ω input and output terminations minimize
■
return losses, reduce component count and minimize
board space
8 kV ESD on LVDS I/O pins protects adjoining
■
components
Small 4 mm x 4 mm LLP-16 space saving package
■
Applications
High-speed channel select applications
■
Clock and data buffering and muxing
■
OC-48 / STM-16
■
SD/HD/3G HD SDI Routers
■
30021803
© 2008 National Semiconductor Corporation 300218 www.national.com
Ordering Code
NSID Function
DS25CP152TSQ 2x2 LVDS Crosspoint Switch
DS25CP152
Block Diagram
Connection Diagram
30021801
DS25CP152 Pin Diagram
Pin Descriptions
Pin Name Pin
Number
IN0+, IN0- ,
IN1+, IN1-
OUT0+, OUT0-,
OUT1+, OUT1-
SEL0, SEL1 7, 8 I, LVCMOS
EN0, EN1 14, 13 I, LVCMOS
NC 6, 15 I, LVCMOS "NO CONNECT" pins.
VDD 16 Power Power supply pin.
GND 5, DAP Power Ground pin and Device Attach Pad (DAP) ground.
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1, 2,
3, 4
12, 11,
10, 9
I/O, Type Pin Description
I, LVDS Inverting and non-inverting high speed LVDS input pins.
O, LVDS Inverting and non-inverting high speed LVDS output pins.
Switch configuration pins. There is a 20 kΩ pulldown resistor on
each pin.
Output enable pins. There is a 20 kΩ pulldown resistor on each
pin.
30021802
DS25CP152
Absolute Maximum Ratings (Note 4)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage −0.3V to +4V
LVCMOS Input Voltage −0.3V to (VCC + 0.3V)
LVDS Input Voltage −0.3V to +4V
LVDS Differential Input Voltage 0V to 1.0V
LVDS Output Voltage −0.3V to (VCC + 0.3V)
LVDS Differential Output Voltage 0V to 1.0V
LVDS Output Short Circuit Current
Duration
Junction Temperature +150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range
Soldering (4 sec.) +260°C
Maximum Package Power Dissipation at 25°C
SQA Package 2.99W
Derate SQA Package 23.9 mW/°C above +25°C
5 ms
Package Thermal Resistance
θ
θ
JA
JC
+41.8°C/W
+6.9°C/W
ESD Susceptibility
HBM (Note 1)
MM (Note 2)
CDM (Note 3)
Note 1: Human Body Model, applicable std. JESD22-A114C
Note 2: Machine Model, applicable std. JESD22-A115-A
Note 3: Field Induced Charge Device Model, applicable std.
JESD22-C101-C
≥8 kV
≥250V
≥1250V
Recommended Operating Conditions
Min Typ Max Units
Supply Voltage (VCC) 3.0 3.3 3.6 V
Receiver Differential Input
Voltage (VID)
Operating Free Air
Temperature (TA)
0 1 V
−40 +25 +85 °C
DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7)
Symbol Parameter Conditions Min Typ Max Units
LVCMOS DC SPECIFICATIONS
V
IH
V
IL
I
IH
I
IL
V
CL
LVDS INPUT DC SPECIFICATIONS
V
ID
V
TH
V
TL
V
CMR
I
IN
C
IN
R
IN
High Level Input Voltage 2.0 V
CC
Low Level Input Voltage GND 0.8 V
High Level Input Current VIN = 3.6V
40 175 250
VCC = 3.6V
Low Level Input Current VIN = GND
0 ±10
VCC = 3.6V
Input Clamp Voltage ICL = −18 mA, VCC = 0V −0.9 −1.5 V
Input Differential Voltage 0 1 V
Differential Input High Threshold
Differential Input Low Threshold
VCM = +0.05V or VCC-0.05V
0 +100 mV
−100 0 mV
Common Mode Voltage Range VID = 100 mV 0.05 VCC -
0.05
Input Current
VIN = +3.6V or 0V
VCC = 3.6V or 0V
Input Capacitance Any LVDS Input Pin to GND
Input Termination Resistor Between IN+ and IN-
±1 ±10
1.7 pF
100
V
μA
μA
V
μA
Ω
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Symbol Parameter Conditions Min Typ Max Units
LVDS OUTPUT DC SPECIFICATIONS
V
OD
DS25CP152
ΔV
V
OS
ΔV
I
OS
C
OUT
R
OUT
Differential Output Voltage
Change in Magnitude of VOD for Complimentary
OD
Output States
Offset Voltage
Change in Magnitude of VOS for Complimentary
OS
Output States
RL = 100Ω
RL = 100Ω
250 350 450 mV
-35 35 mV
1.05 1.2 1.375 V
-35 35 mV
Output Short Circuit Current (Note 8) OUT to GND -35 -55 mA
OUT to V
CC
Output Capacitance Any LVDS Output Pin to GND
Output Termination Resistor Between OUT+ and OUT-
7 55 mA
1.2 pF
100
SUPPLY CURRENT
I
I
CC
CCZ
Supply Current EN0 = EN1 = High 64 77 mA
Supply Current with Outputs Disabled EN0 = EN1 = Low 23 29 mA
Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and
ΔVOD.
Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
Ω
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AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified (Notes 9, 10)
Symbol Parameter Conditions Min Typ Max Units
LVDS OUTPUT AC SPECIFICATIONS
t
PLHD
t
PHLD
t
SKD1
t
SKD2
t
SKD3
t
LHT
t
HLT
t
ON
t
OFF
t
SEL
JITTER PERFORMANCE (Note 11)
t
RJ1
t
RJ2
t
DJ1
t
DJ2
t
TJ1
t
TJ2
Differential Propagation Delay Low to
High (Note 11)
Differential Propagation Delay High to
RL = 100Ω
340 500 ps
344 500 ps
Low (Note 11)
Pulse Skew |t
PLHD
− t
PHLD
|
4 35 ps
(Notes 11, 12)
Channel to Channel Skew
12 40 ps
(Notes 11, 13)
Part to Part Skew
50 150 ps
(Notes 11, 14)
Rise Time (Note 11)
Fall Time (Note 11) 65 120 ps
Output Enable Time
Output Disable Time
Select Time
Random Jitter (RMS Value)
(Note 15)
Deterministic Jitter (Peak to Peak)
(Note 16)
Total Jitter (Peak to Peak)
(Note 17)
RL = 100Ω
ENn = LH to output active
ENn = HL to output inactive
SELn LH or HL to output
VID = 350 mV
VCM = 1.2V
Clock (RZ)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps 0.5 1 ps
3.125 Gbps 0.5 1 ps
2.5 Gbps 8 25 ps
3.125 Gbps 3 19 ps
2.5 Gbps 0.04 0.08
3.125 Gbps 0.03 0.09
65 120 ps
7 20
5 12 ns
3.5 12 ns
UI
UI
DS25CP152
μs
P-P
P-P
Note 9: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 10: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 11: Specification is guaranteed by characterization and is not tested in production.
Note 12: t
going edge of the same channel.
Note 13: t
all outputs).
Note 14: t
devices at the same VCC and within 5°C of each other within the operating temperature range.
Note 15: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Note 16: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted
algebraically.
Note 17: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.
, |t
− t
SKD1
PLHD
, Channel to Channel Skew, is the difference in propagation delay (t
SKD2
, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to
SKD3
|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
PHLD
or t
PLHD
) among all output channels in Broadcast mode (any one input to
PHLD
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DC Test Circuits
DS25CP152
FIGURE 1. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
30021820
30021821
FIGURE 2. Differential Driver AC Test Circuit
30021822
FIGURE 3. Propagation Delay Timing Diagram
FIGURE 4. LVDS Output Transition Times
30021823
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Functional Description
The DS25CP152 is a 3.125 Gbps 2x2 LVDS digital crosspoint
switch optimized for high-speed signal routing and switching
TABLE 1. Switch Configuration Truth Table
S1 S0 OUT1 OUT0
0 0 IN0 IN0
0 1 IN0 IN1
1 0 IN1 IN0
1 1 IN1 IN1
TABLE 2. Output Enable Truth Table
EN1 EN0 OUT1 OUT0
0 0 Disabled Disabled
0 1 Disabled Enabled
1 0 Enabled Disabled
1 1 Enabled Enabled
DS25CP152
over lossy FR-4 printed circuit board backplanes and balanced cables.
7 www.national.com
Input Interfacing
The DS25CP152 accepts differential signals and allows simple AC or DC coupling. With a wide common mode range, the
DS25CP152 can be DC-coupled with all common differential
DS25CP152
drivers (i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the DS25CP152 inputs are internally
terminated with a 100Ω resistor.
Typical LVDS Driver DC-Coupled Interface to DS25CP152 Input
Typical CML Driver DC-Coupled Interface to DS25CP152 Input
30021831
30021832
Typical LVPECL Driver DC-Coupled Interface to DS25CP152 Input
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30021833
Output Interfacing
The DS25CP152 outputs signals that are compliant to the
LVDS standard. Its outputs can be DC-coupled to most common differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers
and assumes that the receivers have high impedance inputs.
While most differential receivers have a common mode input
range that can accomodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to
Typical Performance
DS25CP152
A 3.125 Gbps NRZ PRBS-7 After 2"
30021851
Differential FR-4 Stripline
V:100 mV / DIV, H:50 ps / DIV
Total Jitter as a Function of Input Common Mode Voltage
30021854
A 2.5 Gbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
V:100 mV / DIV, H:75 ps / DIV
Total Jitter as a Function of Data Rate
30021855
30021850
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Physical Dimensions inches (millimeters) unless otherwise noted
DS25CP152
Order Number DS25CP152TSQ
(See AN-1187 for PCB Design and Assembly Recommendations)
NS Package Number SQA16A
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Notes
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DS25CP152 3.125 Gbps LVDS 2x2 Crosspoint Switch
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