The DS10BR254 is a 1.5 Gbps 1:4 LVDS repeater optimized
for high-speed signal routing and distribution over FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and
noise immunity.
The device has two different LVDS input channels and a select pin determines which input is active. A loss-of-signal
) circuit monitors both input channels and a unique
(LOS
LOS pin is asserted when no signal is detected at that input.
Wide input common mode range allows the switch to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires a minimal
space on the board while the flow-through pinout allows easy
board layout. Each differential input and output is internally
terminated with a 100Ω resistor to lower device return losses,
reduce component count and further minimize board space.
Typical Application
Features
DC - 1.5 Gbps low jitter, low skew, low power operation
■
Wide Input Common Mode Voltage Range allows for DC-
■
coupled interface to LVDS, CML and LVPECL drivers
Redundant inputs
■
circuitry detects open inputs fault condition
LOS
■
Integrated 100Ω input and output terminations
■
8 kV ESD on LVDS I/O pins protects adjoining
■
components
Small 6 mm x 6 mm LLP-40 space saving package
SEL_in14I, LVCMOSThis pin selects which LVDS input is active.
LOS1,
LOS2
PWDN0,
PWDN1,
PWDN2,
PWDN3
PWDN38I, LVCMOSDevice power down pin. When the PWDN is set to L, the device
VDD3, 8,
GND16, DAP PowerGround pin and a pad (DAP - die attach pad).
NC1, 2
4, 5,
6, 7,
29, 28,
27, 26,
24, 23,
22, 21
37,
36
35,
34
33,
32
15,25, 30
9, 10,
11, 12,
13, 17,
18, 19,
20, 31,
39, 40
I/O, TypePin Description
I, LVDSInverting and non-inverting high speed LVDS input pins.
O, LVDSInverting and non-inverting high speed LVDS output pins.
O, LVCMOSLoss Of Signal output pins, LOSn report when an open input fault
condition is detected at the input, INn. These are open drain
outputs. External pull up resistors are required.
I, LVCMOSChannel output power down pin. When the PWDNn is set to L, the
channel output OUTn is in the power down mode.
is in the power down mode.
PowerPower supply pins.
NCNO CONNECT pins. May be left floating.
3www.national.com
Absolute Maximum Ratings (Note 4)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
DS10BR254
Supply Voltage−0.3V to +4V
LVCMOS Input Voltage−0.3V to (VCC + 0.3V)
LVCMOS Output Voltage−0.3V to (VCC + 0.3V)
LVDS Input Voltage−0.3V to +4V
LVDS Differential Input Voltage0.0V to +1V
LVDS Output Voltage−0.3V to (VCC + 0.3V)
LVDS Differential Output Voltage0.0V to +1V
LVDS Output Short Circuit Current
Duration
Junction Temperature+150°C
Storage Temperature Range−65°C to +150°C
Lead Temperature Range
Soldering (4 sec.)+260°C
Maximum Package Power Dissipation at 25°C
SQA Package4.65W
Derate SQA Package37.2 mW/°C above +25°C
5 ms
Package Thermal Resistance
θ
θ
JA
JC
+26.9°C/W
+3.8°C/W
ESD Susceptibility
HBM (Note 1)
MM (Note 2)
CDM (Note 3)
Note 1: Human Body Model, applicable std. JESD22-A114C
Output Short Circuit Current (Note 8)OUT to GND-35-55mA
OUT to V
CC
Output CapacitanceAny LVDS Output Pin to GND
Output Termination ResistorBetween OUT+ and OUT-
755mA
1.2pF
100
Ω
SUPPLY CURRENT
I
I
CC
CCZ
Supply CurrentPWDN = H113135mA
Power Down Supply CurrentPWDN = L5060mA
Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD andΔVOD.
Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
DS10BR254
5www.national.com
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
DS10BR254
SymbolParameterConditionsMinTypMaxUnits
LVDS OUTPUT AC SPECIFICATIONS
t
PLHD
t
PHLD
Differential Propagation Delay Low to
High (Note 11)
Differential Propagation Delay High to
RL = 100Ω
440650ps
400650ps
Low (Note 11)
t
SKD1
Pulse Skew |t
PLHD
− t
PHLD
|
40100ps
(Notes 11, 12)
t
SKD2
Channel to Channel Skew
40125ps
(Notes 11, 13)
t
SKD3
Part to Part Skew
50200ps
(Notes 11, 14)
t
t
t
t
t
LHT
HLT
ON
OFF
SEL
Rise Time (Note 11)
Fall Time (Note 11)150300ps
Any PWDN to Output Active Time
Any PWDN to Output Inactive Time
Select Time
RL = 100Ω
150300ps
820
512ns
512ns
JITTER PERFORMANCE (Note 11)
t
RJ1
t
RJ2
t
RJ3
t
RJ4
t
DJ1
t
DJ2
t
DJ3
t
DJ4
t
TJ1
t
TJ2
t
TJ3
t
TJ4
Note 9: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 10: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 11: Specification is guaranteed by characterization and is not tested in production.
Note 12: t
going edge of the same channel.
Note 13: t
all outputs).
Note 14: t
devices at the same VCC and within 5°C of each other within the operating temperature range.
Note 15: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Note 16: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted
algebraically.
Note 17: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.
Random Jitter
(RMS Value)
(Note 15)
Deterministic Jitter
(Peak to Peak Value)
(Note 16)
Total Jitter
(Note 17)
, |t
− t
SKD1
PLHD
, Channel to Channel Skew, is the difference in propagation delay (t
SKD2
, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to
SKD3
|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
PHLD
VID = 350 mV
VCM = 1.2V
Clock (RZ)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
or t
PLHD
135 MHz0.51ps
311 MHz0.51ps
503 MHz0.51ps
750 MHz0.51ps
270 Mbps622ps
622 Mbps621ps
1.0625 Gbps918ps
1.5 Gbps917ps
270 Mbps0.010.03
622 Mbps0.010.03
1.0625 Gbps0.010.04
1.5 Gbps0.010.06
) among all output channels in Broadcast mode (any one input to
PHLD
UI
UI
UI
UI
μs
P-P
P-P
P-P
P-P
www.national.com6
DC Test Circuits
FIGURE 1. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
DS10BR254
30007820
FIGURE 2. Differential Driver AC Test Circuit
30007822
FIGURE 3. Propagation Delay Timing Diagram
FIGURE 4. LVDS Output Transition Times
30007821
30007823
7www.national.com
Functional Description
The DS10BR254 is a 1.5 Gbps 1:4 LVDS repeater optimized
for high-speed signal routing and distribution over lossy FR-4
printed circuit board backplanes and balanced cables.
DS10BR254
TABLE 1. Input Select Truth Table
CONTROL Pin (SEL_in) StateInput Selected
0IN1
1IN2
www.national.com8
DS10BR254
Input Interfacing
The DS10BR254 accepts differential signals and allows simple AC or DC coupling. With a wide common mode range, the
DS10BR254 can be DC-coupled with all common differential
Typical LVDS Driver DC-Coupled Interface to an DS10BR254 Input
drivers (i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the DS10BR254 inputs are internally
terminated with a 100Ω resistor.
30007831
Typical CML Driver DC-Coupled Interface to an DS10BR254 Input
Typical LVPECL Driver DC-Coupled Interface to an DS10BR254 Input
30007832
30007833
9www.national.com
Output Interfacing
The DS10BR254 outputs signals compliant to the LVDS standard. Its outputs can be DC-coupled to most common differential receivers. The following figure illustrates typical DC-
DS10BR254
coupled interface to common differential receivers and
assumes that the receivers have high impedance inputs.
While most differential receivers have a common mode input
range that can accomodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to
implementing the suggested interface implementation.
Typical DS10BR254 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
30007834
www.national.com10
Typical Performance
DS10BR254
A 1.5 Gbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
V:100 mV / DIV, H:100 ps / DIV
A 622 Mbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
V:100 mV / DIV, H:200 ps / DIV
30007863
30007861
A 1.06 Gbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
V:100 mV / DIV, H:200 ps / DIV
A 270 Mbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
V:100 mV / DIV, H:500 ps / DIV
30007862
30007860
Supply Current as a Function of a Number of Outputs Used
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DS10BR254 1.5 Gbps 1:4 LVDS Repeater
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