National Semiconductor DP83865 Technical data

DP83865 Gig PHYTER® V
10/100/1000 Ethernet Physical Layer

General Description

The DP83865 is a fully featured Physical Layer transceiver
with integrated PMD sublayers to support 10BASE-T,
100BASE-TX and 1000BASE-T Ethernet protocols.

The DP83865 is an ul tra low po wer v ersion of t he DP8 3861
and DP83891. It uses advanced 0.18 um, 1.8 V CMOS
technology, fabricated at National Semiconductor’s South
Portland, Maine facility.

The DP83865 is designed for easy implementation of
10/100/1000 Mb/s Ethernet LANs. It interfaces directly to
Tw isted Pai r media vi a an externa l transfo rmer. This devic e
interfaces directly to the MAC layer through the IEEE

802.3u Standard Media Independent Interface (MII), the
IEEE 802.3z Gigabit Media Independent Interface (GMII),
or Reduced GMII (RGMII).

The DP83865 is a fourth generation Gigabit PHY with field
proven architecture and performance. Its robust perfor­mance ensures drop-in replacement of existing
10/100 Mbps equipmen t wi th t en to o ne hundr ed time s t he
performance using the existing networking infrastructure.

Applications

The DP83865 fits applications in:

■ 10/100/1000 Mb/s capable node cards

■ Switches with 10/100/1000 Mb/s capable ports

■ High speed uplink ports (backbone)

Features

■ Ultra low power consumption typically 1.1 watt

■ Fully compliant with IEEE 802.3 10BASE-T, 100BASE-

TX and 1000BASE-T specifications

■ Integrated PMD sub layer featuring adaptive e qualization

and baseline wander compensation according to ANSI
X3.T12

■ 3.3 V or 2.5 V MAC interfaces:

■ IEEE 802.3u MII

■ IEEE 802.3z GMII

■ RGMII version 1.3

■ User progr ammable GMII pin ordering

■ IEEE 802.3u Auto-Negotiation and Parallel Detection

■ Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s,

and 10 Mb/s full duplex and half duplex devices

■ Speed Fallback mode to achieve quality link

■ Cable length estimator

■ LED support for activity, full / half duplex, link1000,

link100 and link10, user programmable (manual on/off),
or reduced LED mode

■ Supports 25 MHz operation with crystal or oscillator.

■ Requires only two power supplies, 1.8 V (core and

analog) and 2.5 V (analog and I/O). 3.3V is supported
as an alternative supply for I/O voltage

■ User programable interrupt

■ Supports Auto-MDIX at 10, 100 and 1000 Mb/s

■ Supports JTAG (IEEE1 149.1 )

■ 128-pin PQFP package (14mm x 20mm)

DP83865 Gig PHYTER® V 10/100/1000 Ethernet Physical Layer

October 2004

SYSTEM DIAGRAM

MII
GMII
RGMII

10BASE-T
100BASE-TX
1000BASE-T

DP83820

10/100/1000 Mb/s
ETHERNET MAC

PHYTER® is a registered trademark of National Semiconductor Corporation

© 2004 National Semiconductor Corporation www.national.com

ETHERNET PHYSICAL LAYER

25 MHz

crystal or oscillator

DP83865

10/100/1000 Mb/s

STATUS

RJ-45

MAGNETICS

LEDs

Block Diagram

DP83865

MGMT INTERFACE

MDIO

MDC

Interrupt

COMBINED MII / GMII / RGMII INTERFACE

µC MGMT

& PHY CNTRL

100BASE-TX

10BASE-T

Block Block Block

MII

100BASE-TX

PCS

100BASE-TX

PMA

MII

10BASE-T

PLS

10BASE-T

PMA

GTX_CLK

TX_EN

TXD[7:0]

TX_ER

1000BASE-T

1000BASE-T

PCS

1000BASE-T

PMA

TX_CLK

RX_CLK

COL

CRS

RX_ER

MUX/DMUX

GMIIMII

GMII

RX_DV

RXD[7:0]

Echo cancellation
Crosstalk cancellation
ADC
Decode/Descramble
Equalization
Timing
Skew compensation
BLW

100BASE-TX

PMD

MLT-3
100 Mb/s

Manchester
10 Mb/s

PAM-5

17 Level PR Shaped

125 Msymbols/s

DAC/ADC

SUBSYSTEM

TIMING

DRIVERS/

RECEIVERS

DAC/ADC

TIMING BLOCK

MAGNETICS

4-pair CAT-5 Cable

www.national.com 2

Table of Contents

1.0 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

1.1 MAC Interfaces (MII, GMII, and RGMII) . . . . . . .5

1.2 Management Interface . . . . . . . . . . . . . . . . . . . .7

1.3 Media Dependent Interface . . . . . . . . . . . . . . . .7

1.4 JTAG In te r f a c e . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.5 Clock In terface . . . . . . . . . . . . . . . . . . . . . . . . . .8

1.6 Device Configuration and LED Interface . . . . . . . .8

1.7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.8 Power and Ground Pins . . . . . . . . . . . . . . . . . . . .11

1.9 Special Connect Pins . . . . . . . . . . . . . . . . . . . .11

1.10 Pin Assignments in the Pin Number Order . . . .12

2.0 Regis t e r B lo c k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.1 Register Definitions . . . . . . . . . . . . . . . . . . . . . . .18

2.2 Regis te r M a p . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3 Register Description . . . . . . . . . . . . . . . . . . . . . .21

3.0 Confi guration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

3.1 Accessing Expanded Memory Space . . . . . . . . .40

3.2 Manual Configuration . . . . . . . . . . . . . . . . . . . . . .40

3.3 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . .41

3.4 Auto-Negotiation Register Set . . . . . . . . . . . . . . .44

3.5 Auto-MDIX resolution . . . . . . . . . . . . . . . . . . . . . .44

3.6 Polari ty C o r rection . . . . . . . . . . . . . . . . . . . . . . . .45

3.7 PHY Address, Strapping Options and LEDs . . . . 45

3.8 Reduced LED Mode . . . . . . . . . . . . . . . . . . . . . .45

3.9 Modulate LED on Error . . . . . . . . . . . . . . . . . . . .45

3.10 MAC In t e r f a c e . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.11 Clock to MAC Enable . . . . . . . . . . . . . . . . . . . . . .46

3.12 MII/GMII/RGMII Isolate Mode . . . . . . . . . . . . . . .46

3.13 Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . .46

3.14 IEEE 802.3ab Test Modes . . . . . . . . . . . . . . . . . .46

3.15 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.16 Low Power Mode / WOL . . . . . . . . . . . . . . . . . . .47

3.17 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . .47

3.18 BIST Configuration . . . . . . . . . . . . . . . . . . . . . . .47

3.19 Cable Length Indicator . . . . . . . . . . . . . . . . . . . . .48

3.20 10BASE-T Half Duplex Loopback . . . . . . . . . . . .48

3.21 I/O Voltage Selection . . . . . . . . . . . . . . . . . . . . . .48

3.22 Non-compliant inter-operability mode . . . . . . . . .48

4.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .49

4.1 1000BASE-T PCS Transmitter . . . . . . . . . . . . . .49

4.2 1000BASE-T PMA Transmitter . . . . . . . . . . . . . .50

4.3 1000BASE-T PMA Receiver . . . . . . . . . . . . . . . .50

4.4 1000BASE-T PCS Receiver . . . . . . . . . . . . . . . .51

4.5 Gigabit MII (GMII) . . . . . . . . . . . . . . . . . . . . . . . .52

4.6 Reduced GMII (RGMII) . . . . . . . . . . . . . . . . . . . . 53

4.7 10BASE-T and 100BASE-TX Transmitter . . . . . .54

4.8 10BASE-T and 100BASE-TX Receiver . . . . . . . .57

4.9 Media Independent Interface (MII) . . . . . . . . . . . .60

5.0 Desig n Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.1 Hardw a re R e s e t . . . . . . . . . . . . . . . . . . . . . . . . . .63

5.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3

5.3 Power Supply Decoupling . . . . . . . . . . . . . . . . . .64

5.4 Sensitive Supply Pins . . . . . . . . . . . . . . . . . . . . . 64

5.5 PCB Layer Stacking . . . . . . . . . . . . . . . . . . . . . . .64

5.6 Layou t N o t e s on MAC Interfac e . . . . . . . . . . . . . . 66

5.7 Twisted Pair Interf a ce . . . . . . . . . . . . . . . . . . . . .66

5.8 RJ-45 Connections . . . . . . . . . . . . . . . . . . . . . . .67

5.9 LED/Strapping Option . . . . . . . . . . . . . . . . . . . . . 67

5.10 Unused Pins and Reserved Pins . . . . . . . . . . . . .67

5.11 I/O Voltage Considerations . . . . . . . . . . . . . . . . .68

5.12 Power-up Recommendations . . . . . . . . . . . . . . .6 8

5.13 Component Selection . . . . . . . . . . . . . . . . . . . . .68

6.0 Electrical Specific a t ions . . . . . . . . . . . . . . . . . . . . . . . 71

6.1 DC Electrical Specification . . . . . . . . . . . . . . . . . 71

6.2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.3 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.4 1000 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . 74

6.5 RGMII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6.6 100 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.7 10 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6.8 Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . 79

6.9 Serial Management Interface Timing . . . . . . . . . 80

6.10 Power Consumption . . . . . . . . . . . . . . . . . . . . . . 81

7.0 Frequently Asked Questions . . . . . . . . . . . . . . . . . . . 82

7.1 Do I need to access any MDIO register to start up

the PHY? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

7.2 I am trying to access the registers through MDIO

and I got invalid data. What should I do? . . . . . 82

7.3 Why can the PHY establish a valid link but can

not transmit or receive data? . . . . . . . . . . . . . . . 82

7.4 What is the difference between TX_CLK,

TX_TCLK, and GTX_CLK? . . . . . . . . . . . . . . . . 82

7.5 What happens to the TX_CLK during 1000 Mbps
operation? Similarly what happens to RXD[4:7]

during 10/100 Mbps operation? . . . . . . . . . . . . . 82

7.6 What happens to the TX_CLK and RX_CLK

during Auto-Negotiation and during idles? . . . . . 82

7.7 Why doesn’t the Gig PHYTER V complete Auto­Negotiation if the link partner is a forced

1000 Mbps PHY? . . . . . . . . . . . . . . . . . . . . . . . . 82

7.8 What determines Master/Slave mode when Auto­Negotiation is disabled in 1000Base-T mode? . . 82

7.9 How long does Auto-Negotiation take? . . . . . . . 83

7.10 How do I measure FLP’s? . . . . . . . . . . . . . . . . . 83

7.11 I have forced 10 Mbps or 100 Mbps operation but

the associated speed LED doesn’t come on. . . . 83

7.12 I know I have good link, but register 0x01, bit 2
“Link Status” doesn’t contain value ‘1’ indicating

good link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

7.13 Your reference design shows pull-up or pull-down
resistors attached to certain pins, which conflict
with the pull-up or pull-down information specified

in the datasheet? . . . . . . . . . . . . . . . . . . . . . . . . 83

7.14 How is the maximum package case temperature

calculated? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

7.15 The DP83865 will establish Link in 100 Mbps
mode with a Broadcom part, but it will not
establish link in 1000 Mbps mode. When this
happens the DP83865’s Link LED will blink on

and off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

7.16 How do I quickly determine the quality of the

link over the cable ? . . . . . . . . . . . . . . . . . . . . . . 83

7.17 What is the power up sequence for DP83865? . 83

7.18 What are some other applicable documents? . . 84

8.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 86

3 www.national.com

PQFP Pin Layout

DP83865

TX_TCLK / MAN_MDIX_STRA P

ACTIVITY_LED / SPEED0_STRAP

LINK10_LED / RLED/SPEED1_STRAP

LINK100_LED / DUPLEX_STRAP
LINK1000_LED / AN_EN_STRAP

DUPLEX_LED / PHYADDR0_STRAP

NON_IEEE_STRAP

RESERVED

INTERRUPT

IO_VDD

VSS

CORE_VDD

VSS

PHYADDR1_STRAP

IO_VDD

VSS
PHYADDR2_STRAP
PHYADDR3_STRAP

CORE_VDD

VSS

IO_VDD

VSS

RESERVED

TCK

CORE_VDD

VSS

TMS

TDO

IO_VDD

VSS

TDI

TRST

RESET

VDD_SEL_STRAP

CORE_VDD

VSS

IO_VDD

VSS

1V8_AVDD1

VSS

43

124

MDIC_N

VSS

121

122

123

46

45

44

MDID_N

MDID_P

VSS

VSS

125

126

127

128

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

42

41

40

39

1V8_AVDD1

MDIC_P

VSS

119

120

MDIB_N

VSS

VSS

115

117

116

118

DP83865DVH

Gig PHYTER V

52

50

48

51

49

47

1V8_AVDD1

MDIA_N

MDIB_P

VSS

VSS

112

113

114

55

54

53

MDIA_P

VSS

VSS

108

110

107

109

111

59

57

60

58

56

1V8_AVDD1

1V8_AVDD1

VSS

VSS

103

106

104

105

102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65

64

61

63

62

BG_REF
2V5_AVDD1
1V8_AVDD3
VSS
1V8_AVDD2
VSS
2V5_AVDD2
PHYADDR4_STRAP
MUL T I_ EN_STRAP / TX_TRIGGER
VSS
CORE_VDD
VSS
IO_VDD
MDIX_EN_STRAP
MAC_CLK_EN_STRAP
CLK_OUT
CLK_IN
CLK_TO_MAC
RESERVED
IO_VDD
VSS
MDC
MDIO
GTX_CLK/TCK
VSS
IO_VDD
TXD0/TX0
TXD1/TX1
VSS
CORE_VDD
TXD2/TX2
TXD3/TX3
VSS
IO_VDD
TXD4
TXD5
TXD6
TXD7

RXD4

CORE_VDD

VSS

RXD5

RXD6

RXD7

RX_DV/RCK

VSS

IO_VDD

RX_ER/RXDV_ER

CRS/RGMII_SEL0

COL/CLK_MAC_FREQ

Figure 1. DP83865 Pinout

Order Part Number: DP83865DVH

www.national.com 4

RXD1/RX1

RXD2/RX2

VSS

RXD3/RX3

IO_VDD

VSS

RX_CLK

TX_CLK/RGMII_SEL1

IO_VDD

RXD0/RX0

VSS

TX_ER

CORE_VDD

TX_EN/TXEN_ER

1.0 Pin Description

The DP83865 pins are c lassifi ed into the fol lowing i nterfac e
categories (each is described in the sections that follow):

— MAC Interfaces
— Management Interface
— Media Dependent Interface
—JTAG Interface
— Clock Interface
— Device Configuration and LED Interfa ce
—Reset
— Power and Ground Pins
— Special Connect Pins

1.1 MAC Interfaces (MII, GMII, and RGMII)

DP83865

Type: I Inputs
Type: O Output
Type: O_Z Tristate Output
Type: I/O_Z Tristate Input_Output
Type: S Strapping Pin
Type: PU Internal Pull-up
Type: PD Internal Pull-down

Signal Name Type

CRS/RGMII_SEL0 O_Z,

S, PD

COL/CLK_MAC_FREQ O_Z,

S, PD

TX_CLK/RGMII_SEL1 O_Z,

S, PD

PQFP

Pin #

40 C ARRIER SENSE or RGMII SELECT: CRS is asserted high to indicate the

presence of a carrier due to receive or transmit activity in Half Duplex mode.
For 10BASE-T and 100BASE-TX Full Duplex operation CRS is as serted when
a received packet is detected. This signal is not defined for 1000BASE-T Full
Duplex mode.

In RGMII mode, the CRS is not used. This pin can be used as a RGMII strap­ping selection pin.

RGMII_SEL1

00= GMII
01= GMII
1 0 = RGMII - HP
1 1 = RGMII - 3COM

39 COLLISION DETECT: Asserted hig h to indic ate dete ction o f a collis ion co ndi-

tion (assertion of CRS due to simultaneous transmit and receive activity) in
Half Duplex modes. This signal is not synchronous to either MII clock
(GTX_CLK, TX_CLK or RX_CLK). This signal is not defined and stays low for
Full Duplex modes.

CLOCK TO MAC FREQUENCY Select:
1 = CLOCK TO MAC output is 125 MHz

0 = CLOCK TO MAC output is 25 MHz

60 TRANSMIT CLOCK or RGMII SELECT: TX_CLK is a cont inu ous cloc k sig nal

generated from reference CLK_IN and driven by the PHY during 10 Mbps or
100 Mbps MII mode. TX_ CLK clocks the data or error ou t of the MAC layer and
into the PHY.

The TX_CLK clock frequency is 2.5 MHz in 10BASE-T and 25 MHz in
100BASE-TX mode.

Note: “TX_CLK” should not be confused with the “TX_TCLK” signal.
In RGMII mode, the TX_CLK is not used. This pin can be used as a RGMII

strapping selection pin. This pin should be pulled high for RGMII interface.

RGMII_SEL0 MAC Interface

Description

5 www.national.com

1.0 Pin Description (Continued)

DP83865

Signal Name Type

TXD0/TX0
TXD1/TX1
TXD2/TX2
TXD3/TX3
TXD4
TXD5
TXD6
TXD7

TX_EN/TXEN_ER I 62 TRANSMIT ENABLE or TRANSMIT ENABLE/ERROR: In MII or GMII mo de ,

GTX_CLK/TCK I 79 GMII and RGMII TRANSMIT CLOCK: This continu ous cloc k signal i s sourced

TX_ER I 61 TRANSM IT ERROR: It is an active high input used in MII mode and GMII

RX_CLK O_Z 57 RECEIVE CLOCK: Provides the recove red receive clocks for d iffe rent modes

RXD0/RX0
RXD1/RX1
RXD2/RX2
RXD3/RX3
RXD4
RXD5
RXD6
RXD7
RX_ER/RXDV_ER O_Z 41 RECEIVE ERROR or RECEIVE DATA AVAILABLE/ERROR: In 10 Mbps,

RX_DV/RCK O_Z 44 RECEIVE DATA VALID or RECEIVE CLOCK: In MII and GMII modes, it is as-

PQFP

Pin #

I76

75
72
71
68
67
66
65

O_Z 56

55
52
51
50
47
46
45

Description

TRANSMIT DATA: These signals carry 4B data nibbles (TXD[3:0]) during 10

Mbps and 100 Mbps MII mode, 4-bit data (TX[3:0]) in RGMII mode, and 8-bit
data (TXD[7:0]) in 1000 Mbps GMII mode. They are synchronous to the trans­mit clocks (TX_CLK, TCK, GTX_CLK).

Transmit data is input to PHY. In MII or GMII mode, the transmit data is en­abled by TX_EN. In RGMII mode, the transmit data is enabled by TXEN_ER.

it is an active high in pu t s ourc ed fro m M AC l ay er t o i ndi ca te t r ans m issio n d ata
is available on the TXD.

In RGMII mode, it combines the transm it en able and the trans m it error si gna ls
of GMII mode using both clock edges.

from the MAC layer to the PHY. Nominal frequency is 125 MHz.

mode forcing the PHY to transmit invalid symbols. The TX_ER signal is syn­chronous to the transmit clocks (TX_CLK or GTX_CLK).

In MII 4B nibble mode, assertion of Transmit Error by t he controller cau ses the
PHY to issue invalid symbols foll owed by Halt (H) s ymbols until dea ssertion oc­curs.

In GMII mode, assertion causes the PHY to emit one or more code-groups that
are invalid data or delimiter in the transmitted frame.

This signal is not used in the RGMII mode.

of operation:

2.5 MHz in 10 Mbps mode.
25 MHz in 100 Mbps mode.
125 MHz in 1000 Mps GMII mode.

This pin is not used in the RGMII mode.
RECEIVE DATA: These signals carry 4-b it d ata nib ble s (RX D[ 3:0 ]) du ring 10

Mbps and 100 Mbps MII mode and 8-bit data bytes (RXD[7:0]) in 1000 Mbps
GMII mode. RXD is synchronou s to the receive clock (RX_CLK). Receive data
is souirced from the PHY to the MAC layer.

Receive data RX[3:0] is u se d i n RGM II m ode . Th e d ata is s yn ch rono us to the
RGMII receive clock (RCK). The rece ive dat a avail able (RXD V_EN) indic ates
valid received data to the MAC layer.

100 Mbps and 1000 Mbps mod e this ac tive high ou tput indica tes that th e PHY
has detected a Receive Error. The RX_ER signal is synchronous with the re­ceive clock (RX_CLK).

In RGMII mode, the receive data available and receive error is combined
(RXDV_ER) using both rising and falling edges of the receive clock (RCK).

serted high to indicate that valid data is present on the corresponding R XD[3:0]
in MII mode and RXD[7:0] in GMII mode.

In RGMII mode, this pin is the recovered receive clock (125MHz).

www.national.com 6

1.0 Pin Description (Continued)

1.2 Management Interface

DP83865

Signal Name Type

MDC I 81 M ANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial man-

MDIO I/O 80 MANAGEMENT DATA I/O: Bi-directional mana geme nt ins tructi on/ data sig nal

INTERRUPT

PQFP

Pin #

agement input/outpu t data. This clo ck may be as ynchronous to the MAC trans ­mit and receive clocks. The maximum clock rate is 2.5 MHz and no minimum.

that may be sourced b y the mana gemen t stati on or the PHY. Thi s pin re quires
a 2kΩ pullup resistor.

O_Z, PU3 MANAGEMENT INTERRUPT: It is an active-low open drain output indicating

to the MAC layer or t o a m ana gm ent interface that an inte rrupt ha s requested.
The interrupt status can be read through the Interrupt Status Register. (See
section “3.15 Interrupt” on page 47.)

If used this pin requires a 2kΩ pullup resistor. This pin is to be left floating if it
is not used.

Description

1.3 Media Dependent Interface

Signal Name Type

MDIA_P
MDIA_N
MDIB_P
MDIB_N
MDIC_P
MDIC_N
MDID_P
MDID_N

PQFP

PIn #

I/O 108

109
114
115
120
121
126
127

Description

Media Dependent Interface: Differential receive and transmit signals.

The TP Interface connects the DP83865 to the CAT-5 cable through a single
common magnetics t ransformer. The se differenti al inputs and ou tputs are c on­figurable to 10BASE-T, 100BASE-TX or 1000BASE-T signalling:

The DP83865 will au tomat icall y con figure the dri ver ou tput s for t he prop er sig ­nal type as a result of either forced configuration or Auto-Negotiation. The au­tomatic MDI / MDIX configuration allows for transmit and receive channel
configuration and p olarity con figurati on be tween channel s A and B , and C and
D.

NOTE: During 10/100 Mbps operation only MDIA_P, MDIA_N, MDIB_P and
MDIB_N are active. MDIA_P and MDIA_N are transmitting only and MDIB_P
and MDIB_N are receiving only. (See section “3.5Auto-MDIX resolution” on
page 44)

1.4 JTAG Interface

Signal Name Type

TRST

TDI I, PU 31 TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is scanned

TDO O 28 TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most recent

TMS I, PU 27 TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS pin se-

PQFP

PIn #

I, PD 32 TEST RESET: IEEE 1149.1 Test Reset pin, active low reset provid es for asyn-

chronous reset of the Tap Controller. This reset has no effect on the device
registers.

This pin should be pulled down through a 2kΩ resistor if not used.

into the device via TDI.
This pin should be left floating if not used.

test results are scanned out of the device via TDO.
This pin should be left floating if not used.

quences the Tap Controller (16-state FSM) to select the desired test instruc­tion.

This pin should be left floating if not used.

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Description

1.0 Pin Description (Continued)

DP83865

Signal Name Type

TCK I 24 TEST CLOCK: IEEE 1149.1 Test Clock input, primary clo ck s ou rce fo r al l test

PQFP

PIn #

Description

logic input and output controlled by the testing entity.
This pin should be left floating if not used.

1.5 Clock Interface

Signal Name Type

CLK_IN I 86 CLOCK INPUT: 25 MHz oscillator or crystal input (50 ppm).
CLK_OUT O 87 CLOCK OUTPUT: Second terminal for 25 MHz crystal. Must be left floating if

CLK_TO_MAC O 85 CLOCK TO MAC OUTPUT: This clock output can be used to drive the clock

PQFP

Pin #

Description

a clock oscillator is used.

input of a MAC or switch device. This output is avail able aft er power-up and is
active during all mode s except during hard ware or software reset . Note that the
clock frequency is s electabl e through CLK_MAC _FREQ between 25 MHz and
125 MHz.

To disable this clock outp ut the MAC_C LK_EN_ST RAP p in ha s to be ti ed l ow.

1.6 Device Configuration and LED Interface

(See section “3.7 PHY Address, Strapping Options and LEDs” on page 45 and section “5.9 LED/Strapping Option” on
page 67.)

Signal Name Type

NON_IEEE_STRAP I/O,

MAN_MDIX_STRAP /
TX_TCLK

S, PD

I/O,
S, PD

PQFP

Pin #

1 NON IEEE COMPLIANT MODE ENABLE: This mode allows interoperability

with certain non IEEE compliant 1000BASE-T transceivers.
‘1’ enables IEEE compliant operation and non-compliant operation

‘0’ enables IEEE compliant operation but inhibits non-compliant operation
Note: The status of this bit is reflected in bit 10 of register 0x10. Thi s pin also

sets the default for and can be overwritten by bit 9 of register 0x12.

6 MANUAL MDIX SETTING: This pin sets the default for manual MDI/MDIX

configuration.
‘1’ PHY is manually set to cross-over mode (MDIX)

‘0’ PHY is manually set to straight mode (MDI)
Note: The status of this bit is reflected in bit 8 of register 0x10. This pin also

sets the default for and can be overwritten by bit 14 of register 0x12.
TX_TCLK: TX_TCLK is enabled by setting bit 7 of register 0x12. It is used to

measure jitter in Test Modes 2 and 3 as described in IEEE 802.3ab specifica­tion. TX_TCLK should not be c onfused wit h the TX_CLK signal. See T able 12
on page 29 regarding Test Mode setting. This pin should be left floating if not
used.

Description

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1.0 Pin Description (Continued)

DP83865

Signal Name Type

ACTIVITY_LED /
SPEED0_STRAP

LINK10_LED /RLED/
SPEED1_STRAP

LINK100_LED /
DUPLEX_STRAP

LINK1000_LED /
AN_EN_STRAP

I/O,
S, PD

I/O,
S, PD

I/O,
S, PU

I/O,
S, PU

PQFP

Pin #

7 SPEED SELECT STRAP: These strap option pins have 2 different functions

depending on whether Auto-Negotiation is enabled or not.
Auto-Neg disabled:

Speed[1] Speed[0] Speed Enabled

11= Reserved
1 0 = 1000BASE-T
0 1 = 100BASE-TX
0 0 = 10BASE-T

Auto-Neg enabled (Advertised capability):

Speed[1] Speed[0] Speed Enabled

1 1 = 1000BASE-T, 10BASE-T
1 0 = 1000BASE-T
0 1 = 1000BASE-T, 100BASE-TX

0 0 = 1000BASE-T, 100BASE-TX, 10BASE-T
Note: The status of this bit is reflected in register 0x10 .12 .
ACTIVITY LED: The LED output indicates the occurrence of either idle error

or packet transfer.

8 SPEED SELECT STRAP: The stra p o pti on pi ns h ave 2 d ifferent functions de -

pending on whether Auto-Neg is enable d or not. See SPEED0_STRAP for de ­tails.

Note: The status of this bit is reflected in register 0x10 .13 .
10M GOOD LINK LED: In the standard 5-LED display mode, this LED out put

indicates that the PHY has established a good link at 10 Mbps.
RLED MODE: There are two reduced LED modes, the 3-in-1 and 4-in-1

modes. Each RLED mode is enabled in register 0x13.5 and 0x1A.0.

– 3-in-1: 10, 100, and 1000 Mbps good links are combined into one LED.
– 4-in-1: 3-in-1 and activity are combined.

Note: LED steady on ind icates good link an d flashing indic ates Tx/Rx activiti es.

9 DUPLEX MODE: This pin sets the default value for the duplex mode. ‘1’ en-

ables Full Duplex by default, ‘0’ enables Half Du plex only.
Note: The status of this bit is reflected in bit 14 of register 0x10.
100M SPEED AND GOOD LINK LED: The LED output ind icates that the PHY

has established a good link at 100 Mbps.
In 100BASE-T mode, the link is es tablis hed as a result of a n input rec eive am-

plitude compliant with TP-PMD specifications which will result in internal gen­eration of Signal Detect. LINK100_LED will assert after the internal Signal
Detect has remained asserted for a mi nimum of 50 0 µs . LINK100 _LED will de­assert immediately following the de-assertion of the internal Signal Detect.

10 AUTO-NEGOTIATION ENABLE: Input to initialize Auto-Negotiation Enable

bit (register 0 bit-12).
‘1’ enables Auto-Neg and ‘0’ disables Auto-Neg.
Note: The status of this bit is reflected in bit 15 of register 0x10. Thi s pin also

sets the default for and can be overwritten by bit 12 of register 0x00.
1000M SPEED AND GOOD LINK LED: The LED output indicates that the

PHY has established a good link at 1000 Mbps.
In 1000BASE-T mode, the link is established as a result of training, Auto-Ne-

gotiation completed, val id 1000BASE-T link esta blished and reliab le reception
of signals transmitted from a remote PHY is received.

Description

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1.0 Pin Description (Continued)

DP83865

Signal Name Type

DUPLEX_LED /
PHYADDR0_STRAP

PHYADDR1_STRAP
PHYADDR2_STRAP
PHYADDR3_STRAP
PHYADDR4_STRAP

MULTI_EN_STRAP /
TX_TRIGGER

MDIX_EN_STRAP I/O,

MAC_CLK_EN_STRAP
/ TX_SYN_CLK

VDD_SEL_STRAP I/O, S 34 IO_VDD SELECT: This pin selects between 2.5V or 3.3V for I/O VDD .

I/O,
S, PU

PD
PD
PD

PD
I/O,

S, PD

S, PU

PQFP

Pin #

13

PHY ADDRESS [4:0]: The DP83865 provides five PHY ad dress-sen sing pins
for multiple PHY application s. The setting on the se five pins provid es the base
address of the PHY.

14

The five PHYAD[4:0] bits are registered as inputs at reset with PHYADDR4 be-

17

ing the MSB of the 5-bit PHY address.

18

Note: The status of these bit is reflected in bits 4:0 of register 0x12.
DUPLEX STATUS: The LED is lit when the PHY is in Full Duplex operation

95

after the link is established.

94 MULTIPLE NODE ENABLE: This pin d etermines if the PHY advertises Master

(multiple nodes) or Slave (single node) priority during 1000BASE-T Auto-Ne­gotiation.

‘1’ Selects multiple node priority (switch or hub)
‘0’ Selects single node priority (NIC)

Note: The status of this bit is reflected in bit 5 of register 0x10.
TX_TRIGGER: This output can be enabled during the IEEE 1000BASE-T test -

modes. This signal is not required by IEEE to perform the tests, but will help to
take measurements. TX_TRIGGER is only available in test mod es 1 and 4 and
provides a trigger to allow for viewing test waveforms on an oscilloscope.

89 AUTO MDIX ENABLE: This pin controls the automat ic pair swap (Auto-MDIX)

of the MDI/MDIX interface.
‘1’ enables pair swap mode

‘0’ disables the Auto-MDIX and defaults the part into the mode preset by the
MAN_MDIX_STRAP pin.

Note: The status of this bit is reflected in bit 6 of register 0x10. This pin also
sets the default for and can be overwritten by bit 15 of register 0x12.

I, S, PU88 CLOCK TO MAC ENABLE:

‘1’ CLK_TO_MAC clock output enabled
‘0’ CLK_TO_MAC disabled

Note: This status of this pin is reflected in bit 7 of register 0x10.
TX_SYN_CLK: This output can be enabl ed during the IEEE 1000BASE-T test-

modes. This signal is not required by IEEE to perform the tests, but will help to
take measurements. TX_SYN_CLK is only available in test modes 1 and 4.

TX_SYN_CLK = TX_TCLK / 4 in test mode 1
TX_SYN_CLK = TX_TCLK / 6 in test mode 4

‘1’ selects 3.3V mode
‘0’ selects 2.5V mode

This pin must either be connec ted directly to ground or directly to a supp ly volt­age (2.5V to 3.3V).

Description

1.7 Reset

Signal Name Type

RESET

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PQFP

Pin #

I33RESET: The ac tive low RESET input allo ws for hard-reset, soft-res et, and TRI-

STATE output reset combinations. The RESET input must be low for a mini­mum of 150 µs.

Description

1.0 Pin Description (Continued)

1.8 Power and Ground Pins

(See section “5.3 Power Supply Decoupling” on page64.)

Signal Name PQFP Pin # Description

IO_VDD 4, 15, 21, 29, 37, 42, 53, 58, 69,

77, 83, 90

CORE_VDD 11, 19, 25, 35, 48, 63, 73, 92 1.8V Digital Core Supply
2V5_AVDD1 101 2.5V Analog Supply
2V5_AVDD2 96 2.5V Analog Supply
1V8_AVDD1 103, 105, 111, 117, 123 1.8V Analog Supply
1V8_AVDD2 98 1.8V Analog Supply - See section “5.4 Sensitive Supply

1V8_AVDD3 100 1.8V Analog Supply - See section “5.4 Sensitive Supply

VSS 5, 12, 16, 20, 22, 26, 30, 36, 38,

43, 49, 54, 59, 64, 70, 74, 78, 82,
91, 93, 97, 99, 104, 106, 107,
110, 112, 113, 116, 118, 119,
122, 124, 125, 128

2.5V or 3.3V I/O Supp ly for “MAC Interfaces”, “Management
Interface”, “JTAG Inte rface”, “Clo ck Interf ace”, “Devi ce Con­figuration and LED Interface” and “Reset”.

Pins” on page 64 for low pass filter recommendation.

Pins” on page 64 for low pass filter recommendation.
Ground

DP83865

1.9 Special Connect Pins

Signal Name TYPE

BG_REF I 102 Internal Reference Bias: See s ection “5.4 Sensitive Supply Pins” on page64

RESERVED 2, 23, 84These pins are reserved and must be left floating.

PQFP

Pin #

Description

for information on how to terminate this pin.

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1.0 Pin Description (Continued)

1.10 Pin Assignments in the Pin Number Order

DP83865

Pin # Data Sheet Pin Name Type Connection / Comment

1 NON_IEEE_STRAP Strap Non IEEE Compliant Mod e Enable: Use a 2kΩ

2 RESERVED Reserved Reserved: Leave floating.
3 INTERRUPT

4IO_VDD PowerI/O VDD: (Digital) Connect to 2.5V or 3.3V. The

5 VSS Ground Ground: Connect to common ground plane.
6 TX_TCLK Output Transmit Test Clock: See sect ion “1.9 Special

7 ACTIVITY_LED / SPEED0_STRAP Strap /

8 LINK10_LED / RLED/SPEED1_STRAP Strap /

9 LINK100_LED / DUPLEX_STRAP Strap /

10 LINK1000_LED / AN_EN_STRAP Strap /

11 CORE_VDD Power Core VDD: (Digital) Connect to 1.8V.
12 VSS Ground Ground: Connect to common ground plane.
13 DUPLEX_LED / PHYADDR0_STRAP Strap /

14 PHYADDR1_STRAP Strap PHY Address 1: See section

15 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V . The

16 VSS Ground Ground: Connect to common ground plane.
17 PHYADDR2_STRAP Strap PHY Address 2: See section

18 PHYADDR3_STRAP Strap PHY Address 3: See section

19 CORE_VDD Power Core VDD: (Digital) Connect to 1.8V.
20 VSS Gound Ground: Connect to common ground plane.
21 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V . The

22 VSS Ground Ground: Connect to common ground plane.

Table 1.

pull-up resistor to enable. Leav e open to di sable.

Output INTERRUPT: Connect to MAC or manage men t

Output

Output

Output

Output

Output

IC. This is a tri-sta te pin and require s an external
2kΩ pull-up resistor if the pin is used.

VDD_SEL pin must be tied accordingly.

Connect Pins” on page 11.
Activity LED / SPEED0 Select: See section

“5.9 LED/Strapping Option” on page67 on how
to connect this pin for speed selection and
ACTIVITY_LED function.

10M Link LED / RLED / SPEED1: See section
“5.9 LED/Strapping Option” on page67 on how
to connect this pin for speed selection and
LINK10_LED function.

100M Link LED / Duplex Select: See section
“5.9 LED/Strapping Option” on page67 on how
to connect this pin for Duplex selection and
100_LED function.

1000M Link LED / Auto-Neg. Select: See sec­tion “5.9 LED/Strapping Option” on page 67 on
how to connect this pin for Auto-negotia tion con­figuration and 1000_LED function.

Duplex LED / PHY Address 0: See section
“5.9 LED/Strapping Option” on page67 on how
to connect this pin for PHY address configura­tion and DUPLEX_LED function.

“5.9 LED/Strapping Option” on page67 on how
to connect this pin.

VDD_SEL pin must be tied accordingly.

“5.9 LED/Strapping Option” on page67 on how
to connect this pin

“5.9 LED/Strapping Option” on page67 on how
to connect this pin

VDD_SEL pin must be tied accordingly.

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1.0 Pin Description (Continued)

Table 1.

Pin # Data Sheet Pin Name Type Connection / Comment

23 RESERVED Reserved Reserved: Leave floating.
24 TCK Input JTA G Test Clock: This pin should be left float-

ing if not used.
25 CORE_VDD Power Core VDD: (Digital) Connect to 1.8V.
26 VSS Ground Ground: Connect to common ground plane.
27 TMS Input JTAG Test Mode Select: This pin should be le ft

28 TDO Output JTAG Test Data Output: This p in shoul d be left

29 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V . The

30 VSS Ground Ground: Connect to common ground plane.
31 TDI Input JTAG Test Data Input: This pin should be left

32 TRST

33 RESET
34 VDD_SEL_STRAP Strap I/O VDD Select: Pull high to select 3.3V or low

35 CORE_VDD Power Core VDD: (Digital) Connect to 1.8V.
36 VSS Ground Ground: Connect to common ground plane.
37 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V . The

38 VSS Ground Ground: Connect to common ground plane.
39 COL Output Collision: Connect to MAC chip through a single

40 CRS/RGMII_SEL0 Output Carrier Sense: Connect to MAC chip through a

41 RX_ER/RXDV_ER Output Receive Error: Connect to MAC c hi p th roug h a

42 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V . The

43 VSS Ground Ground: Connect to common ground plane.
44 RX_DV/RCK Output Receive Data Valid: Connect to MAC chip

Input JTAG Test Reset: This pin should be pulled

Input Reset: Connect to board reset signal.

floating if not used.

floating if not used.

VDD_SEL pin must be tied accordingly.

floating if not used.

down through a 2kΩ resistor if not used .

to select 2.5V. T he pin must be connected di rect-

ly to power or ground (no pull-up/d own resistor!).

VDD_SEL pin must be tied accordingly.

50 Ω impedance trace. Th is output i s capable of

driving 35 pF load and is not intended to drive

connectors, cables, backplanes or multiple trac-

es. This applies if the part is in 100 Mbps mode

or 1000 Mbps mode.

single 50Ω impedance trace. This output is ca-

pable of driving 35 pf load and is n ot inten ded to

drive connectors, ca bles, backplan es or multiple

traces. This applies if the part is in 100 Mbps

mode or 1000 Mbps mode.

single 50 Ω impedance trace. This output is ca-

pable of driving 35 pf load and is n ot inten ded to

drive connectors, ca bles, backplan es or multiple

traces. This applies if the part is in 100 Mbps

mode or 1000 Mbps mode.

VDD_SEL pin must be tied accordingly.

through a sing le 50 Ω impe dance trace. This out -

put is capable of driving 35 pf load and is not in-

tended to drive connectors, cables, backplanes

or multiple traces. This applies if the part is in

100 Mbps mode or 1000 Mbps mode.

DP83865

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1.0 Pin Description (Continued)

DP83865

Table 1.

Pin # Data Sheet Pin Name Type Connection / Comment

45 RXD7 Output Receive Data 7: Connect to MAC chip through

a single 50 Ω impedance trace. This output is ca -

pable of driving 35 pf load and is n ot inten ded to

drive connectors, ca bles, backplan es or multiple

traces. This applies if the part is in 100 Mbps

mode or 1000 Mbps mode.
46 RXD6 Output Receive Data 6: Connect to MAC chip through

a single 50 Ω impedance trace. This output is ca -

pable of driving 35 pf load and is n ot inten ded to

drive connectors, ca bles, backplan es or multiple

traces. This applies if the part is in 100 Mbps

mode or 1000 Mbps mode.
47 RXD5 Output Receive Data 5: Connect to MAC chip through

a single 50 Ω impedance trace. This output is ca -

pable of driving 35 pf load and is n ot inten ded to

drive connectors, ca bles, backplan es or multiple

traces. This applies if the part is in 100 Mbps

mode or 1000 Mbps mode.
48 CORE_VDD Power Core VDD: (Digital) Connect to 1.8V.
49 VSS Ground Ground: Connect to common ground plane.
50 RXD4 Output Receive Data 4: Connect to MAC chip through

a single 50 Ω impedance trace. This output is ca -

pable of driving 35 pf load and is n ot inten ded to

drive connectors, ca bles, backplan es or multiple

traces. This applies if the part is in 100 Mbps

mode or 1000 Mbps mode.
51 RXD3/RX3 Output Receive Data 3: Connect to MAC chip through

a single 50 Ω impedance trace. This output is ca -

pable of driving 35 pf load and is n ot inten ded to

drive connectors, ca bles, backplan es or multiple

traces. This applies if the part is in 100 Mbps

mode or 1000 Mbps mode.
52 RXD2/RX2 Output Receive Data 2: Connect to MAC chip through

a single 50 Ω impedance trace. This output is ca -

pable of driving 35 pf load and is n ot inten ded to

drive connectors, ca bles, backplan es or multiple

traces. This applies if the part is in 100 Mbps

mode or 1000 Mbps mode.
53 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V . The

VDD_SEL pin must be tied accordingly.
54 VSS Ground Ground: Connect to common ground plane.
55 RXD1/RX1 Output Receive Data 1: Connect to MAC chip through

a single 50 Ω impedance trace. This output is ca -

pable of driving 35 pf load and is n ot inten ded to

drive connectors, ca bles, backplan es or multiple

traces. This applies if the part is in 100 Mbps

mode or 1000 Mbps mode.
56 RXD0/RX0 Output Receive Data 0: Connect to MAC chip through

a single 50 Ω impedance trace. This output is ca -

pable of driving 35 pf load and is n ot inten ded to

drive connectors, ca bles, backplan es or multiple

traces. This applies if the part is in 100 Mbps

mode or 1000 Mbps mode.

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1.0 Pin Description (Continued)

Table 1.

Pin # Data Sheet Pin Name Type Connection / Comment

57 RX_CLK Output Receive Clock/ Receive Byte Clock 1: Con-

nect to MAC chip through a single 50 Ω imped-

ance trace. This output is capable of driving 35

pf load and is not intended to drive connectors,

cables, backplanes or multiple traces. This ap-

plies if the part is in 100 Mbps mode or 1000

Mbps mode.
58 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V . The

VDD_SEL pin must be tied accordingly.
59 VSS Ground Ground: Connect to common ground plane.
60 TX_CLK/RGMII_SEL1 Output Transmit Clock: Connect to MAC chip through

a single 50 Ω impedance trace. This input has a

typical input capacitance of 6 pF.
61 TX_ER Input Transmit Error: Connect to MAC ch ip through a

single 50 Ω impedance trace. This input has a

typical input capacitance of 6 pF.
62 TX_EN/TXEN_ER Input Transmit Enable: Connect to MAC chip through

a single 50 Ω impedance trace. This input has a

typical input capacitance of 6 pF.
63 CORE_VDD Power Core VDD: (Digital) Connect to 1.8V.
64 VSS Ground Ground: Connect to common ground plane.
65 TXD7 Input Transmit Data 7: Connect to MAC ch ip th roug h

a single 50 Ω impedance trace. This input has a

typical input capacitance of 6 pF.
66 TXD6 Input Transmit Data 6: Connect to MAC ch ip th roug h

a single 50 Ω impedance trace. This input has a

typical input capacitance of 6 pF
67 TXD5 Input Transmit Data 5: Connect to MAC ch ip th roug h

a single 50 Ω impedance trace. This input has a

typical input capacitance of 6 pF
68 TXD4 Input Transmit Data 4: Connect to MAC ch ip th roug h

a single 50 Ω impedance trace. This input has a

typical input capacitance of 6 pF
69 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V . The

VDD_SEL pin must be tied accordingly.
70 VSS Ground Ground: Connect to common ground plane.
71 TXD3/TX3 Input Transmit Data 3: Connect to MAC chip throug h

a single 50 Ω impedance trace. This input has a

typical input capacitance of 6 pF
72 TXD2/TX2 Input Transmit Data 2: Connect to MAC chip throug h

a single 50 Ω impedance trace. This input has a

typical input capacitance of 6 pF
73 CORE_VDD Power Core VDD: (Digital) Connect to 1.8V.
74 VSS Ground Ground: Connect to common ground plane.
75 TXD1/TX1 Input Transmit Data 1: Connect to MAC chip throug h

a single 50 Ω impedance trace. This input has a

typical input capacitance of 6 pF
76 TXD0/TX0 Input Transmit Data 0: Connect to MAC chip throug h

a single 50 Ω impedance trace. This input has a

typical input capacitance of 6 pF
77 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V . The

VDD_SEL pin must be tied accordingly.
78 VSS Ground Ground: Connect to common ground plane.

DP83865

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1.0 Pin Description (Continued)

DP83865

Table 1.

Pin # Data Sheet Pin Name Type Connection / Comment

79 GTX_CLK/TCK Input GMII Transmit Clock: Connect to MAC chip

through a single 50 Ω impedance trace. This in-

put has a typical input capacitance of 6 pF
80 MDIO Input /

Output

81 MDC Input Management Data Cl ock: Connect to MAC or

82 VSS Ground Ground: Connect to common ground plane.
83 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V . The

84 RESERVED Reserved Reserved: Leave floating.
85 CLK_TO_MAC Output Clock to MAC: Connect to the reference clock

86 CLK_IN Input Clock Input: Connect to external 25MHz refer-

87 CLK_OUT Input Clock Output: Connect to the second terminal

88 MAC_CLK_EN_STRAP Strap Clock to MAC Enable: Use a 2kΩ pull-down re-

89 MDIX_EN_STRAP Strap Automatic MDIX Enable: Use a 2kΩ pu ll-down

90 IO_VDD Power I/O VDD: (Digital) Connect to 2.5V or 3.3V . The

91 VSS Ground Ground: Connect to common ground plane.
92 CORE_VDD Power Core VDD: (Digital) Connect to 1.8V.
93 VSS Ground Ground: Connect to common ground plane.
94 MULTI_EN_STRAP Strap Multiple Node Enable: Use a 2 kΩ pull-up resis-

95 PHYADDR4_STRAP Strap PHY Address 4: See section

96 AFE_VDD Power AFE VDD: (Analog) Connect to 2.5V.
97 VSS Ground Ground: Connect to common ground plane.
98 PGM_VDD Power PGM VDD: Connect to 1.8V through a low pass

99 VSS Ground Ground: Connect to common ground plane.

100 1V8_AVDD3 Power Analog Supply: Connect to 1.8V throu gh a low

101 BG_VDD Power BG VDD: (Analog) Connect to 2.5V.
102 BG_REF Input BG Reference: See section “5.4 Sensitive Sup-

103 RX_VDD Power Receive VDD: (Analog) Connect to 1.8V.
104 VSS Ground Ground: Connect to common ground plane.
105 RX_VDD Power Receive VDD: (Analog) Connect to 1.8V.
106 VSS Ground Ground: Connect to common ground plane.

Management Data I/O: This pin requires a 2kΩ

parallel termination resistor (pull-up to VDD).

controller using a 50 Ω impedance trace.

VDD_SEL pin must be tied accordingly.

input of a GMAC. Use pin

MAC_CLK_EN_STRAP to disable this function.

ence clock source. If a crystal is used connect to

first terminal of crystal.

of a crystal. Leave floating if an external clock

source is used.

sistor to disable. Leave open to enable.

resistor to disable. Leave open to enable.

VDD_SEL pin must be tied accordingly.

tor to enable. Leave open to disable.

“5.9 LED/Strapping Option” on page67 on how

to connect this pin.

filter. See section “5 .4 Sensitive Supply Pins” on

page 64 for details.

pass filter. See section “5.4 Sensitive Supply

Pins” on page 64 for details.

ply Pins” on page 64 on how to connect this pin.

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1.0 Pin Description (Continued)

Table 1.

Pin # Data Sheet Pin Name Type Connection / Comment

107 VSS Ground Ground: Connect to common ground plane.
108 MDIA_P Input /

Output

109 MDIA_N Input /

Output
110 VSS Ground Ground: Connect to common ground plane.
111 RX_VDD Power Receive VDD: (Analog) Connect to 1.8 Volt.
112 VSS Ground Ground: Connect to common ground plane.
113 VSS Ground Ground: Connect to common ground plane.
114 MDIB_P Input /

Output
115 MDIB_N Input /

Output
116 VSS Ground Ground: Connect to common ground plane.
117 RX_VDD Power Receive VDD: (Analog) Connect to 1.8V.
118 VSS Ground Ground: Connect to common ground plane.
119 VSS Ground Ground: Connect to common ground plane.
120 MDIC_P Input /

Output
121 MDIC_N Input /

Output
122 VSS Ground Ground: Connect to common ground plane.
123 RX_VDD Power Receive VDD: (Analog) Connect to 1.8V.
124 VSS Ground Ground: Connect to common ground plane.
125 VSS Ground Ground: Connect to common ground plane.
126 MDID_P Input /

Output
127 MDID_N Input /

Output
128 VSS Ground Ground: Connect to common ground plane.

MDI Channel A Positive: Connect to TD+ of
channel A of the magnetics.

MDI Channel A Negative: Connect to TD- of
channel A of the magnetics.

MDI Channel B Positive: Connect to TD+ of
channel B of the magnetics.

MDI Channel B Negative: Connect to TD- of
channel B of the magnetics.

MDI Channel C Positive: Connect to TD+ of
channel C of the magnetics.

MDI Channel C Negative: Connect to TD- of
channel C of the magnetics.

MDI Channel D Positive: Connect to TD+ of
channel D of the magnetics.

MDI Channel D Negative: Connect to TD- of
channel D of the magnetics.

DP83865

17 www.national.com

2.0 Register Block

2.1 Register Definitions

DP83865

Register maps and addres s def ini t io ns are giv en in the followi ng table:

Table 2. Register Block - DP83865 Register Map

Offset

Hex Decimal

0x00 0 RW BMC R Basic Mode Control Register
0x01 1 RO BMSR Basic Mode Status Register
0x02 2 RO PHYIDR1 PHY Identifier Register #1
0x03 3 RO PHYIDR2 PHY Identifier Register #2
0x04 4 RW ANAR Auto-Negotiation Advertisemen t Reg ist er
0x05 5 RW ANLPAR Auto-Negotiation Link Partner Ability Register
0x06 6 RW ANER Auto-Negotiation Expansion Regis ter
0x07 7 RW ANNPTR Auto-Negotiation Next Page TX
0x08 8 RW ANNPRR Auto-Negotiation Next Page RX
0x09 9 RW 1KTCR 1000BASE-T Control Register

0x0A 10 RO 1KSTSR 1000BASE-T Status Register

0x0B-0x0E 11-14 RO Reserved Reserved

0x0F 15 RO 1KSCR 1000BASE-T Extended Status Register
0x10 16 RO STRAP_REG Strap Options Register
0x11 17 RO LINK_AN Link and Auto-Negotiation Status Register
0x12 18 RW AUX_CTRL Auxiliary Control Register
0x13 1 9 RW LED_CTRL LED Control Regi ster
0x14 20 RO INT_STATUS Interrupt Status Register
0x15 21 RW INT_MASK Interrupt Mask Register
0x16 22 RO EXP_MEM_CTL Expanded Memory Access Control
0x17 23 RW INT_CLEAR Interrupt Clear Register
0x18 24 RW BIST_CNT BIST Counter Register
0x19 25 RW BIST_CFG1 BIST Configuration Register #1

0x1A 26 RW BIST_CFG2 BIST Configuration Register #2

0x1B-0x1C 27-28 RO Reserved Reserved

0x1D 29 RW EXP_MEM_DATA Expanded Memory Data
0x1E 30 RW EXP_MEM_ADDR Expanded Memory Address

0x1F 31 RW PHY_SUP PHY Support Register

Access Tag Description

www.national.com 18

2.0 Register Block (Continued)

0

Reserved

0

Reserved

0

Reserved

0

1

OUI[18]

Extended

Capability

0, LH

Detect

Jabber

OUI[17]

0, LL

OUI[16]

Link Status

0

MDL_REV[0]

0

1

MDL_REV[1]

0

0

MDL_REV[2]

DP83865

1

PSB[0]

PSB[1]

PSB[2]

0

PSB[0]

LP_AN Able

0

0

PSB[1]

Page _RX

0

0

PSB[2]

NP_Able

0

0

NP_M[0]

0, LH

NP_M[1]

1

NP_M[2]

0

0

NP_M[0]

Reserved

0

0

NP_M[1]

Reserved

0

0

NP_M[2]

Reserved

Count[0]

Idle Error

0

Count[1]

Idle Error

0

Count[2]

Idle Error

0

0

0

0

0

0

0

Reserved

0

Reserved

0

Reserved

0

Reserved

Reserved

Reserved

Reserved

0

0

0

0

0

Reserved

0

Reserved

Reserved

Reserved

Reserved

Reserved

0

0

Reserved

Reserved

0

Reserved

0

Reserved

0

Reserved

Strap[1]

Speed[1]

Selection

0

Collision Test

Strap[1]

Duplex Mode

0, SC

Restart

Auto-Neg

0

Isolate

1

Ability

Auto-Neg

0, LH

Remote Fault

0

Auto-Neg

Complete

1

Preamble

Suppression

Reserved

1

Ext’d Status

1000BASE-T

0

Half-Duplex

100BASE-T2

0

Full-Duplex

100BASE-T2

0

0

1

OUI[15]

0

OUI[14]

0

OUI[13]

0

OUI[12]

0

0

OUI[11]

0

OUI[10]

0

OUI[9]

0

OUI[8]

PSB[3]

MDL_REV[3]

1

PSB[4]

VMDR_MDL[0]

1

10BASE-T

VMDR_MDL[1]

VMDR_MDL[2]

VMDR_MDL[3]

VMDR_MDL[4]

VMDR_MDL[5]

OUI[24]

Half-Duplex

1

10BASE-T

Full-Duplex

0

Half-Duplex

100BASE-TX

0

Full-Duplex

100BASE-TX

0

100BASE-T4

1

PAUSE

0

PSB[3]

LP_NP Able

0

0

PDF

PSB[4]

0

STRAP[1]

STRAP[1]

STRAP[1]

STRAP[1]

0

0

Reserved

10BASE-T

Half-Duplex

0

Reserved

10BASE-T

Full-Duplex

0

Reserved

Half-Duplex

100BASE-TX

0

Reserved

Full-Duplex

100BASE-TX

0

Reserved

100BASE-T4

0

PAUSE

Reserved

0

0

NP_M[3]

0, LH

NP_M[4]

0

NP_M[5]

0

NP_M[6]

0

NP_M[7]

0

NP_M[8]

0

NP_M[9]

0

NP_M[10]

0

0

NP_M[3]

Reserved

0

0

NP_M[4]

Reserved

0

0

Reservd

NP_M[5]

0

0

NP_M[6]

Reserved

0

0

NP_M[7]

Reserved

0

0

NP_M[8]

1000BASE-T

0

0

NP_M[9]

1000BASE-T

0

0

NP_M[10]

Repeater DTE

Count[3]

Idle Error

0

Count[4]

Idle Error

0

Count[5]

Idle Error

0

Count[6]

Idle Error

0

Count[7]

Idle Error

Reserved

STRAP[1]

Half-Duplex

Reserved

STRAP[1]

Full-Duplex

LP

STRAP[0]

1000BASE-T

0

0

0

0

0

0

0

0

0

0

0

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

Reserved

Value

Bit Name

Read Only

Default Value

Read/Writable

0

Reserved

Reserved

Reserved

Reserved

0

0

0

0

0

0

0

0

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

0

Reserved

Reserved

0

0

Reserved

Reserved

0

0

Reserved

Reserved

0

0

Reserved

Reserved

0

0

Reserved

Reserved

0

0

Reserved

Reserved

0

0

Reserved

Half-Duplex

Reserved

2.2 Register Map

Register Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0

Power Down

Enable

Strap[1]

Auto-Neg

Strap[0]

Selection

Speed [0]

0

Loopback

0, SC

PHY Reset

Register 0x00

Basic Mode Control Register

0

0

Auto-Neg Advertisement

0

0

0

0

Register (ANAR)

ASY_PAUSE

Reserved

Remote Fault

ACK

Next Page

Register 0x05

Auto-Neg Link Partner

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

Ability Register (ANLPAR)

Register 0x06

Auto-Neg Expansion Register

1

0

1

OUI[7]

OUI[6]

OUI[5]

OUI[4]

OUI[3]

Register 0x02

PHY Identifier Register #1

OUI[23]

ASY_PAUSE

1

0

OUI[22]

Reserved

0

1

OUI[21]

Remote Fault

1

0

OUI[20]

Reserved

0

0

OUI[19]

Next Page

(PHYIDR1)

Register 0x03

PHY Identifier Register #2

(PHYIDR2)

Register 0x04

10BASE-T

Half-Duplex

1

10BASE-T

Full-Duplex

1

Half-Duplex

100BASE-X

1

Full-Duplex

100BASE-X

0

100BASE-T4

(BMCR)

Register 0x01

Basic Mode Status Register

(BMSR)

0

0

TOG_TX

TOG_RX

0

0

ACK2

ACK2

1

0

Message Page

Message Page

0

0

ACK

ACK

1

0

Next Page

Next Page

(ANER)

Register 0x07

Auto-Neg NP TX Register

(ANNPTR)

Register 0x08

0

LP

Master/Slave

0

Master/Slave

0

Test Mode[0]

0

Test Mode[1]

0

Test Mode[2]

Auto-Neg NP RX Register

(ANNPRR)

Register 0x09

1000BASE-T

Config. Value

0

Remote Re-

ceiver Status

Config. Enable

0

Status

Local Receiver

0

Master/Slave-

Config. Resol.

0

Master/Slave

Manual Config.

Register (1KTCR)

1000BASE-T Control

Register 0x0A (10’d)

Full-Duplex

Fault

1000BASE-T Status Register

0

0

0

0

Reserved

0

0

0

0

0

Reserved

1

Half-Duplex

1000BASE-T

1

Full-Duplex

1000BASE-T

0

Half-Duplex

1000BASE-X

0

Full-Duplex

1000BASE-X

Register 0x0F (15’d)

1000BASE-T Extended

Key: Bi t N a me

Status Register (1KSCR)

0

Reserved

Reserved

Reserved

Reserved

0

0

0

Reserved

Reserved

0

0

Reserved

Reserved

0

0

Reserved

Reserved

0

Reserved

0, LH, SC

(1KSTSR)

Reserved

Register 0x0B (11’d)

Reserved

Register 0x0C (12’d)

0

Reserved

Reserved

0

0

Reserved

Reserved

0

0

Reserved

Reserved

0

0

Reserved

Reserved

Reserved

Register 0x0D (13’d)

Reserved

Register 0x0E (14’d)

19 www.national.com

2.0 Register Block (Continued)

DP83865

PHYADDR[0]

PHYADDR[1]

PHYADDR[2]

PHYADDR[3]

PHYADDR[4]

Multi Enable

Enable

Auto MDIX

Enable

MAC Clock

STRAP[1]

STRAP[0]

STRAP[0]

STRAP[0]

STRAP[0]

STRAP[0]

STRAP[1]

STRAP[1]

0

Master/Slave

Config. Status

0

Duplex Status

0

Link Status

0

Speed

Status[0]

0

Speed

Status[1]

0

Status

NC Mode

0

back

Status

(Deep) Loop-

0

Reserved

back Status

(Shallow Loop-

Jabber Disable

0

Reserved

0

Reserved

0

Reserved

0

X_Mac Enable

0

back Enable

Shallow Loop-

0

TX_TRIG

/SYNC Enable

0

Enable

TX_TCLK

0

0

0

0

0

0

0

0

0

10M LED

ACT/LNK-LNK

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

0

0

0

Reserved

0

Reserved

0

Reserved

0

Change Int.

Remote Fault

0

Auto-Neg.

Complete Int.

0

Next Page

Received Int.

0

Int.

Jabber Change

0

No Link Int.

Reserved

Reserved

Reserved

Mask Int.

Mask Int.

Mask Int.

Mask Int.

Mask Int.

AN Fallback

on Idle Error

0

AN Fallback

on CRC Error

0

AN Fallback

on Gigabit Link

0

on Idle Error

Modulate LED

0

on CRC Error

Modulate LED

0

10M LED

RLED enable

0

Duplex LED[0]

0

Duplex LED[1]

0

XMode[0]

Reserved

0

0

XMode[1]

Reserved

0

0

Reserved

Reserved

0

0

Clear Int.

Reserved

0

0

Clear Int.

Reserved

0

0

Clear Int.

Reserved

0

0

0

Clear Int.

Reserved

0

Clear Int.

Broadcast En.

0

0

Counter Bit[0]

0

Counter Bit[1]

0

Counter B i t[ 2 ]

0, SC

Counter Bit[3]

0, SC

Counter Bit[4]

0, SC

Counter Bi t[5]

0, SC

Counter Bit[6]

0, SC

Counter Bit[7]

Packet[0]

Transmit BIST

0

Packet[1]

Transmit BIST

0

Packet[2]

Transmit BIST

0

Packet[3]

Transmit BIST

0

Packet[4]

Transmit BIST

0

Packet[5]

Transmit BIST

0

Packet[6]

Transmit BIST

0

Packet[7]

Transmit BIST

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

0

0

0

1

PHY

Exp Mem Data

Exp Mem Addr

1

0

Exp Mem Data

Exp Mem Addr

2

0

Exp Mem Data

Exp Mem Addr

3

0

Exp Mem Data

Exp Mem Addr

4

0

Exp Mem Data

Exp Mem Addr

5

0

Exp Mem Data

Exp Mem Addr

6

0

Exp Mem Data

Exp Mem Addr

7

0

Exp Mem Data

Exp Mem Addr

ADDRESS[0]

1

0

0

PHY

ADDRESS[1]

2

0

0

PHY

ADDRESS[2]

3

0

0

PHY

ADDRESS[3]

4

0

0

PHY

ADDRESS[4]

5

0

0

Reserved

6

7

0

0

Reserved

0

Reserved

Reserved

0

Reserved

STRAP[0]

(REF_SEL)

Reserved

STRAP[0]

(REF_SEL)

NC Mode

STRAP[0]

Reserved

STRAP[0]

(REF_SEL)

Speed[0]

STRAP[0]

Speed[1]

STRAP[0]

Enable

STRAP[1]

Full Duplex

STRAP[1]

AN Enable

Reserved

In Progress)

(Power-On Init

0

FIFO Error

0

MDIX Status

Status)

Reserved

(Power Down

0

TP_POL[0]

0

TP_POL[1]

0

TP_POL[2]

0

TP_POL[3]

0

0

0

Status Enable

RGMII_inband

Enable

NC Mode

STRAP[0]

Reserved

Sig. Enable)

(RGMII Inband

Reserved

Sig. Enable)

(RGMII Inband

STRAP[0]

RGMII_EN[0]

STRAP[0]

RGMII_EN[1]

Mode

STRAP[0]

Manual MDIX

Enable

STRAP[1]

Auto MDIX

0

Link LED[0]

No HCD Int.

1000BASE-T

0

Fail Int.

Link LED[1]

1000BASE-T

Master/Slave

0

0

Fault Int.

Link LED[0]

100BASE-TX

PDF Detection

0

0

Polarity

Change Int.

Link LED[1]

100BASE-TX

0

10BASE-T

10BASE-T

Act. LED[0]

Act. LED[1]

Int.

Link LED[0]

MDIX Change

0

Duplex

Link LED[1]

Change Int.

0

Int.

Link Change

0

Int.

Speed Change

0

0

Mask Int.

0

0

Mask Int.

0

0

Mask Int.

0

0

Mask Int.

0

0

Mask Int.

0

0

Mask Int.

0

0

Mask Int.

0

0

Mask Int.

able)

Reserved

(Broadcast En-

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0, SC

Global Reset

0

Clear Int.

Clear Int.

Clear Int.

Clear Int.

Clear Int.

Clear Int.

Clear Int.

Clear Int.

0

0

0

0, SC

0, SC

0, SC

0, SC

0, SC

0, SC

0, SC

0, SC

Reserved

Counter Bi t[8]

0

Counter Bit[9]

0

Counter B i t[ 1 0 ]

0

Counter Bit[11]

0

Counter Bit[12]

0

Counter Bi t[13]

0

Counter Bit[14]

0

Counter Bit[15]

Reserved

0

Reserved

Reserved

0

Reserved

Packet Type

Transmit BIST

0

Packet

Enable

Transmit BIST

Transmit BIST

0

IFG

Packet

Transmit BIST

Transmit BIST

0

Packet

Transmit BIST

Packet Length

Transmit BIST

0

Clear

Select

BIST Counter

BIST Counter

0

Type

Enable

BIST Counter

Receive BIST

0

Reserved

0

0

Reserved

0

0

Reserved

0

0

Count[0]

Reserved

0

0

Count[1]

Reserved

0

0

Count[2]

Reserved

0

0

Reserved

0

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

0

Reserved

8

0

8

Exp Mem Data

Exp Mem Addr

9

0

9

Exp Mem Data

Exp Mem Addr

0

10

10

Exp Mem Data

Exp Mem Addr

0

11

11

Exp Mem Data

Exp Mem Addr

0

12

12

Exp Mem Data

Exp Mem Addr

0

13

13

Exp Mem Data

Exp Mem Addr

0

14

14

Exp Mem Data

Exp Mem Addr

0

15

15

Exp Mem Data

Exp Mem Addr

0

0

Reserved

BrdCst_AD[0]

0

0

Reserved

BrdCst_AD[1]

0

0

Reserved

BrdCst_AD[2]

0

0

Reserved

BrdCst_AD[3]

0

0

Reserved

BrdCst_AD[4]

0

0

Reserved

0

0

Reserved

0

0

Reserved

Value

Bit Name

Read Only

Default Value

Read/Writable

Key: Bi t N a me

Register Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Register 0x10 (16’d)

Strap Option Register

Status Register (LINK_AN)

(STRAP_REG)

Register 0x11 (17’d)

Link and Auto-Negotiation

Register 0x12 (18’d)

Auxiliary Control Register

(AUX_CTRL)

Register 0x13 (19’d)

LED Control Register

(LED_CTRL)

Register 0x14 (20’d)

Interrupt Status Register

(INT_STATUS)

Register 0x15 (21’d)

Interrupt Mask Register

(INT_MASK)

Register 0x16 (22’d)

Exp Memory Access Control

(EXP_MEM_CTL)

Register 0x17 (23’d)

Interrupt Clear Register

(INT_CLEAR)

www.national.com 20

#1 (BIST_CFG1)

Register 0x18 (24’d)

BIST Counter Register

(BIST_CNT)

Register 0x19 (25’d)

BIST Configuration Register

#2 (BIST_CFG2)

Register 0x1A (26’d)

BIST Configuration Register

Register 0x1B (27’d)

Reserved

Register 0x1C (28’d)

Reserved

Register 0x1D (29’d)

Exp Memory Data

(EXP_MEM_DATA)

Register 0x1E (30’d)

Exp Memory Address Pointer

(EXP_MEM_ADD)

Register 0x1F (31’d)

PHY Support Register

(PHY_SUP)

2.0 Register Block (Continued)

2.3 Register Description

In the register description under the ‘Default’ heading, the following definitions hold true:

—RW = Read Write access
—RO = Read Only access
—LH = Latched High until read, based upon the occurrence of the corresponding event
—LL = Latched Low until read, based upon the occurrence of the corresponding event
— SC = Register sets on event occurrence (or is manually set) and Self-Clears when event ends
— P = Register bit is Permanently set to a default value
— STRAP[x] = Default value read from Strapped value at device pin at Reset, where x may take the values:

[0] internal pull-down
[1] internal pull-up

Table 3. Basic Mode Control Register (BMCR) address 0x00

Bit Bit Name Default Description

15 Reset 0, RW, SC Reset:

1 = Initiate software Reset / Reset in Process.
0 = Normal operation.
This bit sets the status and control registers of the PHY to their

default states. This bit, which is self-clearing, returns a value of
one until the res et proces s is co mplete (a pproxima tely 1.2 ms for
reset duration). Reset is finished once the Auto-Negotiation pro­cess has begun or the device has entered it’s forced mode.

14 Loopback 0, RW Loopback:

1 = Loopback enabled.
0 = Normal operation.
The loopback functi on en abl es MII/GMII transmit da ta to be ro ut-

ed to the MII/GMII receive data path. The data loops around at
the DAC/ADC Subsystem (s ee block diagram page 2), bypassing
the Drivers/Recei vers block. This exe rcises m ost of the PH Y’s in­ternal logic.

13 Speed[0] STRAP[0], RW Speed Select:

When Auto-Negotiation is disabled, bits 6 and 13 select device
speed selection per table below:

Speed[1]

11= Reserved
1 0 = 1000 Mbps
0 1 = 100 Mbps
0 0 = 10 Mbps

(The default value of this bit is = to the strap value of pin 7 during
reset/power-on IF Auto-Negotiation is disabled.)

12 AN_EN STRAP[1], RW Auto-Negotiation Enable:

1 = Auto-Negotiation E nabled - bits 6, 8 and 13 of this register are
ignored when this bit is set.

0 = Auto-Negotiation Disabled - bits 6, 8 and 13 determine th e link
speed and mode.

(The default value o f this bit is = to the strap valu e of pin 10 du ring
reset/power-on.)

Speed[0] Speed Enabled

DP83865

21 www.national.com

2.0 Register Block (Continued)

DP83865

Table 3. Basic Mode Control Register (BMCR) address 0x00

Bit Bit Name Default Description

11 Power_Down 0, RW Power Down:

1 = Power down (only Management Interface and logic active.)
0 = Normal operation.
Note: This mode is internally the same as isolate mode (bit 10).

10 Isolate 0, RW Isolate:

1 = Isolates the Port from the MII/GMII with the exception of the
serial management. Wh en this bit is asserte d, the DP83865 doe s
not respond to TXD[7:0], TX_EN, and TX_ER inputs, and it pre­sents a high impeda nce on TX_C LK, RX_CL K, RX_DV, RX_ER,
RXD[7:0], COL and CRS outputs.

0 = Normal operation.

9 Restart_AN 0, RW, SC Restart Auto-Negotiation:

1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation
process. If Auto-Negotiation is disabled (bit 12 = 0), this bit is ig­nored. This bit is self-clearing and will return a value of 1 until
Auto-Negotiation is initiated, whereupon it will self-clear. Opera­tion of the Auto-Negotiation process is not affected by the man­agement entity clearing this bit.

0 = Normal operation.

8 Duplex STRAP[1], RW Duplex Mode:

1 = Full Duplex operati on. D uplex sele ction is a llowed only
Auto-Negotiation is disabled (AN_EN = 0).

0 = Half Duplex operation.
(The default value of this bit is = to the strap value of pin 9 during

reset/power-on IF Auto-Negotiation is disabled.)

7 Collision Test 0, RW Collision Test:

1 = Collision test enabled.
0 = Normal operation.
When set, this bit will cause the COL signal to be asserted in re-

sponse to the assertion of TX_EN withinTBD- bit times. The COL
signal will be de-asserted within 4-bit times in response to the de­assertion of TX_EN.

6 Speed[1] STRAP[0], RW Speed Select: See description for bit 13.

(The default value of this bit is = to the strap value of pin 8 during
reset/power-on IF Auto-Negotiation is disabled.)

5:0 Reserved 0, RO Reserved by IEEE: Write ignored, read as 0.

when

Table 4. Basic Mode Status Register (BMSR) address 0x01

15 100BASE-T4 0, P 100BASE-T4 Capable:

0 = Device not able to perform 100BASE-T4 mode.
DP83865 does not supp ort 100B ASE-T4 mod e and bit sh ould a l-

ways be read back as “0”.

14 100BASE-X

Full Duplex

13 100BASE-X

Half Duplex

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1, P 100BASE-X Full Duplex Capable:

1 = Device able to perform 100BASE-X in Full Duplex mode.

1, P 100BASE-X Half Duplex Capable:

1 = Device able to perform 100BASE-X in Half Duplex mode.

2.0 Register Block (Continued)

Table 4. Basic Mode Status Register (BMSR) address 0x01

12 10BASE-T

Full Duplex

11 10BASE-T

Half Duplex

10 100BASE-T2

Full Duplex

9 100BASE-T2

Half Duplex

8 1000BASE-T

Extended Status

7 Reserved 0, RO Reserved by IEEE: Write ignored, read as 0.
6 Preamble

Suppression

5 Auto-Negotiation

Complete

4 Remote Fault 0, RO, LH Remote Fault:

3 Auto-Negotiation

Ability

2 Link Status 0, RO, LL Link Lost Since Last Read Status:

1 Jabber Detect 0, RO, LH Jabber Detect: Set to 1 if 10BASE-T Jabber detected locally.

0 Extended Capability 1, P Extended Capability:

1, P 10BASE-T Full Duplex Capable:

1 = Device able to perform 10BASE-T in Full Duplex mode.

1, P 10BASE-T Half Duplex Capable:

1 = Device able to perform 10BASE-T in Half Duplex mode.

0, P 100BASE-T2 Full Duplex Capable:

0 = Device unable to perform 100BASE-T2 Full Duplex mode.
DP83865 does not supp ort 100B ASE-T2 mod e and bit sh ould a l-

ways be read back as “0”.

0, P 100BASE-T2 Half Duplex Capable:

0 = Device unable to perform 100BASE-T2 Half Duplex mode.
DP83865 does not supp ort 100B ASE-T2 mod e and bit sh ould a l-

ways be read back as “0”.

1, P 1000BASE-T Extended Status Register:

1 = Device supports Extend ed Status Regi ster 0x0F.

1, P Preamble suppression Capable:

1 = Device able to pe rform ma na gem en t transaction with pream ­ble suppressed, 32-bits of preamble needed only once after re­set, invalid opcode or invalid turnar ou nd.

0, RO Auto-Negotiation Complete:

1 = Auto-Negotiation p rocess complete , and contents o f registers
5, 6, 7, & 8 are valid.

0 = Auto-Negotiation process not complete.

1 = Remote Fault condition detected (cleared on read or by re­set). Fault criteria: Far End Fault Indication or notification from
Link Partner of Remote Fault.

0 = No remote fault condition detected.

1, P Auto Configuration Ability:

1 = Device is able to perform Auto-Negotiation.

1 = Link was good since last read of this register. (10/100/1000
Mbps operation).

0 = Link was lost since last read of this register.
The occurrence of a l ink failure cond ition will caus es the Link Sta-

tus bit to clear. Once cleared, this bit may only be set by estab­lishing a good link condition and a read via the management
interface.

This bit doesn’t indicate the link status, but rather if the link was
lost since last read. For actual link status, either this register
should be read twice, or register 0x11 bit 2 should be read .

1 = Jabber condition detected.
0 = No Jabber.

1 = Extended register capable.

DP83865

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2.0 Register Block (Continued)

DP83865

Table 5. PHY Identifier Register #1 (PHYIDR1) address 0x02

Bit Bit Name Default Description

15:0 OUI[3:18] 16’b<0010_0000

_0000_0000>, P

The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83865. The Identifier consists of a con­catenation of the Organizationally Unique Identifier (OUI), the vendor’s model number and the model revision number. A
PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. Th e PHY Identi fie r is inte nd ed to su p­port network management. National’s IEEE assigned OUI is 0x080017h.

Table 6. PHY Identifier Register #2 (PHYIDR2) address 0x03

Bit Bit Name Default Description

15:10 OUI[19:24] 6’b<01_0111>, P OUI Bits 19:24:

9:4 VNDR_MDL[5:0] 6’b <00_0111>, PVendor Model Number:

3:0 MDL_REV[3:0] 4’b <1010>, P Model Revision Number:

OUI Bits 3:18:

Bits 3 to 18 of the OUI (0x080017h) are stored in bits 15 to 0 of
this register. The mos t signi fican t two bits of the O UI are ig nored
(the IEEE standard refers to these as bits 1 and 2).

Bits 19 to 24 of the OUI (0x 080017h) are mapped to bits 15 to 1 0
of this register respectively.

The six bits of vendor model number are mapped to bits 9 to 4
(most significant bit to bit 9).

Four bits of the vendo r model revisio n number are map ped to bits
3 to 0 (most signi ficant bit to bit 3). This fi eld w il l b e in cre me nte d
for all major device changes.

Table 7. Auto-Negotiation Advertisement Register (ANAR) address 0x04

Bit Bit Name Default Description

15 NP 0, RW Next Page Indication:

1 = Next Page Transfer desired.

0 = Next Page Transfer not desired.
14 Reserved 0, RO Reserved by IEEE: Writes ignored, Read as 0.
13 RF 0, RW Remote Fault:

1 = Advertises that this device has detected a Remote Fault.

0 = No Remote Fault detected.
12 Reserved 0, RO Reserved for Future IEEE use: Write as 0, Read as 0.
11 ASY_PAUSE 0, RW Asymmetrical PAUSE:

1 = MAC/Controller supports Asymmetrical Pause direction.

0 = MAC/Controller does not support Asymmetrical Pause direc-

tion.
10 PAUSE 0, RW PAUSE:

1 = MAC/Controller supports Pause frames.

0 = MAC/Controller does not support Pause frames.

9 100BASE-T4 0, RO 100BASE-T4 Support:

1 = 100BASE-T4 supported.

0 = No support for 100BASE-T4.

DP83865 does not support 100BASE-T4 mode and this bit

should always be read back as “0”.

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2.0 Register Block (Continued)

Table 7. Auto-Negotiation Advertisement Register (ANAR) address 0x04

Bit Bit Name Default Description

8 100BASE-TX

Full Duplex

7 100BASE-TX

(Half Duplex)

6 10BASE-T

Full Duplex

5 10BASE-T

(Half Duplex)

4:0 PSB[4:0] 5’b<0_0001>, P Protocol Selection Bits:

STRAP[1], RW 10 0BASE-TX Full Duple x Support:

1 = 100BASE-TX Full Duplex is supported by the local device.

0 = 100BASE-TX Full Duplex not supported.

The default value of this bit is determined by the combination of

the Duplex Enable and Spee d[1:0] stra p pins duri ng reset/po wer-

on IF Auto-Negotiation is enabled.

The advertised speed is determined by the Speed[1:0]:

Speed[1]

0 0 = 1000B-T, 100B-TX, 10B-T
0 1 = 1000B-T, 100B-TX
1 0 = 1000B-T

1 1 = 1000B-T, 10B-T
The advertised duplex mode is determined by Duplex Mode:
0 = Half Duplex
1 = Full Duplex

STRAP[1], RW 100BASE-TX (Half Duplex) Support:

1 = 100BASE-TX (Half Duplex) is supported by the local device.
0 = 100BASE-TX (Half Duplex) not supported.
(The default valu e o f th is bi t is determined by t he combination of

the Duplex Enable and Spee d[1:0] stra p pins duri ng reset/po wer­on IF Auto-Negotiation is enabled. See bit 8 for details.)

STRAP[1], RW 10BASE-T Full Duplex Support:

1 = 10BASE-T Full Duplex is supported.
0 = 10BASE-T Full Duplex is not supported.
(The default valu e o f th is bi t is determined by t he combination of

the Duplex Enable and Spee d[1:0] stra p pins duri ng reset/po wer­on IF Auto-Negotiation is enabled. See bit 8 for details.)

STRAP[1], RW 10BASE-T (Half Duplex) Support:

1 = 10BASE-T (Half Duplex) is supported by the local device.
0 = 10BASE-T (Half Duplex) is not supported.
(The default valu e o f th is bi t is determined by t he combination of

the Duplex Enable and Spee d[1:0] stra p pins duri ng reset/po wer­on IF Auto-Negotiation is enabled. See bit 8 for details.)

These bits contain the binary encoded protocol selector support­ed by this port. <00 001> indi cates that this devic e supports I EEE

802.3.

Speed[0] Speeds Enabled

DP83865

This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Negoti­ation.

25 www.national.com

2.0 Register Block (Continued)

DP83865

Table 8. Auto-Negotiation Link Partner Ability Register (ANLPAR) address 0x05

Bit Bit Name Default Description

15 NP 0, RO Next Page Indication:

14 ACK 0, RO Acknowledge:

13 RF 0, RO Remote Fault:

12 Reserved 0, RO Reserved for Future IEEE use: Write as 0, read as 0.
11 ASY_PAUSE 0, RO Asymmetrical PAUSE:

10 PAUSE 0, RO PAUSE:

9 100BASE-T4 0, RO 100BASE-T4 Support:

8 100BASE-TX

Full Duplex

7 100BASE-TX

(Half Duplex)

6 10BASE-T

Full Duplex

5 10BASE-T

(Half Duplex)

4:0 PSB[4:0] 5’b<0_0000>, ROProtocol Selection Bits:

0 = Link Partner does not desire Next Page Transfer.
1 = Link Partner desires Next Page Transfer.

1 = Link Partner acknowle dges re ceptio n of the ab ility d ata wo rd.
0 = Not acknowledged.
The Device’s Auto-Negotiation state machine will automatically

control this bit based on the incoming FLP bursts. Software
should not attempt to write to this bit.

1 = Remote Fault indicated by Link Partner.
0 = No Remote Fault indicated by Link Partner.

1 = Link Partner supports Asymmetrical Pause direction.
0 = Link Partner does not s up port Asy mmet r ic al Pa us e di rec tio n.

1 = Link Partner supports Pause frames.
0 = Link Partner does not support Pause frames.

1 = 100BASE-T4 is supported by the Link Partner.
0 = 100BASE-T4 not supported by the Link Partner.

0, RO 100BASE-TX Full Duplex Support:

1 = 100BASE-TX Full Duplex is supported by the Link Partner.
0 = 100BASE-TX Full Duplex not supported by the Link Partner.

0, RO 100BASE-TX (Half Duplex) Support:

1 = 100BASE-TX (Half Duplex) is supported by the Link Partner.
0 = 100BASE-TX (Half Duplex ) not supported by the Link Partner.

0, RO 10BASE-T Full Duplex Support:

1 = 10BASE-T Full Duplex is supported by the Link Partner.
0 = 10BASE-T Full Duplex not supported by the Link Partner.

0, RO 10BASE-T (Half Duplex) Support:

1 = 10BASE-T (Half Duplex) is supported by the Link Partner.
0 = 10BASE-T (Half Duplex) not supported by the Link Partner.

Link Partners’s binary encoded protocol selector.

This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation

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