National Semiconductor DP83849IF Technical data

August 2006

DP83849IF PHYTER® DUAL Industrial Temperature with Fiber Support (FX) and Flexible Port Switching Dual Po rt 10/ 10 0 Mb/s Ethernet Physical Layer Transceiver

DP83849IF PHYTER® DUAL Industrial Temperature with Fiber Support (FX) and Flexible Switching

Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver

General Description

The number of applications requiring Ethernet Connectivity continues to expand. Along with this increased market demand is a change in application requirements. Where single channel Ethernet used to be sufficient, many applications such as wireless remote base stations and industrial networking now require DUAL Port functionality for redundancy or system management.

The DP83849IF is a highly reliable, feature rich device perfectly suited for industrial applications enabling Ethernet on the factory floor. The DP83849IF features two fully independent 10/100 ports for multi-port applications. NATIONAL’s unique po rt switching capabilit y also allows the two ports to be configured to provide fully integrated range extension, media conversion, hardware based failover and port monitoring.

The DP83849IF provides optimum flexibility in MPU selection by supporting both MII and RMII interfaces. The device also provides flexibility by supporting both copper and fiber media. In additio n this de vice includ es a powerful new diagnostics tool to ensure initial network operation and maintenance.

In addition to the TDR scheme, commonly used for detecting faults during installation, NATIONAL’s innovative cable diagnostics provides for real time continuous monitoring of the link quality. This allows the system designer to implement a fault prediction mechanism to detect and warn of changing or deteriorating link conditions.

With the DP83849IF, National Semiconductor continues to build on its Ethernet expertise and leadership position by providing a powerful combination of features and flexibility, easing Ethernet implementation for the system designer.

Features

• Low-power 3.3V, 0.18µm CMOS technology

• Low power consumption <600mW Typical

• 3.3V MAC Interface

• Auto-MDIX for 10/100 Mb/s

• Energy Detection Mode

• Flexible MII Port Assignment

• Dynamic Integrity Utility

• Dynamic Link Quality Monito r ing

• TDR based Cable Diagnostic and Cable Length Detection

• Optimized Latency for Real Time Ethernet Operation

• Reference Clock out

• RMII Rev. 1.2 Interface (configurable)

• SNI Interface (configurable)

• MII Serial Management Interface (MDC and MDIO)

• IEEE 802.3u MII

• IEEE 802.3u Auto-Negotiation and Parallel Detection

• IEEE 802.3u ENDEC, 10BASE-T transceivers and filters

• IEEE 802.3u PCS, 100BASE-TX transceivers and filters

• IEEE 802.3u 100BASE-FX Fiber Interface

• IEEE 1149.1 JTAG

• Integrated ANSI X3.263 compliant TP-PMD physical sub-layer

with adaptive equalization and Baseline Wander compensation

• Programmable LED support for Link, 10 /100 Mb/s Mode, Activ-

ity, Duplex and Collision Detect

• Single register access for complete PHY status

• 10/100 Mb/s packet BIST (Built in Self Test)

• 80-pin TQFP package (12mm x 12mm)

Applications

• Medical Instrumentation

• Factory Automation

• Motor & Motion Control

• Wireless Remote Base Station

• General Embedded Applications

System Diagram

100BASE-FX

Port B

DP83849IF

Port A

Status

LEDs

Magnetics

100BASE-FX

MPU/CPU

MII/RMII/SNI

MAC

MII/RMII/SNI

MAC

25 MHz Clock

Source

Typical Application

PHYTER is a registered trademark of National Semiconductor Corporation

10BASE-T

RJ-45

100BASE-TX

10BASE-T

RJ-45

100BASE-TX

DP83849IF

LED

DRIVERS

PORT A

MII/RMII/SNI

10/100 PHY CORE

PORT A

MII MANAGEMENT

INTERFACE

MDC

MANAGEMENT

INTERFACE

BOUNDARY

SCAN

MDIO

PORT B

MII/RMII/SNI

RXTXTX RX

10/100 PHY CORE

PORT B

LED

DRIVERS

LEDS

TPTD/FXTD±

TPRD/FXRD±

JTAG

TPTD/FXTD±

Figure 1. DP83849IF Functional Block Diagram

LEDS

TPRD/FXRD±

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Table of Contents

1.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.1 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.2 MAC Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.3 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.4 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.5 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

1.6 Reset and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

1.7 Strap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

1.8 10 Mb/s and 100 Mb/s PMD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

1.9 Special Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

1.10 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

1.11 Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.1 Media Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.2 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.2.1 Auto-Negotiation Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.2.2 Auto-Negotiation Register Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.2.3 Auto-Negotiation Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.2.4 Auto-Negotiation Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.2.5 Enabling Auto-Negotiation via Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.2.6 Auto-Negotiation Complete Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3 Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

2.4 PHY Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

2.4.1 MII Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.5 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

2.5.1 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.5.2 LED Direct Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2.6 Half Duplex vs. Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

2.7 Internal Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

2.8 BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

3.0 MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.1 MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.1.1 Nibble-wide MII Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.1.2 Collision Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.1.3 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2 Reduced MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

3.3 10 Mb Serial Network Interface (SNI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

3.4 Single Clock MII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

3.5 Flexible MII Port Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

3.5.1 RX MII Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.5.2 TX MII Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.5.3 Common Flexible MII Port Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.5.4 Strapped Extender or Media Converter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.5.5 Notes and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.6 802.3u MII Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

3.6.1 Serial Management Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.6.2 Serial Management Access Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.6.3 Serial Management Preamble Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.6.4 Simultaneous Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.0 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1 100BASE-TX TRANSMITTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

4.1.1 Code-group Encoding and Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.1.2 Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.1.3 NRZ to NRZI Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.1.4 Binary to MLT-3 Convertor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.2 100BASE-TX RECEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

4.2.1 Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

DP83849IF

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4.2.2 Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.2.2.1 Digital Adaptive Equalization and Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.2.2.2 Base Line Wander Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.2.3 Signal Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.2.4 MLT-3 to NRZI Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.2.5 NRZI to NRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.2.6 Serial to Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.2.7 Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.2.8 Code-group Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.2.9 4B/5B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.2.10 100BASE-TX Link Integrity Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.2.11 Bad SSD Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.3 100BASE-FX Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

4.3.1 100BASE-FX Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.3.2 100BASE-FX Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.3.3 Far-End Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.4 10BASE-T TRANSCEIVER MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

4.4.1 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.4.2 Smart Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.4.3 Collision Detection and SQE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.4.4 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.4.5 Normal Link Pulse Detection/Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.4.6 Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.4.7 Automatic Link Polarity Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.4.8 Transmit and Receive Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.4.9 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.4.10 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.0 Design Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.1 TPI Network Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

5.2 Fiber Network Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

5.3 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

5.4 Clock In (X1) Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

5.5 Power Feedback Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

5.6 Power Down/Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

5.6.1 Power Down Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.6.2 Interrupt Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.7 Energy Detect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

5.8 Link Diagnostic Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

5.8.1 Linked Cable Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.8.1.1 Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.8.1.2 Cable Swap Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.8.1.3 100MB Cable Length Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.8.1.4 Frequency Offset Relative to Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.8.1.5 Cable Signal Quality Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.8.2 Link Quality Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.8.2.1 Link Quality Monitor Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.8.2.2 Checking Current Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.8.2.3 Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.8.3 TDR Cable Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.8.3.1 TDR Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.8.3.2 TDR Pulse Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.8.3.3 TDR Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.8.3.4 TDR Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.0 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.1 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

6.2 Full Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

6.3 Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

7.0 Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.1 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

7.1.1 Basic Mode Control Register (BMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

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7.1.2 Basic Mode Status Register (BMSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.1.3 PHY Identifier Register #1 (PHYIDR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.1.4 PHY Identifier Register #2 (PHYIDR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.1.5 Auto-Negotiation Advertisement Register (ANAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) . . . . . . . . . . . . . . . . 60

7.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) . . . . . . . . . . . . . . . . . 61

7.1.8 Auto-Negotiate Expansion Register (ANER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.1.10 PHY Status Register (PHYSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

7.1.11 MII Interrupt Control Register (MICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

7.1.12 MII Interrupt Status and Misc. Control Register (MISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

7.1.13 Page Select Register (PAGESEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

7.2 Extended Registers - Page 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

7.2.1 False Carrier Sense Counter Register (FCSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.2.2 Receiver Error Counter Register (RECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.2.3 100 Mb/s PCS Configuration and Status Register (PCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.2.4 RMII and Bypass Register (RBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

7.2.5 LED Direct Control Register (LEDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.2.6 PHY Control Register (PHYCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

7.2.7 10 Base-T Status/Control Register (10BTSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.2.8 CD Test and BIST Extensions Register (CDCTRL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

7.2.9 Phy Control Register 2 (PHYCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

7.2.10 Energy Detect Control (EDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

7.3 Link Diagnostics Registers - Page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

7.3.1 100Mb Length Detect Register (LEN100_DET), Page 2, address 14h . . . . . . . . . . . . . . . . . 78

7.3.2 100Mb Frequency Offset Indication Register (FREQ100), Page 2, address 15h . . . . . . . . . 78

7.3.3 TDR Control Register (TDR_CTRL), Page 2, address 16h . . . . . . . . . . . . . . . . . . . . . . . . . . 79

7.3.4 TDR Window Register (TDR_WIN), Page 2, address 17h . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

7.3.5 TDR Peak Register (TDR_PEAK), Page 2, address 18h . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

7.3.6 TDR Threshold Register (TDR_THR), Page 2, address 19h . . . . . . . . . . . . . . . . . . . . . . . . . 80

7.3.7 Variance Control Register (VAR_CTRL), Page 2, address 1Ah . . . . . . . . . . . . . . . . . . . . . . 81

7.3.8 Variance Data Register (VAR_DATA), Page 2, address 1Bh . . . . . . . . . . . . . . . . . . . . . . . . 81

7.3.9 Link Quality Monitor Register (LQMR), Page 2, address 1Dh . . . . . . . . . . . . . . . . . . . . . . . . 82

7.3.10 Link Quality Data Register (LQDR), Page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

8.0 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

8.1 DC Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

8.2 AC Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

8.2.1 Power Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

8.2.2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

8.2.3 MII Serial Management Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

8.2.4 100 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

8.2.5 100 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

8.2.6 100BASE-TX and 100BASE-FX MII Transmit Packet Latency Timing . . . . . . . . . . . . . . . . . 89

8.2.7 100BASE-TX and 100BASE-FX MII Transmit Packet Deassertion Timing . . . . . . . . . . . . . . 90

8.2.8 100BASE-TX Transmit Timing (tR/F & Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

8.2.9 100BASE-TX and 100BASE-FX MII Receive Packet Latency Timing . . . . . . . . . . . . . . . . . 92

8.2.10 100BASE-TX and 100BASE-FX MII Receive Packet Deassertion Timing . . . . . . . . . . . . . 92

8.2.11 10 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

8.2.12 10 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

8.2.13 10 Mb/s Serial Mode Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

8.2.14 10 Mb/s Serial Mode Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

8.2.15 10BASE-T Transmit Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

8.2.16 10BASE-T Transmit Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

8.2.17 10BASE-T Receive Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

8.2.18 10BASE-T Receive Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

8.2.19 10 Mb/s Heartbeat Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

8.2.20 10 Mb/s Jabber Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

8.2.21 10BASE-T Normal Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

8.2.22 Auto-Negotiation Fast Link Pulse (FLP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

8.2.23 100BASE-TX Signal Detect Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

8.2.24 100 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

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8.2.25 10 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

8.2.26 RMII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

8.2.27 RMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

8.2.28 Single Clock MII (SCMII) Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

8.2.29 Single Clock MII (SCMII) Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

8.2.30 Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

8.2.31 CLK2MAC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

9.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

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List of Figures

Figure 1. DP83849IF Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Figure 2. PHYAD Strapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 3. AN Strapping and LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 4. MII Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 5. Typical MDC/MDIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 6. Typical MDC/MDIO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 7. 100BASE-TX Transmit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 8. 100BASE-TX Receive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 9. EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT 5 cable . . . . . . . . . . . 36

Figure 10. 100BASE-TX BLW Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 11. 10BASE-T Twisted Pair Smart Squelch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 12. 10/100 Mb/s Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 13. 100 Mb/s Fiber Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 14. Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 15. Power Feeback Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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List of Tables

Table 1. Auto-Negotiation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 2. PHY Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 3. LED Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 4. Supported packet sizes at +/-50ppm frequency accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 5. Supported SCMII packet sizes at +/-50ppm frequency accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 6. RX MII Port Mapping Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 7. RX MII Port Mapping Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 8. TX MII Port Mapping Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 9. TX MII Port Mapping Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 10. Common Flexible MII Port Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 11. Common Strapped Extender/Media Converter Mode Configurations . . . . . . . . . . . . . . . . . . . . . . .29

Table 12. Typical MDIO Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 13. 4B5B Code-Group Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 14. 25 MHz Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 15. 50 MHz Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 16. 25 MHz Crystal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 17. Link Quality Monitor Parameter Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 18. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 19. Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 20. Basic Mode Control Register (BMCR), address 00h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 21. Basic Mode Status Register (BMSR), address 01h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Table 22. PHY Identifier Register #1 (PHYIDR1), address 02h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 23. PHY Identifier Register #2 (PHYIDR2), address 03h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 24. Negotiation Advertisement Register (ANAR), address 04h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 25. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 05h . . . . . . . . .60

Table 26. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 05h . . . . . . . . . .61

Table 27. Auto-Negotiate Expansion Register (ANER), address 06h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Table 28. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 07h . . . . . . . . . . . . . . . . . . . .63

Table 29. PHY Status Register (PHYSTS), address 10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Table 30. MII Interrupt Control Register (MICR), address 11h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 31. MII Interrupt Status and Misc. Control Register (MISR), address 12h . . . . . . . . . . . . . . . . . . . . . . .66

Table 32. Page Select Register (PAGESEL), address 13h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 33. False Carrier Sense Counter Register (FCSCR), address 14h . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 34. Receiver Error Counter Register (RECR), address 15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 35. 100 Mb/s PCS Configuration and Status Register (PCSR), address 16h . . . . . . . . . . . . . . . . . . . . .68

Table 36. RMII and Bypass Register (RBR), addresses 17h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 37. LED Direct Control Register (LEDCR), address 18h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 38. PHY Control Register (PHYCR), address 19h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 39. 10Base-T Status/Control Register (10BTSCR), address 1Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 40. CD Test and BIST Extensions Register (CDCTRL1), address 1Bh . . . . . . . . . . . . . . . . . . . . . . . . . .76

Table 41. Phy Control Register 2 (PHYCR2), address 1Ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Table 42. Energy Detect Control (EDCR), address 1Dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 43. 100Mb Length Detect Register (LEN100_DET), address 14h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 44. 100Mb Frequency Offset Indication Register (FREQ100), address 15h . . . . . . . . . . . . . . . . . . . . . .78

Table 45. TDR Control Register (TDR_CTRL), address 16h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 46. TDR Window Register (TDR_WIN), address 17h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Table 47. TDR Peak Register (TDR_PEAK), address 18h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Table 48. TDR Threshold Register (TDR_THR), address 19h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Table 49. Variance Control Register (VAR_CTRL), address 1Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Table 50. Variance Data Register (VAR_DATA), address 1Bh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Table 51. Link Quality Monitor Register (LQMR), address 1Dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Table 52. Link Quality Data Register (LQDR), address 1Eh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

DP83849IF

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Pin Layout

DP83849IF

RX_ER_B/MDIX_EN_B

COL_B/FX_EN_B

RXD0_B/PHYAD3

RXD1_B/PHYAD4

RXD2_B/EXTENDER_EN

COREGND2

PFBIN4

RXD3_B/ED_EN_B

IOGND2

IOVDD2

TX_CLK_B

TX_EN_B

TXD0_B

TXD1_B

TXD2_B

TXD3_B/SNI_MODE_B

PWRDOWN_INT_B

LED_LINK_B/AN0_B

LED_SPEED_B/FXSD_B/AN1_B

LED_ACT/LED_COL/AN_EN_B

60595857565554535251504948474645444342

TCK

TDI

61 62 63 64 65 66 67 68 69

71 72 73 74 75 76 77 78 79 80

DP83849IFVS

1011121314151617181920

RS_B/CRS_DV_B/LED_CFG_B

RX_DV_B/MII_MODE_B

RX_CLK_B

IOGND3

IOVDD3

MDIO

MDC

CLK2MAC

RESET_N

TDO TMS

TRSTN

IOGND4

IOVDD4

RX_CLK_A

RX_DV_A/MII_MODE_A

ANAGND4

TPRDM_B/FXRDM_B

TPRDP_B/FXRDP_B

CDGND2

TPTDM_B/FXTDM_B

TPTDP_B/FXTDP_B

PFBIN3

ANAGND3

RBIAS

PFBOUT

ANA33VDD

ANAGND2

PFBIN2

TPTDP_A/FXTDP_A

TPTDM_A/FXTDM_A

CDGND1

TPRDP_A/FXRDP_A

TPRDM_A/FXRDM_A

ANAGND1 LED_ACT/LED_COL/AN_EN_A

PFBIN1

COREGND1

COL_A/FX_EN_A

RXD0_A/PHYAD1

RXD1_A/PHYAD2

RX_ER_A/MDIX_EN_A

CRS_A/CRS_DV_A/LED_CFG_A

RXD2_A/CLK2MAC_DIS

IOVDD1

IOGND1

RXD3_A/ED_EN_A

TXD0_A

TXD1_A

TX_EN_A

TX_CLK_A

TXD2_A

PWRDOWN_INT_A

LED_LINK_A/AN0_A

TXD3_A/SNI_MODE_A

LED_SPEED_A/FXSD_A/AN1_A

Top View

NS Package Number VHB80A

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1.0 Pin Descriptions

The DP83849IF pins are classified into the following interface categories (each interface is described in the sections that follow):

— Serial Management Interface — MAC Data Interface — Clock Interface — LED Interface —JTAG Interface — Reset and Power Down — Strap Options — 10/100 Mb/s PMD Interface — Special Connect Pins — Power and Ground pins

1.1 Serial Management Interface

Signal Name Type Pin # Description

MDC I 67 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO

management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate.

MDIO I/O 66 MANAGEMENT DATA I/O: Bi-directional management instruc-

tion/data signal that may be sou rced by the stati on management en tity or the PHY . This pin requires a 1.5 kΩ pullup resistor.

Note: Strapping pin option. Please s ee Section 1.7 for strap definitions.

All DP83849IF signal pins are I/O cells regardless of the particular use. The defi nition s below define the functiona lit y of the I/O cells for each pin.

Type: I Input Type: O Output Type: I/O Input/Output Type OD Open Drain Type: PD,PU Internal Pulldown/Pullup Type: S Strapping Pin (All strap pins have weak in-

ternal pu ll-ups or pull- downs. If the default strap value is to be changed then an exter nal 2.2 kΩ resistor should be used. Please see Section 1.7 for details.)

DP83849IF

1.2 MAC Data Interface

Signal Name Type Pin # Description

TX_CLK_A TX_CLK_B

TX_EN_A TX_EN_B

TXD[3:0]_A TXD[3:0]_B

O 12

I 13

I 17,16,15,14

45,46,47,48

MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode or 2.5 MH z in 10 Mb/s m ode derived f rom the 25 MHz reference clock.

Unused in RMII mo de. T he d evi ce uses the X1 reference cloc k in put as the 50 MHz reference for both transmit and receive.

SNI TRANSMIT CLOCK: 10 MHz Transmit cloc k output in 10 Mb SNI mode. The MAC should source TX_EN and TXD_0 using this clock.

MII TRANSMIT ENABLE: Active high input indic ates th e prese nce of valid data inputs on TXD[3:0].

RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0].

SNI TRANSMIT ENABLE: Active high input indic ates the presence of valid data on TXD_0.

MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).

RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to the 50 MHz reference clock.

SNI TRANSMIT DATA: Transmit data SNI input p in, T XD _0, that accept data synch ronous to the TX_CL K (10 MHz in 10 Mb/s SNI mode).

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1.2 MAC Data Interface (Continued)

Signal Name Type Pin # Description

RX_CLK_A RX_CLK_B

RX_DV_A RX_DV_B

RX_ER_A RX_ER_B

RXD[3:0]_A RXD[3:0]_B

CRS_A/CRS_DV_A CRS_B/CRS_DV_B

COL_A COL_B

O 79

O 80

O 2

O 9,8,5,4

53,56,57,58

O 1

O 3

MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.

Unused in RMII mo de. T he d evi ce uses the X1 reference clock input as the 50 MHz reference for both transmit and receive.

SNI RECEIVE CLOCK: Provides the 10 MHz recovered receive clocks for 10 Mb/s SNI mode.

MII RECEIVE DATA VALID: Asserted high to i ndi ca te th at v al id d ata is present on the corresponding RXD[3:0].

RMII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[1:0]. This signal is not re quired in RMII mode, since CRS_DV includes the RX_DV signal, but is provided to allow simpler recovery of the Receive data.

This pin is not used in SNI mode. MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to

indicate that an invalid symbol has been detected within a received packet in 100 Mb/s mode.

RMII RECEIVE ERROR: Asserted high synchronou sly to X1 when ever an invalid symbo l is detected, and CRS _DV is asserted in 100 Mb/s mode. This pin is als o ass ert ed on d ete cti on of a Fa ls e C arr ier eve nt. This pin is not required to be used by a MAC in RMII mode, since the Phy is required to corrupt data on a receive error.

This pin is not used in SNI mode. MII RECEIVE DATA: Nibble wide receive data signals driven syn-

chronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data when RX_DV is asserted.

RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronousl y to the X1 clock, 50 MHz.

SNI RECEIVE DATA: Receive data signal, RXD_0, driven synchronously to the RX_CLK. RXD_0 contains valid data when CRS is asserted. RXD[3:1] are not used in this mode.

MII CARRIER SENSE: Asserted high to indicate th e receive me dium is non-idle.

RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and Receive Data Valid indications. For a detailed description of this signal, see the RMII Specification.

SNI CARRIER SENSE: Asserted high to in dicate the receive medium is non-idle. It is used to fra me valid receive data on the RXD _0 sign al.

MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes.

While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1µs at the end of transmission to indicate heartbeat (SQE test).

In Full Duplex M ode, fo r 10 M b/s or 100 Mb /s op eration , this signa l is always logic 0. There is no heartbeat function during 10 Mb/s full du plex operation.

RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC will recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine collision.

SNI COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s SNI mode.

DP83849IF

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1.3 Clock Interface

Signal Name Type Pin # Description

X1 I 70 CRYSTAL/OSCILLATOR INPUT: This pin i s the primary clock

X2 O 69 CRYSTAL OUTPUT: This pin is the primary clock reference out-

CLK2MAC O 68 CLOCK TO MAC:

reference input fo r the DP83849IF and must be co nnected to a 25 MHz 0.005% ( either an external crys tal resonator connecte d across pins X1 and X2, or an external CMO S-level oscil lator sourc e connec ted to pin X1 only.

RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode and mu st be connected to a 50 MHz

0.005% (

put to connect to an external 25 MHz crystal resonator device. This pin must be left unconnected if an ex tern al C MOS os c ill ato r clock source is used.

In MII mode, this pin provides a 25 MHz clock output to the system.

In RMII mode, this pin prov ides a 50 MHz cloc k outpu t to the sys tem.

This allows other devices to use the reference clock from the DP83849IF without requiring additional clock sources.

If the system does not require the CLK2MAC signal, the CLK2MAC output should be disabled via the CLK2MAC disable strap.

+50 ppm) clock source. The DP83849IF supports

+50 ppm) CMOS-level oscillator source.

DP83849IF

1.4 LED Interface

The DP83849IF supports three configurable LED pins. The LEDs support two operational modes which are selected by the LED mode s trap an d a thi rd ope rationa l mod e whic h

Signal Name Type Pin # Description

LED_LINK_A LED_LINK_B

LED_SPEED_A LED_SPEED_B

LED_ACT/LED_COL_A LED_ACT/LED_COL_B

I/O 19

I/O 20

I/O 21

LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be ON when Link is good.

LINK/ACT LED: In Mode 2 and Mode 3, this pi n indicates tra nsmit and receive activity in addition to the status of the Link. The LED will be ON when Link is good. It will blink when the transmitter or receiver is active.

SPEED LED: The LED is ON when device is i n 100 Mb/s and OFF when in 10 Mb/s. Functionality of this LED is independ ent of mode selected.

ACTIVITY LED: In Mode 1, this pin is the A ctivity L ED which i s ON when activity is present on either Transmit or Receive.

COLLISION/DUPLEX LED: In Mode 2, this pin by default indicates Collision detection. For Mode 3, this LED output may be programmed to indicate Full-duplex status instead of Collision.

is register configurable. The definitions for the LEDs for each mode are detailed below. Since the LEDs are also used as strap options, the polarity of the LED output is dependent on whether the pin is pulled up or down.

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1.5 JTAG Interface

Signal Name Type Pin # Description

TCK I, PU 72 TEST CLOCK

This pin has a weak internal pullup.

TDO O 73 TEST OUTPUT

TMS I, PU 74 TEST MODE SELECT

This pin has a weak internal pullup.

TRSTN I, PU 75 TEST RESET Active low test reset.

This pin has a weak internal pullup.

TDI I, PU 76 TEST DATA INPUT

This pin has a weak internal pullup.

1.6 Reset and Power Down

Signal Name Type Pin # Description

RESET_N I, PU 71 RESET: Active Low input that initializes or re-initializes the

PWRDOWN_INT_A PWRDOWN_INT_B

I, PU 18

DP83849IF. Asserting this pin low for at least 1 µs will force a re set process to occur. All internal registers will re-initialize to their default stat es as sp eci fie d for ea ch bi t in th e Regi ste r Bloc k section. All strap options are re-initialized as well.

The default function of this pin is POWER DOWN. POWER DOWN: The pin is an active low input in this mode and

should be asserted low to put the device in a Power Down mode. INTERRUPT: The pin is an open drain output in thi s mode and will

be asserted low when a n in terru pt co nd itio n oc c urs . Alth oug h the pin has a weak internal pull-up, some applications may require an external pull-up resi ster. R egister a ccess i s requi red for th e pin to be used as an in terrupt me chanism. Se e Mechanism for more details on the interrupt mechanisms.

Section 5.6.2 Interrupt

DP83849IF

1.7 Strap Options

The DP83849IF uses many of the functional pins as strap options. The values of these pins are sampled during reset and used to strap the device into specific modes of opera tion. The strap option pin assignments are defined below. The functional pin name is indicated in parentheses.

Signal Name Type Pin # Description

PHYAD1 (RXD0_A) PHYAD2 (RXD1_A) PHYAD3 (RXD0_B) PHYAD4 (RXD1_B)

S, O, PD S, O, PD S, O, PD S, O, PD

58 57

PHY ADDRESS [4:1]: The DP83849IF provides four PHY address pins, the state of which are la tch ed into the PHYC TRL re g-

ister at system Hardware-Reset. Phy Address[0] selects betwe en ports A and B.

The DP83849IF supports PHY Address strapping for Port A even values 0 (<0000_0>) through 30 (<1111_0>). Port B will be strapped to odd values 1 (<0000_1>) through 31 (<1111_1>).

PHYAD[4:1] pins have weak internal pull-down resistors.

A 2.2 kΩ resistor should be used for pull-down or pull-up to change the default strap option. If the default option is required, then there is no need for external pull-up or pull

down resistors. Since these pins may have alternate func

tions after reset is deasserted, they should not be connected directly to VCC or GND.

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1.7 Strap Options (Continued)

Signal Name Type Pin # Description

FX_EN_A (COL_A) FX_EN_B (COL_B)

AN_EN (LED_ACT/LED_COL_A)

AN1_A (LED_SPEED_A) AN0_A (LED_LINK_A)

AN_EN (LED_ACT/LED_COL_B)

AN1_B (LED_SPEED_B) AN0_B (LED_LINK_B)

S, O, PU

S, I, PD

21 20 19

41 42 43

FX ENABLE: Default is to disable 100BASE-FX (Fiber) mode. This strapping option enables 100BASE-FX. An external pull-up will enable 100BASE-FX mode.

Auto-Negotiation Enable: When high, thi s enable s Auto-Negot iation with the capab ility se t by AN0 and AN1 pin s. When low , this puts the part into Forced Mode with the capability set by AN0 and AN1 pins.

AN0 / AN1: These input pins control the forced or advertised operating mode of the DP83849IF according to the following table. The value on these pins is set by connecting the input pins to GND (0) or V

NEVER be connected directly to GND or VCC. Fiber Mode Duplex Selection: If Fiber mode is strapped using

the FX_EN pi n , t he A N0 st ra p va lu e i s u s ed to s el e ct Hal f or F u ll Duplex. AN_EN and AN1are ignored if FX_EN is asserted, since Fiber mode is 100Mb on ly and does not s upport Auto-Negotia tion.

The value set at this input is latc hed into the D P83 84 9IF at Ha rdware-Reset.

The float/pull-down status of these pins are latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset.

The default is 0111 si nce the FX_EN pin has an i nternal pull-down and the Auto-Negotiation pins have internal pull-ups.

(1) through 2.2 kΩ resistors. These pin s should

DP83849IF

FX_EN AN_EN AN1 AN0 Forced Mode

0 0 0 0 10BASE-T, Half-Duplex 0 0 0 1 10BASE-T, Full-Duplex 0 0 1 0 100BASE-TX, Half-Duplex 0 0 1 1 100BASE-TX, Full-Duplex 1 X X 0 100BASE-FX, Half-Duplex 1 X X 1 100BASE-FX, Full-Duplex

FX_EN AN_EN AN1 AN0 Advertised Mode

0 1 0 0 10BASE-T, Half/Full-Duplex 0 1 0 1 100BASE-TX, Half/Full-Duple 0 1 1 0 10BASE-T Half-Duplex

100BASE-TX, Half-Duplex

0 1 1 1 10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duple

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1.7 Strap Options (Continued)

Signal Name Type Pin # Description

MII_MODE_A (RX_DV_A) SNI_MODE_A (TXD3_A) MII_MODE_B (RX_DV_B) SNI_MODE_B (TXD3_B)

S, O, PD 80

17 62 45

DP83849IF

MII MODE SELECT: This strapping option pair determines the

operating mode of the MAC Data Interface. Default operation (No pull-ups) will ena ble no rmal M II Mo de of o peratio n. Strappin g MII_MODE high will c ause th e dev ice to be in RM II or SNI mo des of operation, determined by the status of the SNI_MODE strap. Since the pins include internal pull-downs, the default values are

0. Both MAC Data Interface s mus t ha ve the ir RMII M od e setti ngs the same, i.e. both in RMII mode or both not in RMII mode.

The following table details the configurations:

MII_MODE SNI_MODE MAC Interface

0 X MII Mode 1 0 RMII Mode 1 1 10 Mb SNI Mode

LED_CFG_A (CRS_A/CRS_DV_A)

LED_CFG_B (CRS_B/CRS_DV_B)

MDIX_EN_A (RX_ER_A) MDIX_EN_B (RX_ER_B)

ED_EN_A (RXD3_A) ED_EN_B (RXD3_B)

CLK2MAC_DIS (RXD2_A) S, O, PD 8 Clock to MAC Disable: This strapp ing option disab les (floats) the

EXTENDER_EN (RXD2_B) S, O, PD 56 Extender Mode Enab le: This strapping option en abl es Ext ender

S, O, PU 1

S, O, PU 2

S, O, PD 9

LED CONFIGURATION: This strapping option determines the mode of operation of the LED pin s. Default is Mode 1. Mode 1 and Mode 2 can be controlle d via the strap opt ion. All mode s are co n figurable via register access.

See Table 3 on page 21 for LED Mode Selection. MDIX ENABLE: Default is to enable MDIX. Thi s strap pin g option

disables Auto-MDIX. An external pull-down will disable AutoMDIX mode.

Energy Detect ENABLE: Default is to disable Energy Detect mode. This strapping option enables Energy Detect mode for the port. In Energy Detect mode, the device will initially be in a lowpower state until de tecting a ctivity on the wire . An extern al pull-u p will enable Energy Detect mode.

CLK2MAC pin. Default is to enable CLK2 MAC output. An external pullup will disa ble (float) t he CLK2MAC pin. If th e system does not require the CLK2MAC si gnal, the CLK2MAC output should be dis abled via this strap option.

Mode for both ports. When enabled, the strap will enable Single Clock MII TX and RX modes unless RMII Mode is also strapped. SNI Mode cannot be strapped if Extender Mode is strapped.

Mode

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1.8 10 Mb/s and 100 Mb/s PMD Interface

Signal Name Type Pin # Description

TPTDM_A/FXTDM_A TPTDP_A/FXTDP_A TPTDM_B/FXTDM_B TPTDP_B/FXTDP_B

TPRDM_A/FXRDM_A TPRDP_A/FXRDP_A TPRDM_B/FXRDM_B TPRDP_B/FXRDP_B

FXSD_A (LED_SPEED_A/AN1_A)

FXSD_B (LED_SPEED_B/AN1_B)

I/O 26

I/O 23

I 20

27 36 35

24 39 38

DP83849IF

10BASE-T or 100BASE-TX or 100BASE-FX Transmit Data

In 10BASE-T or 100BASE-TX: Differential common driver transmit output (PMD Ou tput Pair). Th ese different ial ou tputs are a utomatically configured to either 10BASE-T or 100BASE-TX signaling.

In Auto-MDIX mode of opera tion, this pa ir can be used as the Receive Input pair.

In 100BASE-FX mode, this pair becomes the 100BASE-FX Transmit pair.

These pins require 3.3V bias for operation.

10BASE-T or 100BASE-TX or 100BASE-FX Receive Data

In 10BASE-T or 100BASE-TX: Differenti al receiv e input (PMD In put Pair). These differential in puts are autom atically configured to accept either 100BASE-TX or 10BASE-T signaling.

In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair.

In 100BASE-FX mode, this pair becomes the 100BASE-FX Receive pair.

These pins require 3.3V bias for operation. FX Signal Detect: This pin provides the Signal Detect input for

100BASE-FX mode.

1.9 Special Connections

Signal Name Type Pin # Description

RBIAS I 32 Bias Resistor Connection: A 4.87 kΩ 1% resistor should be con -

PFBOUT O 31 Power Feedback Output: Parallel caps, 10µ F and 0.1µF, should

PFBIN1 PFBIN2 PFBIN3 PFBIN4

I 7

28 34 54

nected from RBIAS to GND.

be placed close to the PFBOUT. Connect this pin to PFBIN1 (pin

13), PFBIN2 (pin 27), PFBIN3 (pin35), PFBIN4 (pin 49). See Section 5.5 for proper placement pin.

Power Feedback Input: These pins are fed with power from PFBOUT pin. A small capacitor of 0.1µF should be connected close to each pin.

Note: Do not supply power to these pins other than from PFBOUT.

1.10 Power Supply Pins

Signal Name Pin # Description

IOVDD1, IOVDD2, IOVDD3, IOVDD4

IOGND1, IOGND2, IOGND3, IOGND4

COREGND1, COREGND2 6,55 Core Ground CDGND1, CDGND2 25,37 CD Ground ANA33VDD 30 Anal og 3.3V Supply ANAGND1, ANAGND2,

ANAGND3, ANAGND4

11,51,65,78 I/O 3.3V Supply

10,52,64,77 I/O Ground

22,29,33,40 Analog Ground

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1.11 Package Pin Assignments

DP83849IF

VHB80A Pin #Pin Name

1 CRS_A/CRS_DV_A/LED_CFG_A 2 RX_ER_A/MDIX_EN_A 3 COL_A/FX_EN_A 4 RXD0_A/PHYAD1 5 RXD1_A/PHYAD2 6 COREGND1 7 PFBIN1 8 RXD2_A/CLK2MAC_DIS

9 RXD3_A/ED_EN_A 10 IOGND1 11 IOVDD1 12 TX_CLK_A 13 TX_EN_A 14 TXD0_A 15 TXD1_A 16 TXD2_A 17 TXD3_A/SNI_MODE_A 18 PWRDOWN_INT_A 19 LED_LINK_A/AN0_A 20 LED_SPEED_A/FXSD_A/AN1_A 21 LED_ACT/LED_COL/AN_EN_A 22 ANAGND1 23 TPRDM_A/FXRDM_A 24 TPRDP_A/FXRDP_A 25 CDGND1 26 TPTDM_A/FXTDM_A 27 TPTDP_A/FXTDP_A 28 PFBIN2 29 ANAGND2 30 ANA33VDD 31 PFBOUT 32 RBIAS 33 ANAGND3 34 PFBIN3 35 TPTDP_B/FXTDP_B 36 TPTDM_B/FXTDM_B 37 CDGND2 38 TPRDP_B/FXRDP_B 39 TPRDM_B/FXRDM_B 40 ANAGND4 41 LED_ACT/LED_COL/AN_EN_B 42 LED_SPEED_B/FXSD_B/AN1_B

43 LED_LINK_B/AN0_B 44 PWRDOWN_INT_B 45 TXD3_B/SNI_MODE_B 46 TXD2_B 47 TXD1_B 48 TXD0_B 49 TX_EN_B 50 TX_CLK_B 51 IOVDD2 52 IOGND2 53 RXD3_B/ED_EN_B 54 PFBIN4 55 COREGND2 56 RXD2_B/EXTENDER_EN 57 RXD1_B/PHYAD4 58 RXD0_B/PHYAD3 59 COL_B/FX_EN_B 60 RX_ER_B/MDIX_EN_B 61 CRS_B/CRS_DV_B/LED_CFG_B 62 RX_DV_B/MII_MODE_B 63 RX_CLK_B 64 IOGND3 65 IOVDD3 66 MDIO 67 MDC 68 CLK2MAC 69 X2 70 X1 71 RESET_N 72 TCK 73 TDO 74 TMS 75 TRSTN 76 TDI 77 IOGND4 78 IOVDD4 79 RX_CLK_A 80 RX_DV_A/MII_MODE_A

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2.0 Configuration

This section in clude s inform atio n on the var ious con figura tion options available with the DP83849IF. The configuration options described below include:

— Media Configuration — Auto-Negotiation — PHY Address and LEDs — Half Duplex vs. Full Duplex — Isolate mode — Loopback mode —BIST

2.1 Media Configuration

The DP83849IF supports both Twister Pair (100BASE-TX and 10BASE-T) and Fiber (100BASE-FX) media. Each port may be independe ntly confi gu r ed fo r Twisted Pair (TP) or Fiber (FX) operation by strap option or by register access.

At power-up/reset, the st ate of the COL_A and COL_B pins will select the media for ports A and B respectively. The default selection is TP mode, while an external pull-up will select FX mode of operation. Strapping a port into FX mode also automatically sets the Far-End Fault Enable, bit 3 of PCSR (16h), the Scramble Bypass, bit 1 of PCSR (16h) and the Descrambler Bypass, bit 0 of PCSR (16h). In addition, the media selection may be controlled by writing to bit 6, FX_EN, of PCSR (16h).

2.2 Auto-Negotiation

The Auto-Negotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest per formance mode of operation supported by both devices. Fast Link Pulse (FLP) Bursts provide the signalling used to communicate Auto-Negotiation abilities between two devices at each end of a link segment. For further detail regarding Auto-Negotiation, refer to Clause 28 of the IEEE

802.3u specification. The DP83849IF supports four differ ent Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex), so the inclusion of Auto-Negotiation ensures that the high est performance protocol will be selected based on the advertised ability of the Link Partner. The Auto-Negotiation function within the DP83849IF can be controlled either by internal register access or by the use of the AN_EN, AN1 and AN0 pins.

2.2.1 Auto-Negotiation Pin Control

The state of AN_EN, AN0 an d AN1 det ermine s wheth er the DP83849IF is forced into a specific mode or Auto-Negotia tion will advertise a specific ability (or set of abilities) as given in be selected without requiring internal register access.

The state of AN _EN, AN0 and A N1, upon po wer-up/ reset, determines the state of bits [8:5] of the ANAR register.

The Auto-Negotiation function selected at power-up or reset can be cha nged at any time by writin g to the Basic Mode Contro l Register (BMCR) at address 00h.

Table 1. These pins allow configuration options to

Table 1. Auto-Negotiation Modes

AN_EN AN1 AN0 Forced Mode

0 0 0 10BASE-T, Half-Duplex 0 0 1 10BASE-T, Full-Duplex 0 1 0 100BASE-TX, Half-Duplex 0 1 1 100BASE-TX, Full-Duplex

AN_EN AN1 AN0 Advertised Mo0e

1 0 0 10BASE-T, Half/Full-Duplex 1 0 1 100BASE-TX, Half/Full-Duplex 1 1 0 10BASE-T Half-Duplex

100BASE-TX, Half-Duplex

1 1 1 10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

2.2.2 Auto-Negotiation Register Control

When Auto-Negotiation is enabled, the DP83849IF transmits the abilities programmed into the Auto-Negotiation Advertisement register (ANAR) at address 04h via FLP Bursts. Any combination of 10 Mb/s, 100 Mb/s, HalfDuplex, and Full Duplex modes may be selected.

Auto-Negotiation Priority Resolution: — (1) 100BASE-TX Full Duplex (Highest Priority)

— (2) 100BASE-TX Half Duplex — (3) 10BASE-T Full Duplex — (4) 10BASE-T Half Duplex (Lowest Priority) The Basic Mode Control Register (BMCR) at address 00h

provides control for enabling, disabling, and restarting the Auto-Negotiation process. When Auto-Negotiation is dis abled, the Speed Selection bit in the BMCR controls switching between 10 Mb/s or 100 Mb/s operation, and the Duplex Mode bit controls switching between full duplex operation and half duplex operation. The Speed Selection and Duplex Mode bits have no effect on the mode of oper ation when the Auto-Negotiation Enable bit is set.

The Link Speed can be examined through the PHY Status Register (PHYSTS) at address 10h after a Link is achieved.

The Basic Mode Status Register (BMSR) indicates the set of available abilities for technology types, Auto-Negotiation ability, and Extended Register Capability. These bits are permanently set to indicate the full functionality of the DP83849IF (only the 100BASE-T4 bit is not set since the DP83849IF does not support that function).

The BMSR also provides status on: — Whether or not Auto-Negotiation is complete — Whether or not the Link Partner is advertising that a re-

mote fault has occurred — Whether or not valid link has been established — Support for Management Frame Preamble suppression The Auto-Negotiation Advertisement Register (ANAR) indi-

cates the Auto-Negotiation abilities to be advertised by the DP83849IF. All available abilities are transmitted by default, but any ability can be suppressed by writing to the

DP83849IF

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ANAR. Updating the ANAR to suppress an ability is one way for a management agent to change (restrict) the tech nology that is used.

The Auto-Negotiation Link Partner Ability Register (ANLPAR) at address 05h is used to receive the base link code word as well as all next page code words during the negotiati on. Furthermore, the ANLPAR will be updat ed to either 0081h or 0021h for parallel detection to either 100 Mb/s or 10 Mb/s respectively.

The Auto-Negotiation Expansion Register (ANER) indicates additional Auto-Negotiation status. The ANER provides status on:

— Whether or not a Parallel Detect Fault has occurred — Whether or not the Link Partne r supp orts the N ext Pag e

function

— Whether or not the DP83849IF supports the Next Page

function

— Whether or not the current page being exchanged by

Auto-Negotiation has been receiv ed

— Whether or not the Link Partner supports Auto-Negotia-

tion

2.2.3 Auto-Negotia tion Para llel Detection

The DP83849IF supports the Parallel Detection function as defined in the IEEE 802.3u specifi ca tio n. Para lle l De tect io n requires both the 10 Mb/s and 100 Mb/s receivers to moni tor the receive signal and report link status to the AutoNegotiation function. Auto-Negotiation uses this informa tion to configure th e corre ct techno logy i n the e vent th at the Link Partner does not support Auto-Negotiation but is transmitting link signals that the 100BASE-TX or 10BASET PMAs recognize as valid link signa ls .

If the DP83849IF co mp lete s Au to-Negotiation as a result of Parallel Detection, bits 5 and 7 within the ANLPAR register will be set to reflect the mode of operation present in the Link Partner. Note that bits 4:0 of the ANLPAR will also be set to 00001 based on a successful parallel detection to indicate a valid 802.3 selector field. Software may deter mine that negotiation completed via Parallel Detection by reading a zero in the Link Partn er Au to-N eg oti ati on Ab le b it once the Auto-Negotiat io n Compl ete b it i s s et. I f co nfi gure d for parallel detect mode and any condition other than a sin gle good link occurs then the parallel detect fault bit will be set.

2.2.5 Enabling Auto-Negotiation via Software

It is important to not e that i f the DP 8384 9IF has been initia lized upon power-up as a non-auto-negotiating device (forced technology), and it is then requ ire d that Auto-Negotiation or re-Auto-Negotiation be initiated via software,

12 (Auto-Negotiation Enable) of the Basic Mode Control

bit Register (BMCR) must first be cleared and then set for any Auto-Negotiation function to take effect.

2.2.6 Auto-Negotiation Complete Time

Parallel detection and Auto-Negotiation take approximately 2-3 seconds to co mp let e. In addition, Auto-Negotia tio n wi th next page should take approximately 2-3 seconds to com plete, depending on the number of next pages sent.

Refer to Clause 28 of the IEEE 802.3u standard for a full description of the individual timers related to Auto-Negotiation.

2.3 Auto-MDIX

When enabled, this function utilizes Auto-Negotiation to determine the proper configuration for transmission and reception of data and subsequently selects the appropriate MDI pair for MD I/ MD IX o pe ra ti on. T h e fu nc t io n us es a r an dom seed to control switching of the crossover circuitry.

DP83849IF

2.2.4 Auto-Negotiation Rest art

Once Auto-Negotiation has completed, it may be restarted at any time by setting bit 9 (Res tart Auto- Negotiat ion) of th e BMCR to one. If the mode confi gured b y a su cces sful Au toNegotiation loses a valid link, then the Auto-Negotiation process will resume and attempt to determine the configu ration for the link. This function ensures that a valid configuration is maintained if the cable becomes disconnected.

A renegotiation requ es t fro m any en tity, such as a management agent, wi ll cause th e DP83849I F to halt any tr ansmit data and link pulse activity until the break_link_timer expires (~1500 ms). Consequently, the Link Partner will go into link fail and normal Auto-Negotiation resumes. The DP83849IF will resume Auto-Negotiation after the break_link_timer has expired by issuing FLP (Fast Link Pulse) bursts.

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MDIO bus in a system must have a unique physical address.

The DP83849IF supports PHY Address strapping of Port A to even values 0 (<0000_0>) through 30 (<1111_0>). Port B is strapped to odd values 1 (<0000_1>) through 31 (<1111_1>). Note that Port B address is always 1 greater than Port A address.

For further detail rela ting to the la tch -in timi ng requi rement s of the PHY Address pins, as well as the other hardware configuration pins, refer to the Reset summary in Section 6.0.

Refer to Figure 2 for an exam ple o f a PH YAD connection to external components. In this example, the PHYAD strapping results in address 00010 (02h) for Port A and address 00011 (03h) for Port B.

DP83849IF

2.4.1 MII Isolate Mode

The DP83849IF can be put into MII Isolate mode by writing to bit 10 of the BMCR register.

When in the MII isolate mode, the DP83849IF does not respond to packet data present at TXD[3:0], TX_EN inputs and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When in Isolate mode, the DP83849IF will continue to respond to all management transactions.

While in Isolate mod e, th e PM D ou tput pair will not transm it packet data but will continue to source 100BASE-TX scrambled idles or 10BASE-T normal link pulses.

The DP83849IF can Auto-Negotiate or parallel detect to a specific technology depending on the receive signal at the PMD input pair. A valid link can be established for the receiver even when the DP83849IF is in Isolate mode.

RXD1_B

PHYAD4= 0

RXD0_B

Figure 2. PHYAD Strapping Example

RXD1_A

PHYAD2 = 0PHY AD3 = 0

RXD0_A

PHYAD1 = 1

2.2kΩ

VCC

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2.5 LED Interface

The DP83849IF supports three configurable Light Emitting Diode (LED) pins for each port.

Several functions can be multiplexed onto the three LEDs using three different modes of operation. The LED operation mode can be selected by writing to the LED_CFG[1:0]

register bits in the PHY Control Register (PHYCR) at address 19h, bits [6:5]. In addition, LED_CFG[0] for each port can be set by a strap option on the CRS_A and CRS_B pins. LED_CFG[1] is only controllable through reg ister access and cannot be set by as strap pin.

See Table 3 for LED Mode selection.

DP83849IF

The LED_LINK pin in Mode 1 indicates the link status of the port. In 100BASE-T mode, link is established as a result of input receive amplitude compliant with the TPPMD specifications which will result in internal generation of signal detect. A 10 Mb/s Link is est abli shed as a result of the reception of at least seven consecutive normal Link Pulses or the reception of a valid 10BASE-T packet. This will cause the as sertion of LED_LINK. L ED _LIN K w il l d ea s sert in accordance with the Link Loss Timer as specified in the IEEE 802.3 specification.

The LED_LINK p in in Mode 1 w i ll be O FF w h en no LI N K is present.

The LED_LINK pin in Mode 2 and Mode 3 will be ON to indicate Link is good and BLINK to indicate activity is present on activity. The BLINK frequency is defined in BLINK_FREQ, bits [7:6] of register LEDCR (18h).

Activity is defined as configured in LEDACT_RX, bit 8 of register LEDCR (18h). If LEDACT_RX is 0, Activity is sig naled for either transmit or receive. If LEDACT_RX is 1, Activity is only signaled for receive.

The LED_SPEED pin indicates 10 or 100 Mb/s data rate of the port. The LED is ON when operating in 100Mb/s mode and OFF when operating in 10Mb/s mode. The functional ity of this LED is independent of mode selected.

The LED_ACT/LED_COL pin in Mo de 1 ind ic ates the pre sence of either transmit or receive activity. The LED will be ON for Activity and OFF for No Activity. In Mode 2, this pin indicates the Collision status of the port. The LED will be ON for Collision and OFF for No Collision.

The LED_ACT/LED_COL pin in Mode 3 indicates Duplex status for 10 Mb/s or 100 Mb/s operation. The LED will be ON for Full Duplex and OFF for Half Duplex.

In 10 Mb/s half duplex mode, the collision LED is based on the COL signal.

Since these LED pins are also used as strap options, the polarity of the LED is dependent on whether the pin is pulled up or down.

2.5.1 LEDs

Since the Auto-Negotiation (AN) strap options share the LED output pins, the external components required for strapping and LED usage must be considered in order to avoid contention.

Specifically, when the LED outputs are used to drive LEDs directly, the active state of each output driver is dependent on the logic level sampled by the corresponding AN input upon power-up/reset. For example, if a given AN input is resistively pulled low then the corresponding output will be configured as an active high driver. Conversely, if a given AN input is.4( w)5ee ss.tsv4( w)5 y10.2( su)12.8(tlle12.8(d c)12.8(ei-1.12(g)12.8(e,th)12.8(e )13.3(the))13.3(tc)12.8(nres)10.32po)n12.8(d in12.8(dg-0.5(s)]TJT*0.0033 Tc-0.0013 Tw[(tu)12.96tpu)13.96tp1.63 w)5.63ig.l-1.4(gb)12.96esguas.o-0.47 w45

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LED_ACT/LED_COL_A

AN_EN_A = 0

2.2kΩ 165Ω

GND

Figure 3. AN Strapping and LED Loading Example

2.5.2 LED Direct Control

The DP83849IF provides another option to directly control any or all LED outputs throu gh the LED Di rect Contro l Reg ister (LEDCR), address 18h. The register does not provide read access to LEDs.

LED_SPEED_A

AN1_A = 1

165Ω

LED_LINK_A

AN0_A = 1

165Ω

VCC

2.6 Half Duplex vs. Full Duplex

The DP83849IF supports both half and full duplex operation at both 10 Mb/s and 100 Mb/s speeds.

Half-duplex relies on the C SMA/C D protoc ol t o handl e colli sions and network access. In Half-Duplex mode, CRS responds to both transmit and receive activity in order to maintain compliance with the IEEE 802.3 specification.

Since the DP83849IF is designed to support simultaneous transmit and receiv e act ivi ty it is capabl e of su ppor tin g full duplex switched ap pli ca tio ns with a throughput of up to 200 Mb/s per port when operating in either 100BASE-TX or 100BASE-FX. Because the CSMA/CD protocol does not apply to full-duplex operation, the DP83849IF disables its own internal collision sensing and reporting functions and modifies th e behavior of Carr ier Sense (CRS ) such that it indicates only receive activity. This allows a full-duplex capable MAC to operate properly.

All modes of operation (100BASE-TX, 100BASE-FX, 10BASE-T) can run either half-duplex or full-duplex. Addi tionally, other than CRS and Collision reporting, all remaining MII signaling remains the same regardless of the selected duplex mode.

It is important to understand that while Auto-Negotiation with the use of Fast Link Pulse code words can interpret and configure to full-duplex operation, parallel detection can not recognize the difference between full and halfduplex from a fixed 10 Mb/s or 100 Mb/s link partner over twisted pair. As specified in the 802.3u specification, if a far-end link partner is configured to a forced full duplex 100BASE-TX ability, the parallel detection state machine in the partner would be unable to detect the full duplex capa bility of the far-end link partner. This link segment would negotiate to a half duplex 100BASE-TX configuration (same scenario for 10Mb/s).

Auto-Negotiation is not supported in 100BASE-FX operation. Selection of Half o r Ful l-du ple x o pera tio n is co ntrolled by bit 8 of the Basic Mode Control Register (BMCR), address 00h. If 100BASE-FX mode is strapped using the FX_EN pin, the AN0 strap value is used to set the value of bit 8 of the BMCR (00h) register. Note that the other AutoNegotiation strap pins (AN_EN and AN1) are ignored in 100BASE-FX mode.

2.7 Internal Loopback

The DP83849IF includes a Loopback Test mode for facilitating system diagnostics. The Loopback mode is selected through bit 14 (Loopback) of the Basic Mode Control Reg ister (BMCR). Writing 1 to this bit enables MII transmit data to be routed to the MII receive outputs. Loopback status may be checked in bit 3 of the PHY Status Register (PHYSTS). While in Loopback mode the data will not be transmitted onto the media. To ensure that the desired operating mode is maintained, Auto-Negotiation should be disabled before selecting the Loopback mode.

2.8 BIST

The DP83849IF incorporates an internal Built-in Self Test (BIST) circuit to accommodate in-circuit testing or diagnostics. The BIST circuit can be utilized to test the integrity of the transmit and receive data paths. BIST testing can be performed with the part in the internal loopback mode or externally looped back using a loopback cable fixture.

The BIST is implemented with independent transmit and receive paths, with the tran sm it bl ock gene rati ng a con tin u ous stream of a pseudo random sequence. The user can select a 9 bit or 15 bit pseudo random sequence from the PSR_15 bit in the PHY Control Register (PHYCR). The received data is compared to the generated pseudo-ran dom data by the BIST Linear Feedback Shift Register (LFSR) to determine the BIST pass/fail status.

The pass/fail status of the BIST is stored in the BIST status bit in the PHYCR reg ister. The status bit defaults to 0 (BIST fail) and will transition on a successful comparison. If an error (mis-compare) occurs, the status bit is latched and is cleared upon a subsequent write to the Start/Stop bit.

For transmit VOD testing, the Packet BIST Continuous Mode can be used to allow continuous data transmission, setting BIST_CONT_MODE, bit 5, of CDCTRL1 (1Bh).

The number of BIST errors can be monitored through the BIST Error Count in the CDCTRL1 (1Bh), bits [15:8].

DP83849IF

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3.0 MAC Interface

The DP83849IF support s se veral m odes of op eration using the MII interface pins. The optio ns are defi ned in th e foll ow ing sections and include:

— MII Mode — RMII Mode — 10 Mb Serial Network Interface (SNI) — Single Clock MII Mode (SCMII) In addition, the DP83849IF supports the standard 802.3u

MII Serial Management Interface and a Flexible MII Port Assignment scheme.

The modes of operation can be selected by strap options or register control. For RMII mode, it is recommended to use the strap option, since it requires a 50 MHz clock instead of the normal 25 MHz.

In each of these modes, the IEEE 802.3 serial manage-

DP83849IF

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3.2 Reduced MII Interface

The DP83849IF incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII specification (rev1.2) from the RMII Consortium. This interface may be used to connect PHY devices to a MAC in 10/100 Mb/s systems using a reduced number of pins. In this mode, data is transferred 2-bits at a time using the 50 MHz RMII_REF clock for both transmit and receive. The follow ing pins are used in RMII mode:

—TX_EN —TXD[1:0] — RX_ER (optional for Mac) — CRS_DV — RXD[1:0] — X1 (RMII Reference clock is 50 MHz) In addition, the RMII mode supplies an RX_DV signal

which allows for a simpler method of recovering receive data without having to separate RX_DV from the CRS_DV indication. This is especially useful for diagnostic testing where it may be desirable to externally loop Receive MII data directly to the transmitter.

The RX_ER output may be used by the MAC to detect error conditions. It is asserted for symbol errors received during a pack et, False Carrier even ts, and also for FIFO underrun or overrun conditions. Since the Phy is required to corrupt receive data on an error, a MAC is not required to use RX_ER.

It is important to note that since both digital channels in the DP83849IF share the X1/RMII_REF input, both channels must have RMII mod e enabled or both chann el s m us t hav e

Table 4. Supported packet sizes at +/-50ppm frequency accuracy

RMII mode disabled. Either channel may be in 10Mb or 100Mb mode in RMII or non-RMII mode.

Since the reference clock operates at 10 times the data rate for 10 Mb/s operation, transmit data is sampled every 10 clocks. Likewise, receive data will be generated every 10th clock so that an attached device can sample the data every 10 clocks.

RMII mode requires a 50 MHz oscillator be connected to the device X1 pin. A 50 MHz crystal is not supported.

To tolerate potential frequency differences between the 50 MHz reference clock and the recovered receive clock, the receive RMII function includes a programmable elasticity buffer. The elasticity buffer is programmable to minimize propagation delay based on expected packet size and clock accuracy. This allows for supporting a range of packet sizes including jumbo frames.

The elasticity buffer will force Frame Check Sequence errors for packets which overrun or underrun the FIFO. Underrun and Overrun conditions can be reported in the RMII and Bypass Register (RBR). The following table indi cates how to program the elastic ity buf fer fifo (in 4-bit increments) based on expected max packet size and clock accuracy. It assumes both clocks (RMII Reference clock and far-end Transmitter clock) have the same accuracy.

Packet lengths can be scaled linearly based on accuracy (+/- 25ppm would allows packets twice as large). If the threshold setting must support both 10Mb and 100Mb operation, the setting should be made to support both speeds.

DP83849IF

Start Threshold

RBR[1:0]

01 (default) 2 bits 8 bits 2,400 bytes 9,600 bytes

10 6 bits 4 bits 7,200 bytes 4,800 bytes 11 10 bits 8 bits 12,000 bytes 9,600 bytes 00 14 bits 12 bits 16,800 bytes 14,400 bytes

Latency Tolerance Recommended Packet Size

at +/- 50ppm

100Mb 10Mb 100Mb 10Mb

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3.3 10 Mb Serial Network Interface (SNI)

The DP83849IF incorpor ate s a 10 M b Se rial Netw ork Int erface (SNI) which al lo ws a simple serial dat a in terface for 10 Mb only devices. This is also referred to as a 7-wire inter face. While there is no defined standard for this interface, it is based on early 10 Mb physical layer devices. Data is clocked serially at 10 MHz using separate transmit and receive paths. The following pins are used in SNI mode:

—TX_CLK —TX_EN —TXD[0] —RX_CLK —RXD[0] — CRS —COL

3.4 Single Clock MII Mode

Single Clock MII (SCMII) Mode allows MII operation using a single 25MHz reference clock. Normal MII Mode requires

three clocks, a reference clock for physical layer functions, a Transmit MII clock, and a Receive MII clock. Similar to RMII mode, Single Clock MII mode requires only the refer ence clock. In addition to reducing the number of pins required, this mode allows the attached MAC device to use only the reference clock domain. Since the DP83849IF has two ports, this actually reduces the number of clocks from 6 to 1. A/ C Timing re quir ements for SC MII op erat ion are similar to the RMII timing requirements.

For 10Mb operation, as in RMII mode, data is sampled and driven every 10 clocks si nce the refere nce clock is a t 10x the data rate.

Separate control bits allow enabling the Transmit and Receive Single Clock modes separately, allowing just transmit or receive to operate in this mode. Control of Sin gle Clock MII mode is through the RBR register.

Single Clock MII mode incorporates the use of the RMII elasticity buffer, which is required to tolerate potential fre quency differences between the 25MHz reference clock and the recovered receive clock. Settings for the Elasticity Buffer for SCMII mode are detailed in the following table.

DP83849IF

Table 5. Supported SCMII packet sizes at +/-50ppm frequency accuracy

Start Threshold

RBR[1:0]

01 (default) 4 bits 8 bits 4,000 bytes 9,600 bytes

10 4 bits 8 bits 4,000 bytes 9,600 bytes 11 12 bits 8 bits 9.600 bytes 9,600 bytes 00 12 bits 8 bits 9,600 bytes 9,600 bytes

Latency Tolerance Recommended Packet Size

at +/- 50ppm

100Mb 10Mb 100Mb 10Mb

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3.5 Flexible MII Port Assignment

The DP83849IF supports a flexible assignment scheme for each of the channels to the MII/RMII interface. Either of the MII ports may be assigned to the internal channels A/B. These values are contro lled by th e RMII and Bypas s Reg ister (RBR), address 17h. Transmit assignments and Receive assignments can be made separately to allow even more flexibility (i.e. both channels could transmit from MII A while still allowing separate receive paths for the channels).

MII

Port

MII

Port

In addition, the opposite receive channel may be used as the transmit source for each channel. As shown in Figure 4, Channel A receive data may be used as the Channel B transmit data source while Channel B receive data may be used as the Channel A transmit data source. For proper clock synchronization, this function requires the device be in RMII m ode or Single Clock MII mode of opera tion. A configuration strap is provided on pin 56, RXD2_B/EXTENDER_EN to enable this mode.

Channel A

Channel B

DP83849IF

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3.5.1 RX MII Port Mapping

Note that Channel A is the master of MII Port A, and Channel B is the master of MII Port B. This means that in order for Channel B to control MII Port A, Channel A must be configured t o either co ntrol MII Po rt B or be Disa bled; the reverse is also true.

Table 6. RX MII Port Mapping Controls

RBR[12:11] Desired RX Channel Destination

00 Normal Port 01 Opposite Port 10 Both Ports 11 Disabled

Table 7. RX MII Port Mapping Configurations

Channel A RBR[12:11] Chan nel B RBR[12:11] RX MII Port A Source RX MII Port B Source

00 00 Channel A Channel B

RX MII Port Mapping controls and configurations are shown in the following tables:

DP83849IF

00 01 Channel A Channel B 00 10 Channel A Channel B 00 11 Channel A Disabled 01 00 Channel A Channel B 01 01 Channel B Channel A 01 10 Channel B Channel A 01 11 Disabled Channel A 10 00 Channel A Channel B 10 01 Channel B Channel A 10 10 Channel A Channel B 10 11 Channel A Channel A 11 00 Disabled Channel B 11 01 Channel B Disabled 11 10 Channel B Channel B 11 11 Disabled Disabled

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3.5.2 TX MII Port Mapping

TX MII Port Mapping controls and configurations are shown in the following ta bles:

Table 8. TX MII Port Mapping Controls

RBR[10:9] TX Channel Source

00 Normal Port 01 Opposite Port 10 Opposite RX Port 11 Disabled

Table 9. TX MII Port Mapping Configurations

Channel A RBR[10:9] Port A TX Source Channel B RBR[10:9] Port B TX Source

00 MII Port A 00 MII Port B 01 MII Port B 01 MII Port A

DP83849IF

10 RX Channel B 10 RX Channel A 11 Disabled 11 Disabled

3.5.3 Common Flexible MII Port Configurations

Table 10. Common Flexible MII Port Configurations

Mode Channel A

RBR[12:9]

Normal 0000 0000 MII port A assigned to Channel A, MII

Full Port Swap 0101 0101 MII port A assigned to Channel B, MII

Extender/Media Converter 1110 1110 MII RX disabled, Channel A transmits

Broadcast TX MII Port A xx00 xx01 Both Channels transmit from TX MII

Broadcast TX MII Port B xx01 xx00 Both Channels transmit from TX MII

Channel B RBR[12:9]

Description

Port B assigned to Channel B

Port B assigned to Channel A

from Channel B RX data, Channel B

transmits from Channel A RX data

Port A

Port B

Mirror RX Channel A 10xx 11xx Channel A RX traffic appears on both

Ports.

Mirror RX Channel B 11xx 10xx Channel B RX traffic appears on both

Disable Port A 1111 xxxx MII Port A is disabled Disable Port B xxxx 1111 MII Port B is disabled

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Ports.

3.5.4 Strapped Extender or Media Converter Mode

The DP83849IF provides a simple strap option to automatically configure both channels for Extender or Media Converter Mode with no device register configuration necessary. The EXTENDER_EN Strap can be used in conjunction with the Auto-Negotiation Straps (AN_EN, AN0, AN1), the RMII Mode Strap, and the Fiber Mode (FX_EN) Strap to allow many possible configurations. If

Table 11. Common Strapped Extender/Media Converter Mode Configurations

Mode Auto-Negotiation Straps Fiber Mode Straps

100Mb Copper Extender Both channels are forced to 100Mb Full Duplex Disabled for both channels

100Mb Fiber Extender N/A Enabled for both channels

10Mb Copper Extender Both channels are forced to 10Mb Full Duplex Disabled for both channels

100Mb Media Converter One channel is forced to 100Mb Full Duplex Enabled for the other channel

3.5.5 Notes and Restrictions

— Extender/Media Converter: Both chann els must be op-

erating at the same speed (10 or 100Mb). This can be accomplished us ing s traps or c hannel regis ter c ontrols . Both channels must be in Full Duplex mode. Both chan nels must either be in R MII Mode (R BR:RMII_EN = 1) or full Single Clock MII Mode (RBR:SCMII_RX = 1 and RBR:SCMII_TX = 1) to ensure synchrono us operation. only one RX to TX path is ena bled, SCMII_RX in the RX channel (RBR register 17h bit 7) and SCMII_TX in the TX channel (RBR register 17h bit 6) must be set to 1. Media Conversion is only supported in 100Mb mode; one channel must be in Fiber Mode (100Base-FX) and the other channel must be in Copper Mode (100BaseTX).

— Broadcast TX MII Port Mode: To ensure sync hro nou s

operation, both channels must be in RMII Mode (RBR register 17h bit 5 = 1) or in Single Clock TX MII Mode (RBR register 17h bit 6 = 1). Both channels must be op erating at the same speed (10 or 100Mb). Both channels must be in Full Duplex mode to ensure no collisions are seen. This is because in Single Clock TX MII Mode, a collision on one PHY channel would cause both chan nels to send the Jam pattern.

— RMII Mode: Both Channels must have RMII Mode en-

abled or disabled concurrently due to the internal reference clocking scheme. In Full Port Swap Mode, Channels are not required to have a common speed.

— 10Base-T Serial M ode: This MAC-side mode, also

known as Serial Network Interface (SNI), may not be used when both channels share data connections (Ex tender/Media Converter or Broa dcast TX MII Port). This is due to the requirement of synchronous operation be tween channels, which is not supported in SNI Mode.

— CRS Assignment: When a channel is n ot in RMII Mode ,

its associated CRS pin is sourced from the transmitter

Extender Mode is strapped but RMII Mode is not, both channels will automatically be configured for Single Clock MII Receive and Transmit Modes. The optional use of RMII Mode in co njun cti on w ith E xte nde r Mode a llo ws f lexi bility in the system design.

Several common configurations are shown in Table 11.

and controlled by the TX MII Port Assignment, bits [10:9] of RBR (17h). When a channel is in RMII Mode, the as sociated CRS pin is sourced from the receiver and con-

trolled by the RX MII Port Assignment, bits [12:11] of RBR (17h).

— Output Enables: Flexible MII Port Assignment does not

control signal output enables.

— Test Modes: Test modes are not designed to be com-

patible with Flexible MII Port Selection, which assumes default MII pin directions.

— LED Assignment: LEDs are associated with their re-

spective digital channels, and therefore do not get mapped to alternate channels. For example, assertion of LED_LINK_A indicate s valid lin k status fo r Channel A independent of the MII Port Assignment.

— Straps: Strap pins are always associated with their re-

spective channel, i.e. a strap on RX_ER_A is used by

Channel A.

— Port Isolate Mode: Each MII port’s Isolate function, bit

10 of BMCR (00h) is always associated with its respec tive channel, i. e. the Isolat e func tion fo r Port A i s alwa ys controlled by Channel A’s BMCR (00h). Due to the var ious possible combi nation s of TX and RX po rt selectio n, it may not be advisable to place a port in Isolate mode.

— Energy Detect and Powerdown Modes: The output

enables for each MII port are alwa ys controlled b y the re spective channel Energy Detect and Powerdown functions. These functions shoul d be dis abled wh eneve r an MII port is in use b ut not ass igned to its defau lt chann el. Note that Extender/Media Converter modes allow the use of Energy Detect and Powerdown modes if the RX

MII ports are not in use.

DP83849IF

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3.6 802.3u MII Serial Management Interface

DP83849IF

3.6.1 Seri al Managemen t Register Access

The serial management MII specification defines a set of thirty-two 16-bit status and control registers that are acces

sible through the management interface pins MDC and MDIO. The DP83849IF im pleme nts all the requi red MII re g

isters as well as several optional registers. These registers are fully described in Section 7.0. A descri ption of the seria l management access protocol follows.

3.6.2 Serial Management Access Protocol

The serial co ntrol interface co nsists of two pins, Management Data Clock (MDC) and Management Data Input/Output (MDIO). MDC has a maximum clock rate of 25 MHz and no minimum rate. The MDIO line is bi-directional and may be shared by up to 32 devices. The MDIO frame for

mat is shown below in Table 12.

In addition, the MDIO pin requires a pull-up resistor (1.5

Ω) which, during IDLE and turnaround, will pull MDIO

k high. In order to initialize the MDIO interface, the station management entity sends a sequence of 32 contiguous logic ones on MDIO to provide the DP83849IF with a sequence that can be used to establish synchronization. This preamble may be generated either by driving MDIO high for 32 consecutive MDC clock cycles, or by simply allowing the MDIO p ull-up r esi stor to pull th e MDIO pin hig h during which time 32 MDC clock cycles are provided. In addition 32 MDC clock cycles should be used to re-sync the device if an invalid start, opcode, or turnaround bit is detected.

The DP83849IF waits until it has received this preamble sequence before responding to any other transaction. Once the DP83849IF serial manage ment port has be en ini

tialized no further preamble sequencing is required until after a power-on/reset, invalid Start, invalid Opcode, or invalid turnaround bit has occurred.

The St art co de is indicated by a <01> pattern. Th is assure s the MDIO line transitions from the default idle line state.

Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no device shall actively drive the MDIO signal during the first bit of Turnaround. The addressed DP83849IF dri ve s the MDI O with a zero for the second bit of turnaround and follows this with the required data.

Figure 5 shows the timing relationship between MDC and th e MDIO as dr iven/re ceiv ed by the Station (STA) and the DP83849IF (PHY) for a typical register read access .

For write transactions, the station management entity writes data to the addressed DP83849IF thus eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity by inserting <10>. Figure 6 shows the timing relationship for a typical MII register write access.

Table 12. Typical MDIO Frame Format

MII Management

Serial Protocol

Read Operation <idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle> Write Operation <idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>

MDC

MDIO

(STA)

MDIO

(PHY)

00011 110000000

Idle Start

Opcode

(Read)

PHY Address

(PHYAD = 0Ch)

(00h = BMCR)

0 0 011000100000000

Figure 5. Typical MDC/MDIO Read Operation

Idle

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MDC

DP83849IF

MDIO

(STA)

00011110000000

Idle Start

Opcode

(Write)

PHY Address

(PHYAD = 0Ch)

(00h = BMCR)

1000

Figure 6. Typical MDC/MDIO Write Operation

3.6.3 Serial Management Preamble Suppression

The DP83849IF supports a Preamble Suppression mode as indicated by a one in bit 6 of the Basic Mode Status Register (BMSR, address 01h.) If the station management entity (i.e. MAC or other management controller) deter

mines that all PHYs in the system support Preamble Suppression by returning a one in this bit, then the station management entity need not generate preamble for each management transaction.

The DP83849IF requires a single initialization sequence of 32 bits of preamble fol lo w ing hard ware/s oftware reset. This requirement is generally met by the mandatory pull-up resistor on MD I O in co nj unc ti o n wi th a co nt i nuo us MD C, or the management access made to determine whether Pre

amble Suppression is supported.

While the DP83849IF requires an initial preamble sequence of 32 bits for management initialization, it does not require

0 0 0 000 00000000

Idle

a full 32-bit sequence between each subsequent transaction. A minimum of one idle bit between management transactions is required as specified in the IEEE 802.3u specification.

3.6.4 Simultaneous Register Write

The DP83849IF inco rpo rates a m od e w hic h a llo w s sim ultaneous write access to both Port A and B register blocks at the same time. This mode is selected by setting bit 15 of RMII and By pass Register (RBR, address 17h) in Port A.

As long as this bit remains set, subsequent writes to Port A will write to registers in both ports.

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4.0 Architecture

This section describes the operations within each transceiver module, 100BASE-TX and 10BASE-T. Each operation consists of several functional blocks and described in the following:

— 100BASE-TX Transmitter — 100BASE-TX Receiver — 100BASE-FX Operation — 10BASE-T Transceiver Module

4.1 100BASE-TX TRANSMITTER

The 100BASE-TX transmitter consists of several functional blocks which conver t sy nchronous 4-bit ni bble d at a, as p ro vided by the MII, to a scrambled MLT-3 125 Mb/s serial data stream. Because the 100BASE-TX TP-PMD is inte grated, the differential output pins, PMD Output Pair, can be directly routed to the magnetics.

The block diagram in Figure 7. provides an overview of each functional block within the 100BASE-TX transmit section.

The Transmitter section consists of the following functional blocks:

— Code-group Encoder and Injection block — Scrambler block (bypass option) — NRZ to NRZI encoder block — Binary to MLT-3 converter / Common Driver The bypass option for the functional blocks within the

100BASE-TX transmitter provides flexibility for applications where data conversion is not always required. The DP83849IF implements the 100BASE-TX transmit state

machine diagram as specified in the IEEE 802.3u Stan dard, Clause 24.

DP83849IF

125MHZ CLOCK

BP_SCR

100BASE-TX

LOOPBACK

TX_CLK

DIVIDE

BY 5

MLT[1:0]

TXD[3:0] /

TX_EN

4B5B CODE-

GROUP

ENCODER &

5B PARALLEL

TO SERIAL

SCRAMBLER

MUX

NRZ TO NRZI

ENCODER

BINARY

TO MLT-3 /

COMMON

DRIVER

PMD OUTPUT PAIR

Figure 7. 100BASE-TX Transmit Block Diag ram

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Table 13. 4B5B Code-Group Encoding/Decoding

DATA CODES

0 11110 0000 1 01001 0001 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 A 10110 1010

B 10111 1011 C 11010 1100 D 11011 1101 E 11100 1110 F 11101 1111

IDLE AND CONTROL CODES

H 00100 HALT code-group - Error code

I 11111 Inter-Packet IDLE - 0000 (Note 1)

J 11000 First Start of Packet - 0101 (Note 1) K 10001 Second Start of Packet - 0101 (Note 1) T 01101 First End of Packet - 0000 (Note 1) R 00111 Second End of Packet - 0000 (Note 1)

INVALID CODES

V 00000 V 00001 V 00010 V 00011 V 00101 V 00110 V 01000 V 01100

Note: Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER asserted.

DP83849IF

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4.1.1 Code-group Encoding and Injection

The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups for transmission. This conversion is required to allow control data to be combined with packet data code-groups. Refer

Table 13 for 4B to 5B code-group mapping details.

to The code-group encoder substitutes the first 8-bits of the

MAC preamble with a J/K code-group pair (11000 10001) upon transmission. The code-group encoder continues to replace subsequent 4B preamble and data nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the deassertion of Transmit Enable signal from the MAC, the code-group encoder injects the T/R code-group pair (01101 00111) indicating the end of the frame.

After the T/R code-group pair, the code-group encoder continuously injects IDLEs into the transmit data stream until the next transmit packet is detected (reassertion of Transmit Enable).

4.1.2 Scrambler

The scrambler is required to control the radiated emissions at the media connector and on the twisted pair cable (for 100BASE-TX applications). By scrambling the data, the total energy launched onto the cable is randomly distrib uted over a wide frequency range. Without the scrambler, energy levels at the PMD and on the cable could peak beyond FCC limitations at frequencies related to repeating 5B sequences (i.e., continuous transmission of IDLEs).

The scrambler is configured as a closed loop linear feedback shift register (LFSR) with an 11-bit polynomial. The output of the closed loop LFSR is X-ORd with the serial NRZ data from the code-group encoder. The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at certain frequencies by as much as 20 dB. The DP83849IF uses the PHY_ID (pins PHYAD [4:1]) to set a unique seed value.

transmit transformer primary winding, resulting in a MLT-3 signal.

The 100BASE-TX MLT-3 signal sourced by the PMD Output Pair common driver is slew rate controlled. This should be considered when selecting AC coupling magnetics to ensure TP-PMD Standard compliant transition times (3 ns < Tr < 5 ns).

The 100BASE-TX transmit TP-PMD function within the DP83849IF is capable of sourcing only MLT-3 encoded data. Binary output from the PMD Output Pair is not possi ble in 100 Mb/s mode.

4.2 100BASE-TX RECEIVER

The 100BASE-TX receiver consists of several functional blocks which convert the scrambled MLT-3 125 Mb/s serial data stream to synchronous 4-bit nibble data that is pro vided to the MII. Because the 100BASE-TX TP-PMD is integrated, the differential input pins, RD±, can be di rectly routed from the AC coupling magnetics.

See Figure 8 for a block diagram of the 100BASE-TX receive function. This provides an overview of each functional block within the 100BASE-TX receive section.

The Receive section consists of the following functional blocks:

— Analog Front End — Digital Signal Processor — Signal Detect — MLT-3 to Binary Decoder — NRZI to NRZ Decoder — Serial to Parallel — Descrambler — Code Group Alignment —4B/5B Decoder — Link Integrity Monitor — Bad SSD Detection

DP83849IF

4.1.3 NRZ to NRZI Encoder

After the transmit data stream has been serialized and scrambled, the data must be NRZI encoded in order to comply with the TP-PMD standard for 100BASE-TX trans mission over Category-5 Unshielded twisted pair cable.

4.1.4 Binary to MLT-3 Convertor

The Binary to MLT-3 conversion is accomplished by converting the serial binary data stream output from the NRZI encoder into two binary data streams with alternately phased logic one events. These two binary streams are then fed to the twisted pa ir out put dri ve r whic h co nverts the voltage to current and alternately drives either side of the

4.2.1 Analog Front End

In addition to the Digital Equalization and Gain Control, the DP83849IF includes Analog Equalization and Gain Control in the Analog Front End. The Analog Equalization reduces the amount of Digital Equalization required in the DSP.

4.2.2 Digital Signal Processor

The Digital Signal Processor includes Adaptive Equalization with Gain Control and Base Line Wander Compensation.

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DP83849IF

RX_DV/CRS

RX_DATA VALID

SSD DETECT

RX_CLK RXD[3:0] / RX_ER

4B/5B DECODER

SERIAL TO

PARALLEL

CODE GROUP

ALIGNMENT

DESCRAMBLER

NRZI TO NRZ

DECODER

MLT - 3 TO BINARY

DECODER

LINK

INTEGRITY

MONITOR

SIGNAL

DETECT

DIGITAL

SIGNAL

PROCESSOR

ANALOG

FRONT

END

RD +/−

Figure 8. 100BASE-TX Receive Block Diagram

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4.2.2.1 Digital Adaptive Equaliza tion and Ga in Con tr ol

When transmitting data at high speeds over copper twisted pair cable, frequency dependent attenuation becomes a concern. In high-speed twisted pair signalling, the fre quency content of the transmitted signal can vary greatly during normal operation based primarily on the random ness of the scrambled data stream. This variation in signal attenuation caused by frequency variations must be com pensated to ensure the integrity of the transmission.

In order to ensure quality transmission when employing MLT-3 encoding, th e compensation must be able to ad apt to various cable lengths and cable types depending on the installed en vironment. The se lection of lo ng cable lengths for a given implementation, requires significant compensa tion which will over-compensate for shorter, less attenuating lengths. Conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. The compensation or equalization must be adap

tive to ensure proper conditioning of the received signal independent of the cable length.

The DP83849IF utilizes an extremely robust equalization scheme referred as ‘Digital Adaptive Equalization.’

The Digital Equalizer removes ISI (inter symbol interference) from the receive data stream by continuously adapting to provide a filter with the inverse frequency response of the channel. Equalization is combined with an adaptive gain control stage. This enables the receive 'eye pattern' to be opened sufficiently to allow very reliable data recovery.

The curves given in Figure 9 illustrate attenuation at ce rtai n frequencies for given cable lengths. This is derived from the worst case frequency vs. attenuation figures as speci fied in the EIA/TIA Bulletin TSB-36. These curves indicate the signific ant vari ations in signal at tenua tion that must be compensated f or by the receive adaptive equaliz ation cir cuit.

DP83849IF

Figure 9. EIA/TIA Attenuation vs. Frequency for 0 , 50,

100, 130 & 150 meters of CAT 5 cable

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4.2.2.2 Base Line Wander Compensation

DP83849IF

Figure 10. 100BASE-TX BLW Event

The DP83849IF is completely ANSI TP-PMD compliant and includes Base Line Wander (BLW) compensation. The BLW compensation block can succ e ssf ul ly re c over th e T PPMD defined “killer” pattern.

BLW can generally be defined as the change in the average DC content, relatively short period over time, of an AC coupled digital transmission over a given transmission medium. (i.e., copper wire).

BLW results from the interaction between the low frequency components of a transmitted bit stream and the frequency response of the AC coupling component(s) within the transmission system. If the low frequency content of the digital bit stream goes below the low frequency pole of the AC coupling transformers then the droop characteris tics of the transformers w ill do mi nate res ulting in potentially serious BLW.

The digital oscilloscope plot provided in Figure 10 illustrates the severity of the BLW event that can theoretically be generated during 100BASE-TX packet transmission. This event consists of approximately 800 mV of DC offset for a period of 120 µs. Left uncompensated, ev ent s suc h as this can cause packet loss.

4.2.3 Signal Detect

The signal detect function of the DP83849IF is incorporated to meet the specifications mandated by the ANSI

FDDI TP-PMD Standard as well as the IEEE 802.3 100BASE-TX S tandard for both volt age th res ho lds a nd tim ing parameters.

Note that the reception of normal 10BASE-T link pulses and fast link pulses per IEEE 802.3u Auto-Negotiation by the 100BASE-TX receiver do not cause the DP83849IF to assert signal detect.

4.2.4 MLT-3 to NRZI Decoder

The DP83849IF decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary NRZI data.

4.2.5 NRZI to NRZ

In a typical application, the NRZI to NRZ decoder is required in order to present NRZ formatted data to the descrambler.

4.2.6 Serial to Parallel

The 100BASE-TX receiver includes a Serial to Parallel converter which supplies 5-bit wide data symbols to the PCS Rx state machine.

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4.2.7 Descrambler

A serial descrambler is used to de-scramble the received NRZ data. The descrambler has to generate an identical data scrambling sequence (N) in order to recover the origi nal unscrambled data (UD) from the scrambled data (SD) as represented in the equations:

SD UD N⊕()= UD SD N⊕()=

Synchronization of the descrambler to the original scrambling sequence (N) is achieved based on the knowledge that the incoming scrambled data stream consists of scrambled IDLE data. After the descrambler has recog nized 12 consecutive IDLE code-groups, where an unscramble d IDLE code-group in 5B NRZ is equal to five consecutive one s (1111 1), it w ill synchron ize to the r eceive data stream and generate unscrambled data in the form of unaligned 5B code-groups .

In order to maintain synchronization, the descrambler must continuously monitor the validity of the unscrambled data that it generates. To ensure this, a line state monitor and a hold timer are used to constantly monitor the synchroniza tion status. Upon synchronization of the descrambler the hold timer star ts a 722 µs countdown. Upon detection of sufficient IDLE c ode -gro up s (58 b it tim es) with in th e 72 2 period, the hold timer will reset and begin a new count down. This monitoring operation will continue indefinitely given a properly operating network connection with good signal integrity. If the line state monitor does not recognize sufficient unscrambled ID LE code-groups within the 722 period, the entire descrambler will be forced out of the cur rent state of synchronization and reset in order to reacquire synchronization.

µs

DP83849IF

4.2.10 100BASE-TX Link Integrity Monitor

The 100 Base TX Lin k mon itor en sures that a v alid and st a ble link is established before enabling both the Transmit and Receive PCS layer.

Signal detect must be vali d for 395u s to allow the link monitor to enter the 'Lin k Up' state, and enable t he transmit and receive functions.

4.2.11 Bad SSD Detection

A Bad Start of Stream Delimiter (Bad SSD) is any transition from consecutive idle code-groups to non-idle code-groups which is not prefixed by the code-group pair /J/K.

If this condition is detected, the DP83849IF will assert RX_ER and present RXD[3:0] = 1110 to the MII for the cycles that correspond to received 5B code-groups until at least two IDLE code groups are detected. In addition, the False Carrier Sense Counter register (FCSCR) will be incremented by one.

Once at least tw o IDLE co de groups are detec ted, RX_ER and CRS become de-asserted.

4.3 100BASE-FX Operation

The DP83849IF provides IEEE 802.3 compliant 100BASEFX operation. Configuration of FX mode is via strap option, or through the register interface.

4.2.8 Code-group Alignment

The code-group alignment module operates on unaligned 5-bit data from the descrambler (or, if the descrambler is bypassed, directly from the NRZI/NRZ decoder) and con verts it into 5B code-group data (5 bits). Code-group alignment occurs after the J/K code-group pair is detected. Once the J/K code-group pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary.

4.2.9 4B/5B Decoder

The code-group decoder functions as a look up table that translates incoming 5B code-groups into 4B nibbles. The code-group decoder first detects the J/K code-group pair preceded by IDLE code-groups and replaces the J/K with MAC preamble. Specifically, the J/K 10-bit code-group pair is replaced by the nibble pair (0101 0101). All subsequent 5B code-groups are converted to the corresponding 4B nibbles for the duration of the entire packet. This conver sion ceases upon the detection of the T/R code-group pair denoting the End of Stream Delimiter (ESD) or with the reception of a minimum of two IDLE code-groups.

4.3.1 100BASE-FX Transmit

In 100BASE-FX mode, the device Transmit Pins conn ect to an industry standard Fiber Transceiver with PECL signalling through a capaciti ve ly co upl ed circuit.

In FX mode, the de vice bypasses the Scrambl er and the MLT3 encoder. This allows for the transmission of serial ized 5B4B encoded NRZI data at 125MHz.

The only added functionality from 100BASE-TX is the support for Far-End Fault data generation.

4.3.2 100BASE-FX Receive

In 100BASE-FX mode, the device Receive pins connect to an industry standard Fiber Transceiver with PECL signal ling through a capaciti ve ly co upl ed circuit.

In FX mode, the device bypasses MLT3 Decoder and the Descrambler. This allows for the reception of serialized 5B4B encoded NRZI data at 125MHz.

The only added functionality for 100BASE-FX from 100BASE-TX is the support of Far-End Fault detection.

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4.3.3 Far-End Fault

Since 100BASE-FX does not support Auto-Negotiation, a Far-End Fault facility is included which allows for detection of link failures.

When no signal is being received as determined by the Signal Detect function, the device sends a Far-End Fault indication to the far-end peer. The Far-En d Fa ult indication is comprised of 3 or more re peatin g cycl es, eac h consis ting of 84 one’s f ollowed by 1 ze ro. Th e pattern is such that i t will not satisfy the 100BASE-X carrier sense mechanism, but is easily detected as the Fault indication. The pattern will be transparent to devices that do not support Far-End Fault.

The Far-End Fault detect ion pro cess co ntinuo usly mon itors the receive data stream for the Far-End Fault indication. When detected, the Link Monitor is forced to deassert Link status. This causes the device to transmit IDLE’s on its transmit path.

4.4 10BASE-T TRANSCEIVER MODULE

The 10BASE-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision, heartbeat, loopback, jabber, and link integrity functions, as defined in the standard. An external filter is not required on the 10BASE-T interface since this is integrated inside the DP83849IF. This section focuses on the general 10BASET system level operation.

4.4.1 Operational Modes

The DP83849IF has two basic 10BASE-T operational modes:

— Half Duplex mode — Full Duplex mode

Full Dupl ex Mode

In Full Duplex mode the DP83849IF is capable of simultaneously transmitting and receiving without asserting the collision signal. The DP83849IF's 10 Mb/s ENDEC is designed to encode and decode simultaneously.

4.4.2 Smart Squelch

The smart squelch is responsible for determining when valid data is present on the differential receive inputs. The DP83849IF implements an intelligent receive squelch to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. Smart squelch operation is independent of the 10BASE-T operational mode.

The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10BSE-T standard) to determine the validity of data on the twisted pair inputs (refer to

The signal at the start of a packet is checked by the smart squelch and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch level is overcome cor rectly, the opposite squelch level must then be exceeded within 150 ns. Finally the signal must again exceed the original squelch level within 150 ns to ensure that the input waveform will not be rejected. This checking procedure results in the loss of typically three preamble bits at the beginning of each packet.

Only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder of the circuitry that valid data is present. At this time, the smart squelch circuitry is reset.

Valid data is considered to be present until the squelch level has not been generated for a time longer than 150 ns, indicating the End of Packet. Once good data has been detected, the squelch levels are reduced to minimize the effect of noise causing premature End of Packet detection.

Figure 11).

DP83849IF

Half Duplex Mode

In Half Duplex mode the DP83849IF functions as a standard IEEE 802.3 10BASE-T transceiver supporting the CSMA/CD protocol.

SQ+(reduced)

SQ-(reduced)

<150 ns

SQ+

SQ-

<150 ns

start of packet

Figure 11. 10BASE-T Twisted Pair Smart Squelch Operation

>150 ns

end of packet

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4.4.3 Collision Detection and SQE

When in Half Duplex, a 10BASE-T collision is detected when the receive and transmit channels are active simulta neously. Collisions are reported by the COL signal on the MII. Collisions are also reported when a jabber condition is detected.

The COL signal remai ns set for the d uration of the c ollis ion. If the PHY is receiving when a collision is detected it is reported immediately (through the COL pin).

When heartbeat is enabled, approximately 1 µs after the transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10-bit times is generated to indi cate successful transmission. SQE is reported as a pulse on the COL signal of the MII.

The SQE test is inhibited when the PHY is set in full duplex mode. SQE can also be inhibited by setting the HEARTBEAT_DIS bit in the 10BTSCR register.

4.4.4 Carrier Sense

Carrier Sense (CRS) may be as ser t ed d ue to rec eiv e activity once valid data is detected via the squelch function.

For 10 Mb/s Half Duplex operation, CRS is asserted during either packet transmission or reception.

For 10 Mb/s Full Duplex operation, CRS is asserted only during receive activity.

CRS is deasserted following an end of packet.

4.4.5 Normal Link Pulse Detection/Generation

The link pulse generator produces pulses as defined in the IEEE 802.3 10BASE-T standard. Each link pulse is nominally 100 ns in duration and transmitted every 16 ms in the absence of transmit data.

Link pulses are used to check the integrity of the connection with the remote end. If valid link pulses are not received, the link detector disables the 10BASE-T twisted pair transmitter, receiver and collision detection functions.

When the link integrity function is disabled (FORCE_LINK_10 of the 10 BTSC R re gis te r), a g ood link is forced and the 10BASE-T transceiver will operate regard less of the presence of link pulses.

Once disabled by the Jabber function, the transmitter stays disabled for the entire time that the ENDEC module's inter nal transmit enable is asserted. This signal has to be deasserted for approximately 500 ms (the “unjab” time) before the Jabber function re-enables the transmit outputs.

The Jabber function is only relevant in 10BASE-T mode.

4.4.7 Automatic Link Polarity Detection and Correcti on

The DP83849IF's 10BASE-T transceiver module incorporates an automatic link polarity detection circuit. When three consecutive inverted link pulses are received, bad polarity is reported.

A polarity reversal can be c aus ed by a wi ring error at eith er end of the cable, usually at the Main Distribution Frame (MDF) or patc h panel in the wiring closet.

The bad polarity conditi on is la tched in the 10BT SCR regis ter. The DP83849IF's 10BASE-T transceiver module corrects for this error internally and will continue to decode received data correctly. This eliminates the need to correct the wiring error immediately.

4.4.8 Transmit and Receive Filtering

External 10BASE-T filters are not required when using the DP83849IF, as the required signal conditioning is inte grated into the device.

Only isolation transformers and impedance matching resistors are required for the 10BASE-T transmit and receive interface. The internal transmit filtering ensures that all the harmonics in the transmit signal are attenuated by at least 30 dB.

4.4.9 Transmitter

The encoder begins operation when the Transmit Enable input (TX_EN) goes high and converts NRZ data to preemphasized Manchester data for the transceiver. For the duration of TX_EN, the serialized Transmit Data (TXD) is encoded for the transmit-driver pair (PMD Output Pair). TXD must be valid on the rising edge of Transmit Clock (TX_CLK). Transmission ends when TX_EN deasserts. The last transition is always positive; it occurs at the center of the bit cell if the last bit is a one, or at the end of the bit cell if the last bit is a zero.

DP83849IF

4.4.6 Jabber Function

The jabber function monitors the DP83849IF's output and disables the transmitte r if it attempts to transmit a pac ket of longer than legal siz e. A ja bbe r timer monitors the transm it ter and disables the transmission if the transmitter is active for approximately 85 ms.

4.4.10 Receiver

The decoder detect s the en d of a fra me when n o add iti ona l mid-bit transitions are detected. Within one and a half bit

times after the last bit, carrier sense is de-asserted. Receive clock st ay s a cti ve for fi ve mo re bi t tim es after CRS goes low, to guarantee the receive timings of the controller.

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5.0 Design Guidelines

DP83849IF

5.1 TPI Network Circuit

Figure 12 shows the recommended circuit for a 10/100 Mb/s twisted pair interface.

TPRDM

TDRDP

TPTDM

49.9Ω

49.9

49.9Ω

Ω

Vdd

0.1µF

Vdd

Below is a partial list of recommended transformers. It is important that the user realiz e that va riat ion s with PC B and component characteristics requires that the application be tested to ensure that the circuit meets the requirements of the intended application.

Pulse H1102 Pulse H2019 Belfuse S558-5999-U7

Halo TG110-S050N2RL

Vdd

COMMON MODE CHOKES

MAY BE REQUIRED.

1:1

0.1µF*

0.1µF* 1:1

RDRD+

TDTD+

RJ45

49.9

Ω

TPTDP

PLACE RESISTORS AND CAPACITORS CLOSE TO

THE DEVICE.

0.1µF

NOTE: CENTER TAP IS PULLED TO VDD

*PLACE CAPACITORS CLOSE TO THE

TRANSFORMER CENTER TAPS

All values are typical and are +/- 1%

Figure 12. 10/100 Mb/s Twisted Pair Interface

41 www.national.com

5.2 Fiber Network Circuit

Figure 13 shows the recommended circuit for a 100 Mb/s fiber pair interface.

Vdd

DP83849IF

FXTDP

FXTDM

FXSD

FXRDP FXRDM

130

Ω

130

Ω

0.1 uF

130

Ω

130

Ω

Fiber Transceiver

Ω

PLACE RESISTORS AND CAPACITORS CLOSE TO

THE DEVICE.

All values are typical and are +/- 1%

Figure 13. 100 Mb/s Fiber Pair Interface

PLACE RESISTORS

CLOSE TO THE FIBER

TRANSCEIVER.

42 www.national.com

5.3 ESD Protection

Typically, ESD precautions are predominantly in effect when handling the devices or board before being installed in a system. In those cases, strict handling procedures need be implemented during the manufacturing process to greatly reduce the occurrences of catastrophic ESD events. After the system is assembled, internal compo

nents are less sensitive from ESD events. The network interface pins are more susceptible to ESD

events.

5.4 Clock In (X1) Requirements

The DP83849IF sup port s an e xterna l CMOS l evel oscil lator source or a crystal resonator device.

cal connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads.

The oscillator circuit is designed to drive a parallel resonance AT cut crystal with a minimum drive level of 100µW and a maximum of 500

µW. If a crystal is specified for a lower drive level, a current limiting resistor should be placed in series between X2 and the crystal.

As a starting p oint fo r evalu ating an oscilla tor circ uit, if t he requirements for the crystal are not known, C should be set at 33 pF, and R1 should be set at 0Ω.

and C

Specification for 25 MHz crystal are listed in Table 16.

DP83849IF

Oscillator

If an external clock sour ce i s us ed, X1 sho uld be ti ed to the clock source and X2 should be left floating.

Specifications for CMOS oscillators: 25 MHz in MII Mode and 50 MHz in RM II Mode are l isted in

15.

Table 14 and Table

Note: Maximum Reference Clock Jitter should not exceed 1ns peak-to-peak or 78ps rms from 50kHz to 1MHz.

Figure 14. Crystal Oscillator Circuit

Crystal

A 25 MHz, parallel, 20 pF load crystal resonator should be used if a crystal source is desired.

Figure 14 shows a typi-

Table 14. 25 MHz Oscillator Specification

Parameter Min Typ Max Units Condition

Frequency 25 MHz Frequency

Tolerance

Frequency

+50 ppm Operational Tempera-

ture

+50 ppm 1 year aging

Stability

Rise / Fall Time 6 nsec 20% - 80%

Jitter (short term) 50 psec Cycle-to-cycle

Jitter (long term) 1 nsec Accumulative over 10µs

Symmetry 40% 60% Duty Cycle

Table 15. 50 MHz Oscillator Specification

Parameter Min Typ Max Units Condition

Frequency 50 MHz Frequency

+50 ppm Operational Temperature

Tolerance

Frequency

+50 ppm Operational Temperature

Stability

Rise / Fall Time 6 nsec 20% - 80%

Jitter (short term) 50 psec Cycle-to-cycle

Jitter (long term) 1 nsec Accumulative over 10µs

Symmetry 40% 60% Duty Cycle

43 www.national.com

Table 16. 25 MHz Crystal Specification

Parameter Min Typ Max Units Condition

Frequency 25 MHz Frequency

Tolerance

Frequency

Stability

Load Capacitance 25 40 pF

+50 ppm Operational Temperature

+50 ppm 1 year aging

5.5 Power Feedback Circuit

To ensure correct operation for the DP83849IF, parallel caps with values of 10 close to pin 31 (PFBOUT) of the device. Pin 7 (PFBIN1), pin 28 (PFBIN2), pin 34 (PFBIN3) and pin 54 (PFBIN4) must be connected to pin 31 (PFBOUT), each pin requires a small capacitor (.1 connections.

µF and 0.1 µF should be placed

µF). See Figure 15 below for proper

Pin 31 (

PFBOUT

)

DP83849IF

Pin 7 (PFBIN1)

Pin 28 (PFBIN2)

Pin 34 (PFBIN3)

Pin 54 (PFBIN4)

.1 µF

Figure 15. Power Feeback Connection

.1 µF

5.6 Power Down/Interrupt

The Power Down and Interrupt functions are multiplexed on pin 18 and pin 44 of the device. By default, this pin func tions as a power down input and the interrupt function is disabled. Setting bit 0 (INT_OE) of MICR (11h) will configure the pin as an active low interrupt output. Ports A and B can be powered down individually, using the separate PWRDOWN_INT_A and PWRDOWN_INT_B pins.

10 µF

.1 µF

bit 11 (Power Down) in the Basic Mode Control Register, BMCR (00h). An external control signal can be used to drive the pin low, overcoming the weak internal pull-up resistor. Alternatively, the device can be configured to ini tialize into a Power Down state by use of an external pulldown resistor on the PWRDOWN_INT pin. Since the device will still respond to management register accesses, setting the INT_OE bit in the MICR register will disable the PWRDOWN_INT input, allowing the device to exit the Power Down state.

.1 µF

5.6.1 Power Down Control M ode

The PWRDOWN _INT pins can be ass erted low to put the device in a Power Down m od e. Th is i s eq uiv al ent to setting

44 www.national.com

5.6.2 Interrupt Mechanisms

Since each port has a separate interrupt pin, the interrupts can be connected individually or may be combined in a wired-OR fashion. If the interrupts share a single connec tion, each port status should be checked following an interrupt.

The interrupt function is controlled via register access. All interrupt sources are disabled by default. Setting bit 1 (INTEN) of MICR (11h) will enable interrupts to be output, dependent on the interrupt mask set in the lower byte of the MISR (12h). The PWRDOWN_INT pin is asynchro nously asserted low when an interrupt condition occurs. The source of the interrupt can be determined by reading the upper byte of the MISR. One or more bits in the MISR will be set, denoting all currently pending interrupts. Read ing of the MISR clears ALL pending interrupts.

Example: To generate an interrupt on a change of link status or on a change of energy detect power state, the steps would be:

— Write 0003h to MICR to set INTEN and INT_OE — Write 0060h to MISR to set ED_INT_EN and

LINK_INT_EN

— Monitor PWRDOWN_INT pin

When PWRDOWN_INT pin asserts low, the user would read the MISR register to see if the ED_INT or LINK_INT bits are set, i.e. which source caused the interrupt. After reading the MISR, the interrupt bits should clear and the PWRDOWN_INT pin will deassert.

5.7 Energy Detect Mode

When Energy Detect is enabled and there is no activity on the cable, the DP83849IF will remain in a low power mode while monitoring the transmission line. Activity on the line will cause the DP83849IF to go through a normal power up sequence. Regardless of cable activity, the DP83849IF will occasionally wake up the transmitter to put ED pulses on the line, but will otherwise draw as little power as possible. Energy detect functionality is controlled via register Energy Detect Control (EDCR), address 1Dh.

5.8 Link Diagnostic Capabilities

The DP83849IF contains several system diagnostic capabilities for evaluating link quality and detecting potential cabling faults in Twisted Pair cabling. Software configura tion is available through the Link Diagnostics Registers Page 2 which can be selected via Page Select Register (PAGESEL), address 13h. These capabilities include:

— Linked Cable Status — Link Quality Monitor — TDR (Time Domain Reflectometry) Cable Diagnostics

5.8.1 Linked Cable Status

In an active conne ction wi th a valid link s tatu s, the f ollow ing diagnostic capabilities are available:

— Polarity reversal — Cable swap (MDI vs MDIX) detection — 100Mb Cable Length Estimation — Frequency offset relative to link partner — Cable Signal Quality Estimation

5.8.1.1 Polarity Reversal

The DP83849IF detects polarity reversal by detecting negative link pulses. The Polarity indication is available in bit 12 of the PHYSTS (10h) or bit 4 of the 10BTSCR (1Ah). Inverted polarity indicates the positive and negative con ductors in the receive pair are swapped. Since polarity is corrected by the receiver, this does not necessarily indicate a functional problem in the cable.

Since the polarity indication is dependent on link pulses from the link partner, polarity indication is only valid in 10Mb modes of operation, or in 100Mb Auto-Negotiated mode. Polarity indication is not available in 100Mb forced mode of operation or in a parallel detected 100Mb mode.

5.8.1.2 Cable Swap Indication

As part of Auto-Negotiation, the DP83849IF has the ability (using Auto-MDIX) to automatically detect a cable with swapped MDI pairs and select the appropriate pairs for transmitting and receiving data. Normal operation is termed MDI, while crossed operation is MDIX. The MDIX status can be read from bit 14 of the PHYSTS (10h).

5.8.1.3 100MB Cable Length Estimation

The DP83849IF provides a method of estimating cable length based on electrical characteristics of the 100Mb Link. This essentially provides an effective cable length rather than a measurement of the physical cable length. The cable length estimation is only available in 100Mb mode of operation with a valid Link status. The cable length estimation is available at the Link Diagnostics Reg isters - Page 2, register 100Mb Length Detect (LEN100_DET), address 14h.

5.8.1.4 Frequency Offset Relative to Link Partner

As part of the 100Mb clock recovery process, the DSP implementation provides a frequency control parameter. This value may be used to indicate the frequency offset of the device relative to the lin k p artner. This operation is only available in 100Mb operation with a valid link status. The frequency offset can be determined using the register 100Mb Frequency Offset Indication (FREQ100), address 15h, of the Link Diagnostics Registers - Page 2.

Two different versions of the Frequency Offset may be monitored through bits [7:0] of register FREQ100 (15h). The first is the long-term Frequency Offset. The second is the current Frequency Control value, which includes shortterm phase adjustments and can provide information on the amount of jitter in the system.

DP83849IF

45 www.national.com

5.8.1.5 Cable Signal Quality Estimation

The cable signal quality estimator keeps a simple tracking of results of the DSP and can be used to generate an approximate Signal-to-Noise Ratio for the 100Mb receiver. This information is available to software through the Link Diagnostics Registers - Page 2: Variance Control (VAR_CTRL), address 1Ah and Data (VAR_DATA), address 1Bh.

The variance computation times (VAR_TIMER) can be chosen from the set of {2, 4, 6, 8} ms. The 32-bit variance sum can be read by two consecutive reads of the VAR_DATA register. This sum can be used to compute an SNR estimate by software using the following eq uation:

SNR = 10log10((37748736 * VAR_TIMER) / Variance).

5.8.2 Link Quality Monitor

The Link Quality Monitor allows a method to generate an alarm when the DSP adaption strays from a programmable window. This could occur due to changes in the cable which could indicate a potential problem. Software can program thresholds for the following DSP parameters to be used to interrupt the system:

— Digital Equalizer C1 Coefficient (DEQ C1)

DP83849IF

46 www.national.com

5.8.3 TDR Cable Diagnostics

The DP83849IF implements a Time Domain Reflectometry (TDR) method of cable length measurement and evalua tion which can be used to evaluate a connected twisted pair cable. The TDR implementation involves sending a pulse out on either the Transmit or Receive conductor pair and observi ng the re sults on eit her pair. By obser ving the types and strength of ref lec tio ns on eac h p a ir, software can determine the following:

—Cable short — Cable open — Distance to fault — Identify which pair has a fault — Pair sk ew

This is especially useful for eliminating the transmitted pulse, but also may be used to look for multiple reflections.

5.8.3.3 TDR Control Interface

The TDR Control interface is implemented in the Li nk D ia gnostics Registers - Page 2 through TDR Control (TDR_CTRL), address 16h and TDR Window (TDR_WIN), address 17h. The following basic controls are:

— TDR Enable: Enable bit 15 of TDR_CTRL (16h) to allow

the TDR function. This bypasses normal operation and gives control of the CD10 and CD100 block to the TDR function.

— TDR Send Pulse: Enable bit 11 of TDR _CTRL (16 h) to

send the TDR pulse and starts the TDR Mo nitor.

DP83849IF

The TDR cable diagnostics works best in certain conditions. For example, an unterminated cable provides a good reflection for measuring cable length, while a cable with an ideal term ina tio n to an unpowered partner ma y p ro vide no reflection at al l.

5.8.3.1 TDR Pulse Genera tor

The TDR implementation can send two types of TDR pulses. The first option is to send 50ns or 100ns link pulses fro m t he 10Mb Common Dr iv er. The sec o nd op t i on is to send pulses from the 100Mb Common Driver in 8ns increments up to 56ns in width. The 100Mb pulses will alternate between positive and negative pulses. The shorter pulses provide better ability to measure short cable lengths, especially since they will limit overlap between the transmitted pulse and a reflected pulse. The longer pulses may provide better measurements of long cable lengths.

In addition, if the pulse width is programmed to 0, no pulse will be sent, but monitor circuit will still be activated. This allows sampling of background data to provide a baseline for analysis.

5.8.3.2 TDR Pulse Monitor

The TDR monitor implements a timer that starts when the pulse is transmitted. A window may be enabled to qualify incoming data to look for response only in a desired range.

The following Transmit mode controls are available: — Transmit Mode: Enables use of 10Mb Link pulses fro m

the 10Mb Common Driver or da ta pulses from the 100Mb Common Driver by enabling TDR 100Mb, bit 14 of TDR_CRTL (16h).

— Transmit Pulse Width: Bits [10:8] of TDR_CTRL (16h)

allows sending of 0 to 7 c lo ck wid th p uls es . Ac tua l p uls es are dependent on the transmit mode. If Pulse Width is set to 0, then no pulse will be sent.

— Transmit Channel Select: The transmitter can send

pulses down either the transmit pair or the receive pair by enabling bit 13 of TDR_CTRL (16h). Default value is to select the transmit pair.

The following Receive mode controls are available: — Min/Max Mode Select: Bit 7 of TDR_CTRL (16h) con-

trols the TDR Monitor operation. In default mode, the monitor will detect maximum (positive) values. In Min mode, the monitor will detect minimum (negative) val ues.

— Receive Channel Select: The receiver can mo nitor ei-

ther the transmit pair or the receive pair by enabling bit 12 of TDR_CTRL (16h). Default value is to select the transmit pair.

— Receive Window: The receiver can monitor receive

data within a programmable w indow using the TDR Win dow Register (TDR_WIN), address 17h. The window is controlled by two regi ster values: TDR Start Windo w, bits [15:8] of TDR_WIN (17h) and TDR Stop Window, bits [7:0] of TDR_WIN (17h). The TDR Start Window indi cates the first clock to start sampling. The TDR Stop Window indicates the last clock to sample. By default, the full window is enabled, with Start set to 0 and Stop set to 255. The window range is in 8ns clock i ncrements, so the maximum window size is 2048ns.

47 www.national.com

5.8.3.4 TDR Results

The TDR function monitors data from the Analog to Digital Converter (ADC) to detect both peak values and values above a programmable threshold. It can be programmed to detect maximum or minimum values. In addition, it records the time, in 8ns intervals, at which the peak or threshold value firs t occu rs. Th e resul ts of a TDR peak and threshold measurement are available in the TDR Peak Measurement Register (TDR_PEAK), address 18h and TDR Threshold Measurement Register (TDR_THR), address 19h. The thresho ld measurem ent may be a m ore accurate method of measuring the length for longer cables to provide a better indication of the start of the received pulse, rather than the peak value.

Software utilizing the TDR function should implement an algorithm to send TDR pulses and evaluate results. Multi ple runs should be us ed to best qualify any rece iv ed pul ses as multiple reflections could exist. In addition, when moni toring the transmitting pair, the window feature should be used to disqualify the transmitted pulse. Multiple runs may also be used to average the values providing more accu rate results.

Actual distance measurements are dependent on the velocity of prop agatio n of the c able. The delay value is ty p ically on the order of 4.6 to 4.9 ns/m.

DP83849IF

48 www.national.com

6.0 Reset Operatio n

The DP83849IF includes an internal power-on reset (POR) function and does not need to be explicitly reset for normal operation after power up. If required during normal opera tion, the device can be reset by a hardware or software reset.

6.1 Hardware Reset

A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1 RESET_N pin. This will reset the device such that all registers will be reinitialized to default values and the hardware configuration val ues wil l be re-la tc hed into the device (simi lar to the power-up/reset operation).

µs, to the

6.2 Full Software Reset

A full-chip software reset is accomplished by setting the reset bit (bit 15) of the Basic Mode Control Register

(BMCR). The period from the point in time when the reset bit is set to the point in time when software reset has con cluded is approximately 1 µs.

The software reset will reset the device such that all registers will be reset to defau lt v alu es and the h ardw a re co nfi guration values will be maintained. Software driver code must wait 3 further serial MII operations with the DP83849IF.

µs following a software reset before allowing

6.3 Soft Reset

A partial software reset can be initiated by setting the Soft Reset bit (bit 9) in the PHYCR2 Register. Setting this bit will reset all transmit and receive operations, but will not reset the register space. All register configurations will be pre served. Register space will remain available following a Soft Reset.

DP83849IF

49 www.national.com

7.0 Register Block

Table 18. Register Map

Offset

Hex Decimal

00h 0 RW BMCR Basic Mode Control Register 01h 1 RO BMSR Basic Mode Status Register 02h 2 RO PHYIDR1 PHY Identifier Register #1 03h 3 RO PHYIDR2 PHY Identifier Register #2 04h 4 RW

Access Tag Description

DP83849IF

50 www.national.com

Re-

served

bility

Extend-

ed Capa-

REV

MDL_

Protocol

Selection

ABLE

LP_AN_

Re-

Link

Status

served

RHF_IN

T_EN

l Bit

Page_Se

CNT

RXER-

BYPASS

SCRAM_

Re-

Collision

Duplex

Isolate Restart

Power

served

Test

Mode

Auto-

Down

REV

Detect

Jabber

Link

Status

Neg

Auto-

Ability

Fault

Remote

Neg

plete

Auto-

Com-

Sup-

press

amble

MF Pre-

Re-

served

Re-

served

Re-

Neg

served

Re-

served

HDX

10Base-

MDL_

REV

MDL_

REV

MDL_

MDL

VNDR_

MDL

VNDR_

MDL

VNDR_

MDL

VNDR_

MDL

VNDR_

MDL

Protocol

Selection

Protocol

Selection

Protocol

Selection

PAUSE T4 TX_FD TX 10_FD 10 Protocol

ASM_DI

PAGE_

NP_

PDF LP_NP_

Re-

ABLE

served

Re-

Status

Speed

served

Re-

Status

served

Duplex

Re-

tus

Loop-

served

back Sta-

Neg

plete

Auto-

Com-

served

Detect

served

Jabber

Fault

served

Remote

rupt

served

MII Inter-

Page

served

Receive

De-

served

scram-

bler Lock

Signal

Detect

served

False

Sense

served

Carrier

TINT INTEN INT_OE

Re-

FHF_INT

ANC_IN

served

DUP_IN

served

SPED_I

served

LINK_IN

served

ED_INT_

served

LQ_INT_

served

FHF_INT RHF_IN

served

ANC_IN

served

DUP_IN

_EN

T_EN

NT_EN

T_EN

l Bit

Page_Se

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT

Re-

CNT

RXER-

BYPASS

SCRAM_

CNT

RXER-

BYPASS

CNT

RXER-

FEFI_EN NRZI_

Re-

CNT

served

RXER-

CNT

RXER-

100_OK

CNT

RXER-

FX_EN FORCE_

IME

CNT

RXER-

DESC_T

Re-

served

SD_

served

OPTION

Re-

served

CE_PMA

Re-

served

TQ_EN SD_FOR

Re-

served

FREE_C

Table 19. Register Table

Auto-

Speed

Neg

Selection

FDX

Enable

10Base-

100Base

-TX HDX

Re-

served

Fault

Remote

ACK2 Toggle Code Code Code Code Code Code Code Code Code Code Code

sage

Re-

served

Re-

Page

served

ACK2 TOG_TX CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE

sage

Mes-

Re-

Status

served

Polarity

Re-

Page

Latch

Rx Err

served

Re-

served

Re-

served

Re-

SPD_IN

Re-

served

Re-

served

Re-

served

Re-

served

EXTENDED REGISTERS - PAGE 0

Re-

04h ANAR Next

ACK Remote

served

Page Ind

05h ANLPAR Next

back

-TX FDX

100Base

-T4

OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB

OUI LSB OUI LSB OUI LSB OUI LSB OUI LS B OUI LSB VNDR_

00h BMCR Reset Loop-

01h BMSR 100Base

02h PHYIDR

03h PHYIDR

Register Name Addr Tag Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ACK Mes-

05h AN-

Page Ind

LPARNP

Re-

07h ANNPTR Next

Re-

served

MDIX

Page Ind

Re-

served

08-0fh Re-

10h PHYSTS Re-

served

06h ANER Re-

Re-

mode

served

11h MICR Re-

12h MISR LQ_INT ED_INT LINK_IN

Re-

13h Re-

Re-

served

14h FCSCR Re-

Re-

served

15h RECR Re-

16h PCSR Re-

Basic Mode Control Register

Basic Mode Status Register

PHY Identifier Register 1

PHY Identifier Register 2

Auto-Negotiation Advertisement Register

Auto-Negotiation Link Partner Ability Register

(Base Page)

Auto-Negotiation Link Partner Ability Register

Auto-Negotiation Expansion Register

Auto-Negotiation Next Page TX Register

RESERVED

PHY Status Register

MII Interrupt Control Register

MII Interrupt Status and Misc. Control Regis-

ter

Page Select Register

False Carrier Sense Counter Register

Receive Error Counter Register

PCS Sub-Layer Configuration and Status

51 www.national.com

Sel

BUF

ELAST_

PHY

ADDR

JABBER

_DIS

Re-

CDPatt-

ED_DAT

A_COUN

Re-

served

Re-

served

LEN

FFSET

CABLE_

FREQ_O

RX_THR

ESHOLD

TDR_ST

TDR-

THR_TI

AK_TIM

TDR_PE

VAR_DA

Re-

served

MER

VAR_TI

ELAST_

RX_UNF

RX_OVF

RMII_RE

RMII_M

SCMII_T

SCMII_R

PMD_LO

TX_SOU

BUF

_STS

V1_0

ODE

RCE

SPDLED LNKLED ACTLED

TLED

DRV_AC

KLED

DRV_LN

DLED

DRV_SP

REQ

BLINK_F

REQ

BLINK_F

_RX

LEDACT

Re-

served

Re-

served

PHY

LED_

BP_STR

BIST_ST

ADDR

CNFG[0]

CNFG[1]

ETCH

ART

STATUS

HEARTB

EAT_DIS

Re-

served

Re-

served

POLARI-

Re-

served

LINK_10

LP_DIS FORCE_

CK_10_

LOOPBA

SQUELC

DIS

served

ESET

served

ED_DAT

ED_ERR

ED_DAT

ED_ERR

ED_PW

A_COUN

_COUNT

A_MET

_MET

R_STAT

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

LEN

FFSET

CABLE_

LEN

CABLE_

LEN

CABLE_

LEN

CABLE_

LEN

CABLE_

LEN

CABLE_

LEN

CABLE_

Re-

served

Re-

served

Re-

served

FREQ_O

SEL_FC FREQ_O

Re-

FFSET

served

RX_THR

Re-

TDR_MI

TDR_WI

ESHOLD

TDR_ST

ESHOLD

TDR_ST

ESHOLD

TDR_ST

ESHOLD

TDR_ST

ESHOLD

TDR_ST

served

TDR_ST

N_MOD

TDR_ST

DTH

TDR_ST

ART

DTH

TDR_ST

ART

DTH

TDR_ST

ART

Sel

Re-

CDPatt-

Re-

10Meg_

Patt_Ga

Re-

served

Re-

N_10

CDPattE

Re-

ODE

BIST_C

ONT_M

Re-

served

Re-

served

Re-

OUNT

ROR_C

BIST_ER

OUNT

ROR_C

SOFT_R

BIST_ER

Re-

BIST_ER

ROR_C

OUNT

TDR-

AK_TIM

TDR_PE

TDR-

AK_TIM

TDR_PE

TDR-

AK_TIM

TDR_PE

TDR-

AK_TIM

TDR_PE

TDR-

AK_TIM

TDR_PE

TDR-

AK_TIM

TDR_PE

TDR-

AK_TIM

TDR_PE

TDR_TH

Re-

TDR_PE

Re-

TDR_PE

MER

VAR_TI

THR_TI

MER

THR_TI

VAR_TI

EEZE

THR_TI

VAR_FR

Re-

served

THR_TI

Re-

served

THR_TI

Re-

served

THR_TI

Re-

served

THR_TI

Re-

served

R_MET

Re-

served

Re-

served

VAR_DA

TAT

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

Table 19. Register Table

RX_POR

DIS_TX_

Re-

17h RBR SIM_WR

Re-

served

Re-

served

Re-

served

OPT

Re-

served

ITE

served

18h LEDCR Re-

BIST_FE PSR_15 BIST_

PAUSE_

MDIX

FORCE_

19h PHYCR MDIX_E

SQUELC

Re-

1Ah 10BT_S

served

ERIAL

Re-

OUNT

served

ROR_C

BIST_ER

Re-

OUNT

served

ROR_C

BIST_ER

Re-

ROR_C

OUNT

served

Re-

served

1Ch PHYCR2 Re-

BIST_ER

1Bh CDCTRL

ST_DIS

ED_MAN ED_BUR

O_DOW

ED_AUT

O_UP

1Dh EDCR ED_EN ED_AUT

Re-

1Eh-1Fh Re-

Re-

served

Re-

served

RESERVED REGISTERS

Re-

served

Re-

served

Re-

served

14h-1Fh Re-

served

LINK DIAGNOSTICS REGISTERS - PAGE 2

served

Re-

14h LEN100_

served

DET

Re-

served

SEND_T

TDR_ST

Re-

NNEL

served

RX_CHA

TDR_ST

Re-

NNEL

served

TX_CHA

TDR_ST

Re-

0Mb

served

TDR_10

TDR_ST

SAMPLE

_FREQ

TDR_EN

ABLE

TDR_ST

15h FREQ10

16h TDR_CT

17h TDR_WI

ART

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

19h TDR_TH

TDR_PE

Re-

18h TDR_PE

Re-

VAR_RD

1Ah VAR_CT

VAR_DA

1Bh VAR_DA

Re-

served

Re-

served

Re-

served

Re-

TAT

served

Re-

served

1Ch Re-

served

Register Na m e Addr Tag B it 1 5 Bi t 1 4 Bit 13 Bit 12 Bit 11 Bit 10 B it 9 Bit 8 B it 7 Bit 6 Bit 5 B it 4 Bit 3 Bit 2 B i t 1 Bit 0

RMII and Bypass Register

LED Direct Control Register

PHY Control Register

10Base-T Status/Control Register

CD Test Control and BIST Extensions Regis-

ter

Phy Control Register 2

Energy Detect Control Register

RESERVED

100Mb Length Detect Register

100Mb Frequency Offset Indication Register

TDR Control Register

TDR Window Register

TDR Peak Register

TDR Threshold Register

Variance Control Register

Variance Data Register

RESERVED

52 www.national.com

C1_LO_

C1_HI_

DAGC_L

DAGC_H

DBLW_L

DBLW_H

FREQ_L

FREQ_H

FC_LO_

FC_HI_

WARN

O_WAR

I_WARN

O_WAR

I_WARN

O_WAR

I_WARN

WARN

Re-

served

_DATA

LQ_THR

Re-

served

_DATA

LQ_THR

Re-

served

_DATA

LQ_THR

Re-

served

_DATA

LQ_THR

Re-

served

_DATA

LQ_THR

Re-

served

_DATA

LQ_THR

Re-

served

_DATA

LQ_THR

Re-

served

_DATA

LQ_THR

Re-

_SEL

served

LQ_THR

Re-

served

LQ_PAR

AM_SEL

Table 19. Register Table

Re-

served

Re-

served

Re-

served

Re-

served

Re-

served

ABLE

1Dh LQMR LQM_EN

Re-

served

LQ_PAR

AM_SEL

Re-

served

LQ_PAR

AM_SEL

Re-

served

WRITE_

LQ_THR

Re-

served

SAMPLE

_PARAM

Re-

served

Re-

served

1Eh LQDR Re-

1Fh Re-

Register Na m e Addr Tag B it 1 5 Bi t 1 4 Bit 13 Bit 12 Bit 11 Bit 10 B it 9 Bit 8 B it 7 Bit 6 Bit 5 B it 4 Bit 3 Bit 2 B i t 1 Bit 0

Link Quality Monitor Register

Link Quality Data Register

RESERVED

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7.1 Register Definition

In the register definitions under the ‘Default’ heading, the following definitions hold true: — RW=Read Write access — SC=Register sets on event occurrence and Self-Clears when event ends — RW/SC =Read Write access/Self Clearing bit

— RO=Read Only access — COR = Clear on Read — RO/COR=Read Only, Clear on Read — RO/P=Read Only, Permanently set to a default value — LL=Latched Low and held until read, based upon the occurrence of the corresponding event

—LH=Latched High and held until read, based upon the occurrence of the corresponding event

DP83849IF

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7.1.1 Basic Mode Control Register (BMCR)

Table 20. Basic Mode Control Register (BMCR), address 00h

Bit Bit Name Default Description

15 RESET 0, RW/SC Reset:

1 = Initiate software Reset / Reset in Process. 0 = Normal operation. This bit, which is self-clearing, returns a value of one until the reset

process is complete. The configuration is re-strapped.

14 LOOPBACK 0, RW Loopback:

1 = Loopback enabled. 0 = Normal operation. The loopback functio n enables MII transmit dat a to be routed to the MII

receive data path. Setting this bit may cause the descram bler to lose synchroni zation and

produce a 500 µs “dead ti me ” before any valid data will appear at the MII receive outputs.

13 SPEED SELEC-

TION

12 AUTO-NEGOTI-

ATION

ENABLE

11 POWER DOWN 0, RW Power Down:

10 ISOLATE 0, RW Isolate:

9 RESTART

AUTO-NEGOTI

ATION

8 DUPLEX MODE Strap, RW Duplex Mode:

Strap, RW Speed Select:

When auto-negotiation is disabled writing to this bit allows the port speed to be selected.

1 = 100 Mb/s. 0 = 10 Mb/s.

Strap, RW Auto-Negotiation Enable:

Strap controls initial value at reset. If FX is enabled (FX_EN = 1), then this bit will be reset to 0. 1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ig-

nored when this bit is set. 0 = Auto-Negotiati on Disabled - bits 8 and 13 determine t he port speed

and duplex mode.

1 = Power down. 0 = Normal operation. Setting this bit powers down the PHY. Only the register block is en-

abled durin g a power down condition. This bit is OR’d with the input from the PWRDOWN_INT pin . When the acti ve low PWRDO WN_INT pin is asserted, this bit will be set.

1 = Isolates the Port fro m t he M II with the exception of the se rial ma nagement.

0 = Normal operation.

0, RW/SC Restart Auto-Negotiation:

1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If Auto-Negotiati on is disabled (bit 12 = 0), this bit is ig nored. This bit is self-clearing and will retu rn a val ue of 1 until Auto-Negotiation is initiated, whereupo n it will self-clear. Opera tion of the Auto-Negotiati on process is not affected by the management entity clearing this bit.

0 = Normal operation.

When auto-negotiatio n is disabled wri ting to this bit allows the port Duplex capability to be selected.

1 = Full Duplex operation. 0 = Half Duplex operati on.

DP83849IF

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Table 20. Basic Mode Control Register (BMCR), address 00h (Continued)

Bit Bit Name Default Description

7 COLLISION

TEST

6:0 RESERVED 0, RO RESERVED: Write ignored, read as 0.

0, RW Collision Test:

1 = Collision test enabled. 0 = Normal operation. When set, this bit w ill cause the COL s ignal to be asserte d in response

to the assertion of TX _EN within 5 12-bit time s. The COL s ignal w ill be de-asserted within 4-bit times in response to the de-assertion of TX_EN.

DP83849IF

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7.1.2 Basic Mode Status Register (BMSR)

Table 21. Basic Mode Status Register (BMSR), address 01h

Bit Bit Name Default Description

15 100BASE-T4 0, RO/P 100BASE-T4 Capable:

0 = Device not able to perform 100BASE-T4 mode.

14 100BASE-TX

FULL DUPLEX

13 100BASE-TX

HALF DUPLEX

12 10BASE-T

FULL DUPLEX

11 10BASE-T

HALF DUPLEX

10:7 RESERVED 0, RO RESERVED: Write as 0, read as 0.

6 MF PREAMBLE

SUPPRESSION

5 AUTO-NEGOTIATION

COMPLETE

4 REMOTE FAULT 0, RO/LH Remote Fault:

3 AUTO-NEGOTIATION

ABILITY

2 LINK STATUS 0, RO/LL Link Status:

1 JABBER DETECT 0, RO/LH Jabber Detect: This bit only has meaning in 10 Mb/s mode.

0 EXTENDED CAPA-

BILITY

1, RO/P 100BASE-TX Full Duplex Capable:

1 = Device able to perform 100BASE-TX in full duplex mode.

1, RO/P 100BASE-TX Half Duplex Capable:

1 = Device able to perform 100BASE-TX in half duplex mode.

1, RO/P 10BASE-T Full Duplex Capable:

1 = Device able to perform 10BASE-T in full duplex mode.

1, RO/P 10BASE-T Half Duplex Capable:

1 = Device able to perform 10BASE-T in half duplex mode.

1, RO/P Preamble suppression Capable:

1 = Device able to perform management transaction with preamble suppressed, 32-bits of preamble needed on ly once after reset, invali d opcode or invalid turnaround.

0 = Normal management operation.

0, RO Auto-Negotiation Complete:

1 = Auto-Negotiation process complete. 0 = Auto-Negotiation process not complete.

1 = Remote Fault condition detected (cleared on read or by reset). Fault criteria: Far End Fault Indication or notification from Link Part ner of Remote Fault.

0 = No remote fault condition detected.

1, RO/P Auto Negotiation Ability:

1 = Device is able to perform Auto-Negotiation. 0 = Device is not able to perform Auto-Negotiation.

1 = Valid link established (for either 10 or 100 Mb/s operation). 0 = Link not established. The criteria for link vali dity is implementation spec ific. The occurrence

of a link failure cond ition will cau ses the Link Status bit to clear. Onc e cleared, this bit may onl y be set by est ablishin g a good link c ondition and a read via the management interface.

1 = Jabber condition detected. 0 = No Jabber. This bit is implemented with a latching function, such that the occur-

rence of a jabber condition c auses it to set until it is cleared by a rea d to this register by the management interface or by a reset.

1, RO/P Extended Capability:

1 = Extended register capabilities. 0 = Basic register set capa bilities only.

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The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83849IF. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision num ber. A PHY may r etur n a val ue of zero in eac h of th e 32 bi ts of the PHY Identi fier if d esired . The PHY I dentifi er is i ntende d to support network management. National's IEEE assigned OUI is 080017h.

7.1.3 PHY Identifier Register #1 (PHYIDR1)

Table 22. PHY Identifier Register #1 (PHYIDR1), address 02h

Bit Bit Name Default Description

15:0 OUI_MSB <0010 0000 0000

0000>, RO/P

7.1.4 PHY Identifier Register #2 (PHYIDR2)

Table 23. PHY Identifier Register #2 (PHYIDR2), address 03h

Bit Bit Name Default Description

15:10 OUI_LSB <0101 11>, RO/P OUI Least Significant Bits:

9:4 VNDR_MDL <00 1010>, RO/P Vendor Model Number:

3:0 MDL_REV <0010>, RO/P Model Revision Number:

OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are stored in bits 15 to 0 of this register. The most significant two bits of the OUI are ignored (the IEEE stan dard refe rs to these as bit s 1 and 2).

Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10 of this register respectively.

The six bits of vendor model number are mapped from bits 9 to 4 (most significant bit to bit 9).

Four bits of the vendor model revision number are mapped from bits 3 to 0 (most si gnificant bit to bi t 3). This field wil l be incremented for all major device changes.

DP83849IF

7.1.5 Auto-Negotiation Advertisement Register (ANAR)

This register cont ains the ad vertis ed abi lities of thi s dev ice a s they will b e trans mitted to it s link pa rtne r during Auto-N egotiation. Any writes to this register prior to completion of Auto-Negotiation (as indicated in the Basic Mode Status Register (address 01h) Auto-Negotiation Complete bit, BMSR[5]) should be followed by a renegotiation. This will ensure that the new values are properly used in the Auto-Negotiation.

Table 24. Negotiation Advertisement Register (ANAR), address 04h

Bit Bit Name Default Description

15 NP 0, RW Next Page Indication:

0 = Next Page Transfer no t desired.

1 = Next Page Transfer desired. 14 RESERVED 0, RO/P RESERVED by IEEE: Writes ignored, Read as 0. 13 RF 0, RW Remote Fault:

1 = Advertises that this device has detected a Remote Fault.

0 = No Remote Fault detected. 12 RESERVED 0, RW RESERVED for Future IEEE use: Write as 0, Read as 0

58 www.national.com

Table 24. Negotiation Advertisement Register (ANAR), address 04h (Continued)

Bit Bit Name Default Description

11 ASM_DIR 0, RW Asymmetric PAUSE Support for Full Duplex Links:

The ASM_DIR bit indicates that asymmetric PAUSE is supported.

Encoding and resolution of PAUSE bits is defined in IEEE 802.3

Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolu

tion status is reported in PHYCR[13:12].

1 = Advertise that the DTE (MAC) has implemented both the op-

tional MAC control su bl ayer an d the p ause fu nctio n as s pecif ied in

clause 31 and annex 31B of 802.3u.

0= No MAC based full duplex flow control. 10 PAUSE 0, RW PAUSE Support for Full Duplex Links:

The PAUSE bit indicates that the device is capable of providing the

symmetric PAUSE functions as defined in Annex 31B.

Encoding and resolution of PAUSE bits is defined in IEEE 802.3

Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolu

tion status is reported in PHYCR[13:12].

1 = Advertise that the DTE (MAC) has implemented both the op-

tional MAC control su bl ayer an d the p ause fu nctio n as s pecif ied in

clause 31 and annex 31B of 802.3u.

0= No MAC based full duplex flow control.

9 T4 0, RO/P 100BASE-T4 Support:

1= 100BASE-T4 is supported by the local device.

0 = 100BASE-T4 not supported.

8 TX_FD Strap, RW 100BASE-TX Full Duplex Support:

1 = 100BASE-TX Full Duplex is supported by the local device.

0 = 100BASE-TX Full Duplex not supported.

7 TX Strap, RW 100BASE-TX Support:

1 = 100BASE-TX is supported by the local device.

0 = 100BASE-TX not supported.

6 10_FD Strap, RW 10BASE-T Full Duplex Support:

1 = 10BASE-T Full Duplex is supported by the local device.

0 = 10BASE-T Full Duplex not supported.

5 10 Strap, RW 10BASE-T Support:

1 = 10BASE-T is supported by the local device.

0 = 10BASE-T not supported.

4:0 SELECTOR <00001>, RW Protocol Selection Bits:

These bits contain the binary enc oded protoco l se lector s upporte d

by this port. <00001> indicates that this device supports IEEE

802.3u.

DP83849IF

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7.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)

This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported.

Table 25. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 05h

Bit Bit Name Default Description

15 NP 0, RO Next Page Indication:

0 = Link Partner does not desire Next Page Transfer.

1 = Link Partner desires Next Page Transfer. 14 ACK 0, RO Acknowledge:

1 = Link Partner acknowledges reception of the ability data word.

0 = Not acknowledged.

The Auto-Negotiation state machine will automatically control the

this bit based on the incoming FLP bursts. 13 RF 0, RO Remote Fault:

1 = Remote Fault indicated by Link Partner.

0 = No Remote Fault indicated by Link Partner. 12 RESERVED 0, RO RESERVED for Future IEEE use:

Write as 0, read as 0. 11 ASM_DIR 0, RO ASYMMETRIC PAUSE:

1 = Asymmetric pause is supported by the Link Partner.

0 = Asymmetric pause is not supported by the Link Partner. 10 PAUSE 0, RO PAUSE:

1 = Pause function is supported by the Link Partner.

0 = Pause function is not supported by the Link Partner.

9 T4 0, RO 100BASE-T4 Support:

1 = 100BASE-T4 is supported by the Link Partner.

0 = 100BASE-T4 not supported by the Link Partner.

8 TX_FD 0, RO 100BASE-TX Full Duplex Support:

1 = 100BASE-TX Full Duplex is supported by the Link Partner.

0 = 100BASE-TX Full Duplex not supported by the Link Partner.

7 TX 0, RO 100BASE-TX Support:

1 = 100BASE-TX is supported by the Link Partner.

0 = 100BASE-TX not supported by the Link Partner.

6 10_FD 0, RO 10BASE-T Full Duplex Support:

1 = 10BASE-T Full Duplex is supported by the Link Partner.

0 = 10BASE-T Full Duplex not supported by the Link Partner.

5 10 0, R O 10BASE-T Support:

1 = 10BASE-T is supported by the Link Partner.

0 = 10BASE-T not supported by the Link Partner.

4:0 SELECTOR <0 0000>, RO Protocol Selection Bits:

Link Partner’s binary encoded protocol selector.

DP83849IF

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7.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)

Table 26. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 05h

Bit Bit Name Default Description

15 NP 0, RO Next Page Indication:

1 = Link Partner desires Next Page Transfer.

0 = Link Partner does not desire Next Page Transfer. 14 ACK 0, RO Acknowledge:

1 = Link Partner acknowledges reception of the ability data word.

0 = Not acknowledged.

The Auto-Negotiation state machine will automatically control the

this bit based on the incoming FLP bursts. Software should not at

tempt to write to this bit. 13 MP 0, RO Message Page:

1 = Message Page.

0 = Unformatted Page. 12 ACK2 0, RO Acknowledge 2:

1 = Link Partner does have the abi lity to comply to next page mes-

sage.

0 = Link Partner does not have the ability to comply to next page

message. 11 TOGGLE 0, RO Toggle:

1 = Previous value of the transmitted Link Code word equalled 0.

0 = Previous value of the transmitted Link Code word equalled 1.

10:0 CODE <000 0000 0000>, ROCode:

This field represents the code field of the next page transmission.

If the MP bit is set (bit 13 of this register), then the code shall be

interpreted as a “Message Page,” as defined in annex 28C of

Clause 28. Otherwise, the code shall be interpreted as an “Unfor

matted Page,” and the interpretation is application specific.

DP83849IF

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7.1.8 Auto-Negotiate Expansion Register (ANER)

This register contains additional Local Device and Link Partner status information.

Table 27. Auto-Negotiate Expansion Register (ANER), address 06h

Bit Bit Name Default Description

15:5 RESERVED 0, RO RESERVED: Writes ignored, Read as 0.

4 PDF 0, RO Parallel Detection Fault:

1 = A fault has been detected via the Parallel Detection function.

0 = A fault has not been detected.

3 LP_NP_ABLE 0, RO Link Partner Next Page Able:

1 = Link Partner does support Next Page.

0 = Link Partner does not support Next Page.

2 NP_ABLE 1, RO/P Next Page Able:

1 = Indicates local device is able to send additional “Next Pages”.

1 PAGE_RX 0, RO/COR Link Code Word Page Received:

1 = Link Code Word has been received, cleared on a read.

0 = Link Code Word has not been received.

0 LP_AN_ABLE 0, RO Link Partner Auto-Negotiation Able:

1 = indicates that the Link Partner supports Auto-Negotiation.

0 = indicates that the Link Partner does not support Auto-Negotia-

tion.

DP83849IF

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7.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR)

This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.

Table 28. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 07h

Bit Bit Name Default Description

15 NP 0, RW Next Page Indication:

0 = No other Next Page Transfer desired.

1 = Another Next Page desired. 14 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 13 MP 1, RW Message Page:

1 = Message Page.

0 = Unformatted Page. 12 ACK2 0, RW Acknowledge2:

1 = Will comply with message.

0 = Cannot comply with message.

Acknowledge2 is used by the next page function to indicate that

Local Device has th e ability t o comply with t he message r eceived. 11 TOG_TX 0, RO Toggle:

1 = Value of toggle bit in previously transmitted Link Code Word

was 0.

0 = Value of toggle bit in previously transmitted Link Code Word

was 1.

Toggle is used by the Arbitration fun ction within Auto-N egotiation

to ensure synchroniza tion with the Lin k Partner during Ne xt Page

exchange. This bit shall always take the opposite value of the

Toggle bit in the previously exchanged Link Code Word.

10:0 CODE <000 000 0 0001>, RWCode:

This field represent s the code fie ld of the next p age transmis sion.

If the MP bit is set (bit 13 of this register), then the code shall be

interpreted as a "Message Page”, as defined in annex 28C of

IEEE 802.3u. Otherwise, the cod e shall b e interp reted as an "Un

formatted Page”, and the interpretation is application specific.

The default value of the CODE represents a Null Page as defined

in Annex 28C of IEEE 802.3u.

DP83849IF

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7.1.10 PHY Status Register (PHYSTS)

This register provides a single location within the register set for quick access to commonly accessed information.

Table 29. PHY Status Register (PHYSTS), address 10h

Bit Bit Name Default Description

15 RESERVED 0, RO RESERVED: Write ignored, read as 0. 14 MDIX MODE 0, RO MDIX mode as reported by the Auto-Negotiation logic:

This bit will be affected by the settings of the MDIX_EN and FORCE_MDIX bits in the PHYCR register. When MDIX is e nabled, but not forced, this bit will update dy namica lly as the Auto-M DIX al gorithm swaps between MDI and MDIX configurations.

1 = MDI pairs swapped

(Receive on TPTD pair, Transmit on TPRD pair)

0 = MDI pairs normal

(Receive on TRD pair, Transmit on TPTD pair)

13 RECEIVE ERROR

LATCH

12 POLARITY STATUS 0, RO Polarity Status:

11 FALSE CARRIER

SENSE LATCH

10 SIGNAL DETECT 0, RO/LL 100Base-TX qualified Signal Detect from PMA:

9 DESCRAMBLER

LOCK

8 PAGE RECEIVED 0, RO Link Code Word Page Received:

7 MII INTERRUPT 0, RO MII Interrupt Pending:

0, RO/LH Receive Error Latch:

This bit will be cleared upon a read of the RECR register. 1 = Receive error event h as occu rred since last read of RXERCNT

(address 15h, Page 0). 0 = No receive error event has occurred.

This bit is a duplic ation of bit 4 in the 10BTSCR register. This bit will be cleared upon a read of the 10BTSCR register, but not upon a read of the PHYSTS register.

1 = Inverted Polarity detected. 0 = Correct Polarity detected.

0, RO/LH False Carrier Sense Latch:

This bit will be cleared upon a read of the FCSR register. 1 = False Carrier event h as occurred since last read of FCSCR (ad -

dress 14h). 0 = No False Carrier event has occurred.

This is the SD that goes into the link monitor. It is the AND of raw SD and descrambler lock, whe n addres s 16h, bit 8 (page 0) is se t. When this bit is cleared, it will be equivalent to the raw SD from the PMD.

0, RO/LL 100Base-TX Descrambler Lock from PMD.

This is a duplicate of the Page Received bit in the ANER register, but this bit will no t be cl ea red u po n a read of the PH YSTS re gis te r.

1 = A new Link Code Word Page has been received. Cleared on read of the ANER (address 06h, bit 1).

0 = Link Code Word Page has not been received.

1 = Indicates that an internal interrupt is pending. Interrupt source can be determined by reading the MISR Register (12h). Reading the MISR will clear the Interrupt.

0 = No interrupt pending.

DP83849IF

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Table 29. PHY Status Register (PHYSTS), address 10h

Bit Bit Name Default Description

6 REMOTE FAULT 0, RO Remote Fault:

1 = Remote Fault c ondition detected (cleared on read of BMSR (address 01h) register or by reset). Fault c riteria: notif ication from Link Partner of Remote Fault via Auto-Negotiation.

0 = No remote fault condition detected.

5 JABBER DETECT 0, RO Jabber Detect: This bit only has meaning in 10 Mb/s mode

This bit is a dupl icate of the Jabber De tect bit in the BMSR register, except that it is not cleared upon a read of the PHYSTS register.

1 = Jabber condition detected. 0 = No Jabber.

4 AUTO-NEG COM-

PLETE

3 LOOPBACK STA-

TUS

2 DUPLEX STATUS 0, RO Duplex:

1 SPEED STATUS 0, RO Speed10:

0 LINK STATUS 0, RO Link Status:

0, RO Auto-Negotiation Complete:

1 = Auto-Negotiation complete. 0 = Auto-Negotiation not complete.

0, RO Loopback:

1 = Loopback enabled. 0 = Normal operation.

This bit indicates duplex status and is determ ined from Auto -Negotiation or Forced Modes.

1 = Full duplex mode. 0 = Half duplex mode. Note: This bit is only valid if Auto-Negotiation is enabled and com-

plete and there is a valid li nk or if Au to-Negoti ation i s disa bled an d there is a valid link.

This bit indicates the status of the speed and is determined from Auto-Negotiation or Forced Modes.

1 = 10 Mb/s mode. 0 = 100 Mb/s mode. Note: This bit is only valid if Auto-Negotiation is enabled and com-

plete and there is a valid li nk or if Au to-Negoti ation i s disa bled an d there is a valid link.

This bit is a duplicate of the Link Status bit in the BMSR register, except that it will not be cleared upon a read of t he PHYSTS regis ter.

1 = Valid link established (for either 10 or 100 Mb/s operation) 0 = Link not established.

DP83849IF

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7.1.11 MII Interrupt Control Register (MICR)

This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Energy Detect State Change, Link State Change, Speed Status Change, Duplex Status Change, Auto-Negotiation Complete or any of the counters becom in g hal f-ful l. The ind iv idu al in terru pt ev en ts must be enabled by setting bi t s in the MII Interrupt Status and Event Control Register (MISR).

Table 30. MII Interrupt Control Register (MICR), address 11h

Bit Bit Name Default Description

15:3 RESERVED 0, RO RESERVED: Writes ignored, read as 0.

2 TINT 0, RW Test Interrupt:

Forces the PHY to generate an interrupt to facilitate interrupt testing. Interrupts will continue to be generated as long as this bit remains set.

1 = Generate an interrupt 0 = Do not generate interrupt

1 INTEN 0, RW Interrupt Enable:

Enable interrupt dependent on the event enables in the MISR register.

1 = Enable event based interrupts 0 = Disable event based interrupts

0 INT_OE 0, RW Interrupt Output Enable:

Enable interrupt events to signal via the PWRDOWN_INT pin by configuring the PWRDOWN_INT pin as an output .

1 = PWRDOWN_INT is an Interrupt Output 0 = PWRDOWN_INT is a Power Down Input

DP83849IF

7.1.12 MII Interrupt Status and Misc. Control Register (MISR)

This register contains event status and enables for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set, an interrupt will be generated if the event occ urs . The MI CR regis te r con trols mu st al so be se t to allow interrupts. The statu s in dic ati on s in this register will be set even if the interrupt is not enabled

Table 31. MII Interrupt Status and Misc. Control Register (MISR), address 12h

15 LQ_INT 0, RO/COR Link Quality interrupt:

14 ED_INT 0, RO/COR Energy Detect interrupt:

13 LINK_INT 0, RO/COR Change of Link Status interrupt:

12 SPD_INT 0, RO/COR Change of speed status interrupt:

1 = Link Quality interrupt is pending and is cleared by the current read.

0 = No Link Quality interrupt pending.

1 = Energy detect interrup t is pe nding and is clea red by the cu rrent read.

0 = No energy detect interrupt pending.

1 = Change of link status inter r upt is pen din g an d is c lea red by the current read.

0 = No change of link status interrupt pending.

1 = Speed status change interrupt is p end ing and is cleared by the current read.

0 = No speed status change interrupt pending.

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Table 31. MII Interrupt Status and Misc. Control Register (MISR), address 12h

11 DUP_INT 0, RO/COR Change of duplex status interrupt:

1 = Duplex status change interrupt is pending and is cleared by the current read.

0 = No duplex status change interrupt pending.

10 ANC_INT 0, RO/COR Auto-Negotiation Complete interrupt:

1 = Auto-negotiation complete interrupt is pending and is cleared by the curr ent read.

0 = No Auto-negotiation complete interrupt pending.

9 FHF_INT 0, RO/COR False Carrier Counter half-full interrupt:

1 = False carrier counter half-full interrupt is pending and is cleared by the current read.

0 = No false carrier counter half-full interrupt pending.

8 RHF_INT 0, RO/COR Receive Error Counter half-full interrupt:

1 = Receive error counter half-full interrupt is pending and is cleared by the current read.

0 = No receive error carrier counter half-full interrupt pending. 7 LQ_INT_EN 0, RW Enable Interrupt on Link Quality Monitor event 6 ED_INT_EN 0, RW Enable Interrupt on energy detect event 5 LINK_INT_EN 0, RW Enable Interrupt on change of link status 4 SPD_INT_EN 0, RW Enable Interrupt on change of speed status 3 DUP_INT_EN 0, RW Enable Interrupt on change of duplex status 2 ANC_INT_EN 0, RW Enable Interrupt on Auto-negotiation complete event 1 FHF_INT_EN 0, RW Enable Interrupt on False Carrier Counter Register half-full event 0 RHF_INT_EN 0, RW Enable Interrupt on Receive Error Counter Register half-full event

DP83849IF

7.1.13 Page Select Register (PAGESEL)

This register is used to enable access to the Link Diagnostics Registers.

Table 32. Page Select Register (PAGESEL), address 13h

Bit Bit Name Default Description

15:2 RESERVED 0, RO RESERVED: Writes ignored, Read as 0

1:0 PAGE_SEL 0, RW Page_Sel Bit:

Selects between paged registers for address 14h to 1Fh.

0 = Extended Registers Page 0

1 = RESERVED

2 = Link Diagnostics Registers Page 2

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7.2 Extended Registers - Page 0

7.2.1 False Carrier Sense Counter Register (FCSCR)

This counter provides information required to implement the “False Carriers” attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification.

Table 33. False Carrier Sense Counter Register (FCSCR), address 14h

Bit Bit Name Default Description

15:8 RESERVED 0, RO RESERVED: Writes ignored, Read as 0

7:0 FCSCNT[7:0] 0, RO/COR False Carrier Event Counter:

This 8-bit counter increments on every false carrier event. This

counter sticks when it reaches its max count (FFh).

7.2.2 Receiver Error Counter Register (RECR)

This counter provides information required to implement the “Symbol Error During Carrier” attribute within the PHY managed object class of Clause 30 of the IEEE 802.3u specification.

Table 34. Receiver Error Counter Register (RECR), address 15h

Bit Bit Name Default Description

15:8 RESERVED 0, RO RESERVED: Writes ignored, Read as 0

7:0 RXERCNT[7:0] 0, RO/COR RX_ER Counter:

When a valid car rier is prese nt and there is at leas t one occur rence

of an invalid data symbo l, this 8-bit c ounte r incre ments for e ach re-

ceive error detected. Thi s even t can inc remen t only on ce per va lid

carrier event. If a collision is present, the attribute will not incre

ment. The counter sticks when it reaches its max count.

DP83849IF

7.2.3 100 Mb/s PCS Configuration and Status Register (PCSR)

This register contains control and status information for the 100BASE Physical Coding Sublayer.

Table 35. 100 Mb/s PCS Configuration and Status Register (PCSR), address 16h

Bit Bit Name Default Description

15:12 RESERVED <00>, RO RESERVED: Writes ignored, Read as 0.

11 FREE_CLK 0, RW Receive Clock:

1 = RX_CLK is free-running

0 = RX_CLK phase adjusted based on alignment

10 TQ_EN

9 SD FORCE PMA

0, RW

0,RW

100Mbs True Quiet Mode Enable:

1 = Transmit True Quiet Mode.

0 = Normal Transmit Mode.

Signal Detect Force PMA:

1 = Forces Signal Detection in PMA.

0 = Normal SD operation.

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Table 35. 100 Mb/s PC S Configuration and Status Register (PCSR), address 16h (Continued)

Bit Bit Name Default Description

8 SD_OPTION 1, RW Signal Detect Option:

1 = Default operation. Link will be asserted following detection of

valid signal le vel and Descra mbler Lock. Link will be m aintained as

long as signal level is valid. A loss of Descrambler Lock will not

cause Link Status to drop.

0 = Modified sign al detect algori thm. Link wi ll be asserted following

detection of valid signal level and Descrambler Lock. Link will be

maintained as long as signal level is valid and Descrambler re

mains locked. 7 DESC_TIME 0, RW Descrambler Timeout:

Increase the descrambler timeout. When set this should allow the

device to receive larger packets (>9k bytes) without loss of syn-

chronization.

1 = 2ms

0 = 722us (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e) 6 FX_EN Strap, RW FX Fiber Mode Enable:

This bit is set when the FX_ EN strap option is selec ted (pulled high)

for the respective port.

1 = Enables FX operation

0 = Disables FX operation 5 FORCE_100_OK 0, RW Force 100Mb/s Good Link:

1 = Forces 100Mb/s Good Link.

0 = Normal 100Mb/s operation. 4 RESERVED 0, RO RESERVED: Writes ignored, Read as 0 3 FEFI_EN Strap, RW Far End Fault Indication Mode Enable:

This bit is set when the FX_EN strap option is selected for the re-

spective port.

1 = FEFI Mode Enabled

0 = FEFI Mode Disabled 2 NRZI_BYPASS 0, RW NRZI Bypass Enable:

1 = NRZI Bypass Enabled.

0 = NRZI Bypass Disabled. 1 SCRAM

BYPASS

0 DESCRAM

BYPASS

Strap, RW Scrambler Bypass Enable:

This bit is set when the FX_EN strap option is selected for the re-

spective port. In the FX mode, the scrambler is bypassed.

1 = Scrambler Bypass Enabled

0 = Scrambler Bypass Disabled

Strap, RW Descrambler Bypass Enable:

This bit is set when the FX_EN strap option is selected for the re-

spective port. In the FX mode, the descrambler is bypassed.

1 = Descrambler Bypass Enab led

0 = Descramb ler Bypass Disabled

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7.2.4 RMII and Bypass Register (RBR)

This register configures the RMII/MII Interface Mode of operation. This register controls selecting MII, RMII, or Single Clock MII mode for Receive or Transmit. In addition, several additional bits are included to allow datapath selection for Transmit and Receive in multiport applications.

Table 36. RMII and Bypass Register (RBR), addresses 17h

Bit Bit Name Default Description

15 SIM_WRITE 0, RW Simultaneous Write:

Setting this bit in p ort A regi ster space en ables simu ltaneo us write to Phy

registers in both ports. Subsequent writes to port A registers will write to

registers in both ports A an d B .

1 = Simultaneous writes to both ports

0 = Per-port write

14 RESERVED 0, RO RESERVED: Writes ignored, Read as 0 13 DIS_TX_OPT 0, RW Disable RMII TX Latency Optimization:

Normally the RMII Trans mitter will mini mize the tr ansmit late ncy by

realigning the transmit c lock with th e Referen ce clock pha se at the

start of a packet trans mission. Se tting this bit will disable Ph ase re

alignment and ensu re that IDLE bits w ill always be se nt in multiples

of the symbol size. This will result in a larger uncertainty in RMII

transmit latency.

12:11 RX_PORT 00, RW Receive Port:

See Section 3.5 for more information on Flexible Port Switching.

10:9 TX_SOURCE Strap, RW Transmit Source:

See Section 3.5 for more information on Flexible Port Switching.

00 = Not strapped for Extender Mode

10 = Strapped for Extender Mode 8 PMD_LOOP 0, RW PMD Loopback:

0= Normal Op eration

1= Remote (PMD) Loopback

Setting this bit will cause the device to Loopback data received

from the Physical Layer. The loopback is done prior to the MII or

RMII interface. Data received at the internal MII or RMII interface

will be applied to th e trans mitter. Th is mode should o nly be us ed if

RMII mode or Single Clock MII mode is enabled. 7 SCMII_RX Strap, RW Single Clock RX MII Mode:

0= Standard MII mode

1= Single Clock RX MII Mode

Setting this bit will cause the device to generate receive data

(RX_DV, RX_ER, RXD[3:0]) synchronous to the X1 Reference

clock. RX_CLK is not u sed in this m ode. This mode uses the RMII

elasticity buffer to tolerate variations in clock frequencies. This bit

cannot be set if RMII_MO DE is set to a 1. Thi s bit is strap ped to 1

if EXTENDER_EN is 1 and RMII Mode is not strapped at hard re

set. 6 SCMII_TX Strap, RW Single Clock TX MII Mode:

0= Standard MII mode

1= Single Clock TX MII Mode

Setting this bit will cause the device to sample transmit data

(TX_EN, TXD[3:0]) synchronous to the X1 Reference clock.

TX_CLK is not used in this mode. This bit cannot be set if

RMII_MODE is set to a 1. This bit is strapped to 1 if

EXTENDER_EN is 1 and RMII Mod e is no t strapped at hard reset.

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Table 36. RMII and Bypass Register (RBR), addresses 17h (Continued)

Bit Bit Name Default Description

5 RMII_MODE Strap, RW Reduced MII Mode:

0 = Standard MII Mode

1 = Reduced MII Mode 4 RMII_REV1_0 0, RW Reduced MII Revision 1.0:

0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet

to indicate deassertion of CRS.

1 = (RMII revision 1.0) CRS_DV will remain asserted until final data

is transferred. CRS_DV will not toggle at the end of a packet. 3 RX_OVF_STS 0, RO/COR RX FIFO Over Flow Status:

0 = Normal

1 = Overflow detected 2 RX_UNF_STS 0, RO/COR RX FIFO Under Flow Status:

0 = Normal

1 = Underflow detected

1:0 ELAST_BUF[1:0] 01, RW Receive Elasticity Buffer:

This field controls th e Receive Elas ticity Buffer which a llows for fre-

quency variation toleranc e between the 50M Hz RM II clock a nd the

recovered data. See Section 3.2 for more information on Elastic ity

Buffer settings in RMII mode. Se e Section 3.4 for more informat ion

on Elasticity Buffer settings in SCMII mode.

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7.2.5 LED Direct Control Register (LEDCR)

This register provides the ability to directly control any or all LED outputs. It does not provide read access to LEDs. In addition, it provides control for the Activity source and blinking LED frequency.

Table 37. LED Direct Control Register (LEDCR), address 18h

Bit Bit Name Default Description

15:9 RESERVED 0, RO RESERVED: Writes ignored, read as 0.

8 LEDACT_RX 0, RW 1 = Activity is only indicated for Receive traffic

0 = Activity is indicated for Transmit or Receive traffic

7:6 BLINK_FREQ 00, RW LED Blink Frequency

These bits control the blink frequency of the LED_LINK output

when blinking on activity is enabled.

0 = 6Hz

1 = 12Hz

2 = 24Hz

3 = 48Hz 5 DRV_SPDLED 0, RW 1 = Drive value of SPDLED bit onto LED_SPEED output

0 = Normal operation 4 DRV_LNKLED 0, RW 1 = Drive value of LNKLED bit onto LED_LINK output

0 = Normal operation 3 DRV_ACTLED 0, RW 1 = Drive value of ACTLED bit onto LED_ACT/LED_COL output

0 = Normal operation 2 SPDLED 0, RW Value to force on LED_SPEED output 1 LNKLED 0, RW Value to force on LED_LINK output 0 ACTLED 0, RW Value to force on LED_ACT/LED_COL output

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7.2.6 PHY Control Register (PHYCR)

This register provides control for Phy functions such as MDIX, BIST, LED configuration, and Phy address. It also provides Pause Negotiation status.

Table 38. PHY Control Register (PHYCR), address 19h

Bit Bit Name Default Description

15 MDIX_EN Strap, RW Auto-MDIX Enable:

1 = Enable Auto-neg Auto-MDIX capability.

0 = Disable Auto-neg Auto-MDIX capability.

The Auto-MDIX algorithm requires that the Auto-Negotiation En-

able bit in the BMCR register to be set. If Auto-Negotiation is not

enabled, Auto-MDIX should be disabled as well.

14 FORCE_MDIX 0, RW Force MDIX:

1 = Force MDI pairs to cross.

(Receive on TPTD pair, Transmit on TPRD pair)

0 = Normal operation.

13 PAUSE_RX 0, RO Pause Receive Negotiated:

Indicates that pause re ceive shoul d be enabled i n the MAC. Based

on ANAR[11:10] and ANLPAR[11:10] settings.

This function shall be enabled according to IEEE 802.3 Ann ex 28B

Table 28B-3, “Pause Resolutio n”, only if th e Auto-Negotia ted High

est Common Denominator is a full duplex technology.

12 PAUSE_TX 0, RO Pause Transmit Negotiated:

Indicates that pau se transmit shoul d be enabled in t he MAC. Based

on ANAR[11:10] and ANLPAR[11:10] settings.

This function shall be enabled according to IEEE 802.3 Ann ex 28B

Table 28B-3, “Pause Resolutio n”, only if th e Auto-Negotia ted High-

est Common Denominator is a full duplex technology.

11 BIST_FE 0, RW/SC BIST Force Error:

1 = Force BIST Error.

0 = Normal operation.

This bit forces a single error, and is self clearing.

10 PSR_15 0, RW BIST Sequence select:

1 = PSR15 selected.

0 = PSR9 selected. 9 BIST_STATUS 0, LL/RO BIST Test Status:

1 = BIST pass.

0 = BIST fail. Latched, cleared when BIST is stopped.

For a count number of BIST errors, se e the BIST Error Count in the

CDCTRL1 register. 8 BIST_START 0, RW BIST Start:

1 = BIST start.

0 = BIST stop. 7 BP_STRETCH 0, RW Bypass LED Stretching:

This will bypass the LED stre tchin g and the LED s wil l refle ct the in-

ternal value.

1 = Bypass LED stretching.

0 = Normal operation.

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Table 38. PHY Control Register (PHYCR), address 19h (Continued)

Bit Bit Name Default Description

6 5

LED_CNFG[1] LED_CNFG[0]

0, RW

Strap, RW

LED Configuration

LED_CNFG[1] LED_ CNFG[0] Mode Description

Don’t care 1 Mode 1

00Mode 2 10Mode 3

In Mode 1, LEDs are configured as follows:

LED_LINK = ON for Good Link, OFF for No Link

LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s

LED_ACT/LED_COL = ON for Activity, OFF for No Activity

In Mode 2, LEDs are configured as follows:

LED_LINK = ON for good Link, BLINK for Activity

LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s

LED_ACT/LED_COL = ON for Collision, OFF for No Collision

Full Duplex, OFF for Half Duplex

DP83849IF

In Mode 3, LEDs are configured as follows:

LED_LINK = ON for Good Link, BLINK for Activity

LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s

LED_ACT/LED_COL = ON for Full Duplex, OFF for Half Duplex

4:0 PHYADDR[4:0] Strap, RW PHY Address: PHY address for port.

7.2.7 10 Base-T Status/Control Register (10BTSCR)

This register is used for control and status for 10BASE -T device operation.

Table 39. 10Base-T Status/Control Register (10BTSCR), address 1Ah

Bit Bit Name Default Description

15 10BT_SERIAL Strap, RW 10Base-T Serial Mode (SNI)

1 = Enables 10Base-T Serial Mode 0 = Normal Operation Places 10 Mb/s transmit and receive functions in Serial Network

Interface (SNI) Mode of operation. Has no effect on 100 Mb/s operation.

14:12 RESERVED 0, RW RESERVED:

Must be zero.

11:9 SQUELCH 100, RW Squelch Configuration:

Used to set the Squelch ‘ON’ threshold for the receiver. Default Squelch ON is 330mV peak.

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Table 39. 10Base-T Status/Control Register (10BTSCR), address 1Ah (Continued)

Bit Bit Name Default Description

8 LOOPBACK_10_DIS 0, RW 10Base-T Loopback Disable:

In half-duplex mode, default 10BASE-T operation loops Transmit data to the Re ce iv e d at a in addition to transmitt ing the da ta on the physical medium. This is fo r consistency with earlier 10B ASE2 and 10BASE5 implementations which used a shared medium. Setting this bit disables the loopback fun ction.

This bit does not affect loopback due to setting BMCR[14].

7 LP_DIS 0, RW Normal Link Pulse Disable:

1 = Transmission of NLPs is disabled. 0 = Transmission of NLPs is enabled.

6 FORCE_LINK_10 0, RW Force 10Mb Good Link:

1 = Forced Good 10Mb Link. 0 = Normal Link Status.

5 RESERVED 0, RW RESERVED:

Must be zero.

4 POLARITY RO/LH 10Mb Polarity Status :

This bit is a duplication of bit 12 in the PHYSTS regi ste r. Both bi ts will be cleared upon a read of 10BTSCR register, but not upon a read of the PHYSTS register.

1 = Inverted Polarity detected. 0 = Correct Polarity detected.

3 RESERVED 0, RW RESERVED:

Must be zero.

2 RESERVED 1, RW RESERVED:

Must be set to one.

1 HEARTBEAT_DIS 0, RW Heartbeat Disable: This bit onl y has influence in half-duplex 10Mb

mode. 1 = Heartbeat function disabled. 0 = Heartbeat function enabled.

When the device is operating at 100Mb or configured for full duplex operation, this bit will be ignored - the heartbeat func tion is disabled.

0 JABBER_DIS 0, RW Jabber Disable:

Applicable only in 10BASE-T. 1 = Jabber function disabled. 0 = Jabber function enabled.

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7.2.8 CD Test and BIST Extensions Register (CDCTRL1)

This register controls tes t mode s for the 10B AS E-T Comm on Driv er. In addition it contains extended control and status for the packet BIST function.

Table 40. CD Test and BIST Extensions Register (CDCTRL1), address 1Bh

Bit Bit Name Default Description

15:8 BIST_ERROR_COUNT 0, RO BIST ERROR Counter:

Counts number of errored data nibbles during Packet BIST. This value will reset when Packet BIST is restarted. The counter sticks when it reaches its max count.

7:6 RESERVED 0, RW RESERVED:

Must be zero.

5 BIST_CONT_MODE 0, RW Packet BIST Continuous Mode:

Allows continuous pseudo random data transmission without any break in transmission. This can be used for transmit VOD testing. This is used in conjunction with the BIST controls in the PHYCR Register (19h). For 10Mb operation, jabber function must be dis abled, bit 0 of the 10BTSCR (1Ah), JABBER_DIS = 1.

4 CDPATTEN_10 0, RW CD Pattern Enable for 10Mb:

1 = Enabled. 0 = Disabled.

3 RESERVED 0, RW RESERVED:

Must be zero.

2 10MEG_PATT_GAP 0, RW Defines gap between data or NLP test sequences:

1 = 15 µs. 0 = 10 µs.

1:0 CDPATTSEL[1:0] 00, RW CD Pattern Select[1:0]:

If CDPATTEN_10 = 1: 00 = Data, EOP0 sequence

01 = Data, EOP1 sequence 10 = NLPs 11 = Constant Manc hester 1 s (10MHz sine w ave) for h armonic distortion testing.

DP83849IF

7.2.9 Phy Control Register 2 (PHYC R2)

This register provides additional general control.

Table 41. Phy Control Register 2 (PHYCR2), address 1Ch

Bit Bit Name Default Description

15:10 RESERVED 0, RO RESERVED: Writes ignored, read as 0.

9 SOFT_RESET 0, RW/SC Soft Reset:

Resets the entire device minus the registers - all configuration is

preserved.

1= Reset, self-clearing.

8:0 RESERVED 0, RO RESERVED: Writes ignored, read as 0.

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7.2.10 Energy Detect Control (EDCR)

This register provides control and status for the Energy Detect function.

Table 42. Energy Detect Control (EDCR), address 1Dh

Bit Bit Name Default Description

15 ED_EN Strap, RW Energy Detect Enable:

Allow Energy Detect Mode.

When Energy Detect is enabled and Auto-Negotiation is disabled

via the BMCR register, Auto -MDIX should be d isabled via the PHY

CR register.

14 ED_AUTO_UP 1, RW Energy Detect Automatic Power Up:

Automatically begin power up sequence when Energy Detect Data

Threshold value (EDCR[3:0]) is reached. Alternatively, device

could be powered up m an ual ly u si ng the ED _ MAN bi t (ECDR[12]).

13 ED_AUTO_DOWN 1, RW Energy Detect Automatic Power Down:

Automatically begin power down sequence when no energy is de-

tected. Alternatively, device could be powered down using the

ED_MAN bit (EDCR[12]).

12 ED_MAN 0, RW/SC Energy Detect Manual Power Up/Down:

Begin power up/down sequence when this bit is asserted. When

set, the Energy Detect algorithm will initi ate a change of En ergy De

tect state regardless of threshold (error or data) and timer values.

In managed applicat ions, this bit can be s et after clearin g the Ener-

gy Detect interrupt to control the timing of changing the power

state.

11 ED_BURST_DIS 0, RW Energy Detect Burst Disable:

Disable bursting of energy detect data pulses. By default, Energy

Detect (ED) transmits a burst of 4 ED d ata pulses eac h time the CD

is powered up. When bursting is disabled, only a single ED data

pulse will be send each time the CD is powered up.

10 ED_PWR_STATE 0, RO Energy Detect Power State:

Indicates current Energy Detect Power state. When set, Energy

Detect is in the powered up state. W hen cleared , Energy Dete ct is

in the powered down state. This bit is inval id when Ener gy Detec t

is not enabled. 9 ED_ERR_MET 0, RO/COR Energy Detect Error Threshold Met:

No action is automatically tak en up on rec ei pt of erro r eve nts . This

bit is informational only and would be cleared on a read. 8 ED_DATA_MET 0, RO/COR Energy Detect Data Threshold Met:

The number of data events that occu rred met or surpas sed the En-

ergy Detect Data Threshold. This bit is cleared on a read.

7:4 ED_ERR_COUNT 0001, RW Energy Detect Error Threshold:

Threshold to determine the number of energy detect error events

that should cause the d evice to t ake a ction . Inten ded to allo w aver

aging of noise that may be on the line. Counter will reset after ap-

proximately 2 seconds without any energy detect data events.

3:0 ED_DATA_COUNT 0001, RW Energy Detect Data Threshold:

Threshold to determine the number of energy detect events that

should cause the device to take actions. Intended to allow averag-

ing of noise that ma y be on th e line. Coun ter will reset after a pprox-

imately 2 seconds without any energy detect data events.

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7.3 Link Diagnostics Registers - Page 2

Page 2 Link Diagnostics Registers are accessible by setting bits [1:0] = 10 of PAGESEL (13h).

7.3.1 100Mb Length Detect Register (LEN100_DET), Page 2, address 14h

This register contains linked cable length estimation in 100Mb operation. The cable length is an estimation of the effective cable length based on the characteristics of the recovered signal. The cable length is valid only during 100Mb operation with a valid Link status indication.

Table 43. 100Mb Length Detect Register (LEN100_DET), address 14h

Bit Bit Name Default Description

15:8 RESERVED 0, RO RESERVED: Writes ignored, read as 0.

7:0 CABLE_LEN 0, RO Cable Length Estimate:

Indicates an estimate of effective cable length in meters. A value

of FF indicates cable length cannot be determined.

7.3.2 100Mb Frequency Offset Indication Register (FREQ100), Page 2, address 15h

This register returns an indication of clock frequency offset relative to the link partner. Two values can be read, the long term Frequency Offset, or a short term Frequency Control value. The Frequency Control value includes short term phase correction. The variance between the Frequency Control value and the Frequency Offset can be used as an indi cation of the amount of jitter in the system.

DP83849IF

Table 44. 100Mb Frequency Offset Indication Register (FREQ100), address 15h

Bit Bit Name Default Description

15 SAMPLE_FREQ 0, RW Sample Frequency Offset:

If Sel_FC is set to a 0, then setting this bit to a 1 will poll the DSP

for the long-term Frequency Offset value. The value will be avail

able in the Freq_Offset bits of this register.

If Sel_FC is set to a 1, then setting this bit to a 1 will poll the DSP

for the current Frequen cy Control value. The value will be avai lable

in the Freq_Offset bits of this register.

This register bit will always read back as 0.

14:9 RESERVED 0, RO RESERVED: Writes ignored, read as 0.

8 SEL_FC 0, RW Select Frequency Control:

Setting this bit to a 1 will select th e current Freq uency Control v alue

instead of the Frequency Offset. This value contains Frequency

Offset plus the short term phase correction and can be used to in

dicate amount of jit ter in the syst em. The value will be ava ilabl e in

the Freq_Offset bits of this register.

7:0 FREQ_OFFSET 0, RO Frequency Offset:

Frequency off set v alue loade d from the DSP f ollowin g as sertion of

the Sample_Freq control bit. The Frequency Offset or Frequency

Control value is a twos-complement signed value in units of ap

proximately 5.1562ppm. The range is as follows:

0x7F = +655ppm

0x00 = 0ppm

0x80 = -660ppm

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7.3.3 TDR Control Register (TDR_CTRL), Page 2, address 16h

This register contains control for the Time Domain Reflectometry (TDR) cable diagnostics. The TDR cable diagnostics sends pulses down the cable and captures reflection data to be used to estimate cable length and detect certain cabling faults.

Table 45. TDR Control Register (TDR_CTRL), address 16h

Bit Bit Name Default Description

15 TDR_ENABLE 0, RW TDR Enable:

Enable TDR mode. This forces po werup st ate to corre ct operati ng

condition for sending and receiving TDR pulses.

14 TDR_100Mb 0, RW TDR 100Mb:

Sets TDR controller to use the 100Mb Transmitter. This allows for

sending pulse widths in multiples of 8ns. Pulses in 100Mb mode

will alternate between positive pulses and negative pulses.

Default operation us es the 10Mb Link Pulse generator . Pulses may

include just the 50 ns preemphasis p ortion of the puls e or the 100ns

full link pulse (as controlled by setting TDR Width).

13 TX_CHANNEL 0, RW Transmit Channel Select:

Select transmit channel for sending pulses. Pulse can be sent on

the Transmit or Receive pair.

0 : Transmit channel

1 : Receive channel

12 RX_CHANNEL 0, RW Receive Channel Select:

Select receive channel for detecting pulses. Pulse can be moni-

tored on the Transmit or Receive pair.

0 : Transmit channel

1 : Receive channel

11 SEND_TDR 0, RW/SC Send TDR Pulse:

Setting this bit will send a TDR pulse a nd enable the monitor circuit

to capture the respons e. Thi s bit will au tom ati ca lly c le ar whe n t he

capture is complete.

10:8 TDR_WIDTH 0, RW TDR Pulse Width:

Pulse width in clocks for the transmitted pulse. In 100Mb mode,

pulses are in 8ns increments. In 10Mb mode, pulses are in 50ns

increments, bu t only 5 0ns or 10 0ns pulses can be sent. Se nding a

pulse of 0 width will not transmit a pulse, but allows for baseline

testing. 7 TDR_MIN_MODE 0, RW Min/Max Mode control:

This bit controls directio n of the pulse to be detec ted. Default looks

for a positive peak. Thres hol d an d pe ak va lue s wil l be int erpre ted

appropriately based on this bit.

0 : Max Mode, detect positive peak

1 : Min Mode, detect negative peak 6 RESERVED 0, RO RESERVED: Writes ignored, read as 0.

5:0 RX_THRESHOLD <10_0000>, RW RX Threshold:

This value provides a threshold for measurement to the start of a

peak. If Min Mode is set to 0, dat a must be great er than thi s valu e

to trigger a capture. If Min Mode is 1, data must be less than this

value to trigger a capture. Data ranges from 0x00 to 0x3F, with

0x20 as the midpoint . Positiv e dat a is grea ter than 0 x20, ne gative

data is less than 0x20.

DP83849IF

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80 83849I 2[(802.703-018687.3)-11.52.14 To Rest (IN) Paw adewh0.759 75EMC/SpaninatiMCID 1G0 J 0 -12 9 305.519 38.96071.24 1 7252.703-0.0014 T9[(802.1(0)-1868Th)13.2(is)]TJ(w)regi1s

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7.3.7 Variance Control Register (VAR_CTRL), Page 2, address 1Ah

The Variance Control and Data Registers provide control and status for the Cable Signal Quality Estimation function. The Cable Signal Q ua lity Estim ation allows a simple met hod of determining an approxim ate Sign al -to-N oi se Rati o f or the 100Mb receiver. This register contains the programmable controls and status bits for the variance computation, which can be used to make a simple Signal-to-Noise Ratio estimation.

Table 49. Variance Control Register (VAR_CTRL), address 1Ah

Bit Bit Name Default Description

15 VAR_RDY

14:4 RESERVED 0, RO RESERVED: Writes ignored, read as 0.

3 VAR_FREEZE

2:1 VAR_TIMER 0, RW Variance Computation Timer (in ms):

0 VAR_ENABLE

0, RO

0, RW

Variance Data Ready Status:

Indicates new data is available in the Variance data register. This

bit will be automatically cleared after two consecutive reads ot

VAR_DATA.

Freeze Variance Registers:

Freeze VAR_DATA register.

This bit is ensures that VAR_DATA register is frozen for software

reads. This bit is automati cally cleared after two consecut ive re ads

of VAR_DATA.

Selects the Variance computation timer period. After a new value

is written, computation is automatically restarted. New variance

Var_Timer = 0 => 2 ms timer (default)

Var_Timer = 1 => 4 ms timer

Var_Timer = 2 => 6 ms timer

Var_Timer = 3 => 8 ms timer

Time units are actually 217 cycles of an 8ns clock, or 1.048576ms.

Variance Enable:

Enable Variance computation. Off by default.

DP83849IF

7.3.8 Variance Data Register (VAR_DATA), Page 2, address 1Bh

This register cont ai ns the 32-bit Vari an ce Sum . Th e c ontents of the data a re v al id o nl y whe n VAR_RDY is asserted in the V AR_CTRL register. Upon detection of VAR_RDY asserted, software should set the VAR_FREEZE bit in the VAR_CTRL register to prevent loading of a new value into the VAR_DATA register. Since the Variance Data value is 32-bits, two reads of this register are required to get the full value.

Table 50. Variance Data Register (VAR_DATA), address 1Bh

Bit Bit Name Default Description

15:0 VAR_DATA 0, RO Variance Data:

Two reads are required to re turn the full 32-bit Variance Sum value.

Following setting the VAR_FREEZE control, the first read of this

read will return the high 16 bits of Variance data.

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7.3.9 Link Quality Monitor Register (LQMR), Page 2, address 1Dh

This register contains the controls for the Link Quality Monitor function. The Link Quality Monitor provides a mechanism for programm ing a set of thr esholds fo r DSP parameter s. If the thre sholds are vi olated, an interrupt w ill be asser ted if enabled in the MIS R. Mon ito r c on trol and status are a va ila ble i n t his re gis te r, while the LQDR register contro ls rea d/wri te access to threshold value s and cu rrent p aramet er value s. Read ing of LQMR regis ter clears w arning bits and re-arms th e interrupt generation. In add ition, th is registe r prov ides a mecha nims for al lowi ng auto matic reset of th e 100Mb link ba sed on the Link Quality Monitor status

Bit Bit Name Default Description

15 LQM_ENABLE 0, RW Link Quality Monitor Enable:

14:10 RESERVED 0, RO RESERVED: Writes ignored, read as 0.

9 FC_HI_WARN 0, RO/COR Frequency Control High Warning:

8 FC_LO_WARN 0, RO/COR Frequency Control Low Warning:

7 FREQ_HI_WARN 0, RO/COR Frequency Offset High Warning:

6 FREQ_LO_WARN 0, RO/COR Frequency Offset Low Warning:

5 DBLW_HI_WARN 0, RO/COR DBLW High Warning:

4 DBLW_LO_WARN 0, RO/COR DBLW Low Warning:

3 DAGC_HI_WARN 0, RO/COR DAGC High Warning:

2 DAGC_LO_WARN 0, RO/COR DAGC Low Warning:

1 C1_HI_WARN 0, RO/COR C1 High Warning:

0 C1_LO_WARN 0, RO/COR C1 Low Warning:

Table 51. Link Quality Monitor Register (LQMR), address 1Dh

Enables the Link Qual ity Monitor . The enable is quali fied by having

a valid 100Mb link . In additi on, the indi vidual thre sholds can b e dis

abled by setting to the max or min values.

This bit indicates the Frequency Control High Threshold was ex-

ceeded. This register bit will be cleared on read.

This bit indicates the Frequency Control Low Threshold was ex-

ceeded. This register bit will be cleared on read.

This bit indicates the Frequency O ffset High Threshold was ex-

ceeded. This register bit will be cleared on read.

This bit indicates the Fre quency Offset Lo w Threshold was exce ed-

ed. This register bit will be cleared on read.

This bit indicates the DBLW High Threshold was exceeded. This

This bit indicates the DBLW Low Threshold was exceeded. This

This bit indicates the DAGC High Threshold was exceeded. This

This bit indicates the DAGC Low Threshold was exceeded. This

This bit indicates the DEQ C1 High Threshold w as exceeded. Th is

This bit indica tes t he DE Q C1 Low Thre shold was exce ede d. T his

DP83849IF

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7.3.10 Link Quality Data Register (LQDR), Page 2

This register provides rea d/w ri te co ntro l of thre sh old s fo r the 100 Mb Lin k Qu al ity Monito r func tio n. The reg is ter al so pr ovides a mechanism for reading current adapted parameter values. Threshold values may not be written if the device is powered-down

Bit Bit Name Default Description

15:14 RESERVED 0, RO RESERVED: Writes ignored, read as 0.

13 SAMPLE_PARAM 0, RW Sample DSP Parameter:

12 WRITE_LQ_THR 0, RW Write Link Quality Threshold:

11:9 LQ_PARAM_SEL 0, RW Link Quality Parameter Select:

Table 52. Link Quality Data Register (LQDR), address 1Eh

Setting this bit to a 1 enables reading of current parameter values

and initiates sampl ing of the p arameter valu e. The param eter to be

read is selected by the LQ_PARAM_SEL bits.

Setting this bit will ca use a wr ite to the Thres hold re giste r selec ted

by LQ_PARAM_SEL and LQ_THR_SEL. The data written is con-

tained in LQ_THR_DATA. This bit will always read back as 0.

This 3-bit field selec ts the Link Quality Parameter . This field is used

for sampling current pa rameter values as well as for reads/ writes to

Threshold values. The following encodings are available:

000: DEQ_C1

001: DAGC

010: DBLW

01 1: Freq uen cy Of fs et

DP83849IF

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8.0 Electrical Specifications

Note: All parameters are guaranteed by test, statistical analysis or design.

DP83849IF

Absolute Maximum Ratin gs

Supply Voltage (VCC) -0.5 V to 4.2 V DC Input Voltage (VIN) -0.5V to VCC + 0.5V DC Output Voltage (V Storage Temperature (T Lead Temp. (TL)

) -0.5V to VCC + 0.5V

OUT

)

STG

-65oC to 150°C 260 °C

(Soldering, 10 sec.) ESD Rating

= 1.5k, C

ZAP

= 100 pF)

ZAP

4.0 kV

Thermal Characteristic

Maximum Case Temperature @ 1.0 W Theta Junction to Case (Tjc) @ 1.0 W

Theta Junction to Ambient (Tja) degrees Celsius/Watt - No Airflow @ 1.0 W

Recommended Operating Conditions

Supply voltage (VCC) 3.3 Volts + 0.3V Industrial - Ambient Temperature (TA)

-40 to 85 °C

Power Dissipation (PD) 594 mW

Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits.

Max Units

108 °C

17.3 °C / W 53 °C / W

8.1 DC Specs

Symbol Pin Types Parameter Conditions Min Typ Max Units

TPTD_100

TPTDsym

TPTD_10

FXTD_100

I/O

I/O,

PMD Output

Pair

PMD Output

Pair

PMD Output

Pair

PMD Output

Pair

Input High Voltage Nominal V

2.0 V

Input Low Voltage 0.8 V

Input High Current VIN = V

10 µA

Input Low Current VIN = GND 10 µA

Output Low

IOL = 4 mA 0.4 V

Voltage Output High

IOH = -4 mA Vcc - 0.5 V

Voltage TRI-STATE

Leakage 100M Transmit

OUT

= V

+ 10 µA

0.95 1 1.05 V

Voltage 100M Transmit

+ 2 %

Voltage Symmetry 10M Transmit

2.2 2.5 2.8 V

Voltage FX100M Transmit

.3 .5 .93 V

Voltage

IN1

OUT1

I CMOS Input

Capacitance

O CMOS Output

Capacitance

8 pF

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8.1 DC Specs (Continued)

Symbol Pin Types Parameter Conditions Min Typ Max Units

DP83849IF

TH1

dd100

dd10

THon

THoff

PMD Input

Pair

100BASE-TX Signal detect turnon threshold

PMD Input

Pair

100BASE-TX Signal detect turnoff threshold

PMD Input

Pair

10BASE-T Receive Threshold

Supply 100BASE-TX

(Full Duplex)

Supply 10BASE-T

(Full Duplex)

Supply Power Down

Mode

1000 mV diff pk-pk

200 mV diff pk-pk

585 mV

180 mA

CLK2MAC disabled 9.5 mA

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8.2 AC Specs

8.2.1 Power U p Timing

Vcc

X1 clock

Hardware

RESET_N

DP83849IF

T2.1.1

32 clocks

MDC

T2.1.2

Latch-In of Hardware Configuration Pins

input Dual Function Pins Become Enabled As Outputs

Parameter Description Notes Min Typ Max Units

T2.1.1 Post Power Up Stabilization

time prior to M DC preamble for register accesses

T2.1.2 Hardware Configuration Latch-

in Time from power up

T2.1.3 Hardware Configuration pins

transition to output drivers

MDIO is pulled h ig h fo r 32 -bi t s eria l ma nagement initializat ion

X1 Clock must be stable for a min. of 167ms at power up.

Hardware Configuration Pins are described in the Pin Description sec tio n

X1 Clock must be stable for a min. of 167ms at power up.

T2.1.3

output

167 ms

50 ns

Note: In RMII Mode, the minimum Post Power up Stabilization and Hardware Configuration Latch-in times are 84ms.

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8.2 AC Specs (Continued)

8.2.2 Reset Timing

Vcc

X1 clock

Hardware

RESET_N

DP83849IF

T2.2.1

T2.2.4

32 clocks

MDC

T2.2.2

Latch-In of Hardware Configuration Pins

input Dual Function Pins Become Enabled As Outputs

Parameter Description Notes Min Typ Max Units

T2.2.1 Post RESET Stabili zation time

prior to MDC preamble fo r re gister accesses

T2.2.2 Hardware Configuration Latch-

in Time from the Deassertion of RESET (either soft or hard)

MDIO is pulled high for 32-bit serial management initializat ion

Hardware Configuration Pins are described in the Pin Description sec tio n

T2.2.3

output

3 µs

T2.2.3 Hardware Configuration pins

transition to output drivers

T2.2.4 RESET pulse width X1 Clock must be stable for at m in. of 1us

during RESET pulse low time.

Note: It is important to choose pull-up and / or pu ll- dow n resi sto rs fo r eac h of the hardware configuration pins that provide fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver.

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50 ns

1 µs

8.2 AC Specs (Continued)

8.2.3 MII Serial Management Timing

MDC

MDIO (output)

MDC

DP83849IF

T2.3.1

T2.3.4

T2.3.2 T2.3.3

MDIO (input)

Parameter Description Notes Min Typ Max Units

T2.3.1 MDC to MDIO (Output) Delay Time 0 30 ns T2.3.2 MDIO (Input) to MDC Setup Time 10 ns T2.3.3 MDIO (Input) to MDC Hold Time 10 ns T2.3.4 MDC Frequency 2.5 25 MHz

8.2.4 100 Mb/s MII Transmit Timing

T2.4.1

TX_CLK

T2.4.2

TXD[3:0]

TX_EN

Valid Data

T2.4.1

T2.4.3

Valid Data

Parameter Description Notes Min Typ Max Units

T2.4.1 TX_CLK High/Low Time 100 Mb/s Normal mode 16 20 24 ns T2.4.2 TXD[3:0], TX_EN Data Setup to TX_CLK 100 Mb/s Normal mode 10 ns

T2.4.3 TXD[3:0], TX_EN Data Hold from TX_CLK 100 Mb/s Normal mode 0 ns

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8.2 AC Specs (Continued)

8.2.5 100 Mb/s MII Receive Timing

DP83849IF

T2.5.1

RX_CLK

T2.5.1

T2.5.2

RXD[3:0] RX_DV RX_ER

Parameter Description Notes Min Typ Max Units

T2.5.1 RX_CLK High/Low Time 100 Mb/s Normal mode 16 20 24 ns T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode 10 30 ns

Note: RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated.

8.2.6 100BASE-TX and 100BASE-FX MII Transmit Packet Latency Timing

Valid Data

TX_CLK

TX_EN

TXD

PMD Output Pair

Parameter Description Notes Min Typ Max Units

T2.6.1 TX_CLK to PMD Output Pair

Latency

Note: For Normal mode, latency is determ ined by m easuri ng the time from the fir st rising edge of TX_ CLK o ccurring aft er the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.

100BASE-TX and 100BASE-FX modes 5 bits

T2.6.1

(J/K) IDLE DATA

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8.2 AC Specs (Continued)

8.2.7 100BASE-TX and 100BASE-FX MII Transmit Packet Deassertion Timing

TX_CLK

TX_EN

TXD

T2.7.1

DP83849IF

PMD Output Pair

(T/R) DATA IDLE

Parameter Description Notes Min Typ Max Units

T2.7.1 TX_CLK to PMD Output Pair

100BASE-TX and 100BASE-FX modes 5 bits

Deassertion

Note: Deassertion is determined by measuring the time from the first ris ing ed ge o f TX_ CLK oc curring after the deass er tion of TX_EN to the first bit o f the “T” cod e group as output from the PMD Output Pair . 1 bi t time = 10 ns in 100 M b/s mode.

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8.2 AC Specs (Continued)

DP83849IF

8.2.8 100BASE-TX Transmit Timing (t

+1 rise

PMD Output Pair

eye pattern

& Jitter)

R/F

T2.8.1

+1 fall

T2.8.1

-1 fall

T2.8.1

-1 rise

T2.8.1

Parameter Description Notes Min Typ Max Units

T2.8.1 100 Mb/s PMD Output Pair tR

and t

100 Mb/s tR and tF Mismatch 500 ps

T2.8.2 100 Mb/s PMD Output Pair

Transmit Jitter

Note: Normal Mismatch is the difference between the maximum and minimum of all rise and fall times Note: Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude

3 4 5 ns

1.4 ns

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8.2 AC Specs (Continued)

8.2.9 100BASE-TX and 100BASE-FX MII Receive Packet Latency Timing

DP83849IF

PMD Input Pair

CRS

RXD[3:0]

RX_DV RX_ER

Parameter Description Notes Min Typ Max Units

T2.9.1 Carrier Sense ON Delay 100BASE-TX mode

T2.9.2 Receive Data Latency 100BASE-TX mode

Note: Carrier Sense On Delay is determin ed by meas uring the ti me fro m the first b it of the “J” code group to the asse rtion of Carrier Sense.

Note: 1 bit time = 10 ns in 100 Mb/s mode Note: PMD Input Pair voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.

IDLE

T2.9.1

(J/K)

T2.9.2

100BASE-FX mode

Data

20 10 24 14

bits

8.2.10 100BASE-TX and 100BASE-FX MII Receive Packet Deassertion Timing

PMD Input Pair

CRS

Parameter Description Notes Min Typ Max Units

T2.10.1 Carrier Sense OFF Delay 100BASE-TX mode

Note: Carrier Sense Off Delay is determin ed by measu ring th e time from the fir st bit o f the “T” c ode g roup to t he d eassertion of Carrier Sense.

Note: 1 bit time = 10 ns in 100 Mb/s mode

DATA

(T/R)

T2.10.1

100BASE-FX mode

IDLE

24 14

bits

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8.2 AC Specs (Continued)

8.2.11 10 Mb/s MII Transmit Timing

DP83849IF

T2.11.1

TX_CLK

T2.11.2

TXD[3:0]

TX_EN

Parameter Description Notes Min Typ Max Units

T2.11.1 TX_CLK High/Low Time 10 Mb/s MII mode 190 200 210 ns T2.11.2 TXD[3:0], TX_EN Data Setup to TX_CLK fall 10 Mb/s MII mode 25 ns T2.11.3 TXD[3:0], TX_EN Data Hold from TX_CLK rise 10 Mb/s MII mode 0 ns

Note: An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII signals are sampled on the falling edge of TX_CLK.

8.2.12 10 Mb/s MII Receive Timing

Valid Data

T2.11.1

T2.11.3

T2.12.1 T2.12.1

RX_CLK

T2.12.2

RXD[3:0] RX_DV

Parameter Description Notes Min Typ Max Units

T2.12.1 RX_CLK High/Low Time 160 200 240 ns T2.12.2 RX_CLK to RXD[3:0], RX_DV Delay 10 Mb/s MII mode 100 ns T2.12.3 RX_CLK rising edge delay from RXD[3:0],

RX_DV Valid

Note: RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated.

T2.12.3

Valid Data

10 Mb/s MII mode 100 ns

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8.2 AC Specs (Continued)

8.2.13 10 Mb /s Serial Mode Transmit Timing

DP83849IF

T2.13.1

TX_CLK

T2.13.3

TXD[0] TX_EN

Parameter Description Notes Min Typ Max Units

T2.13.1 TX_CLK High Time 10 Mb/s Serial mode 20 25 30 ns T2.13.2 TX_CLK Low Time 10 Mb/s Serial mode 70 75 80 ns T2.13.3 TXD_0, TX_EN Data Setup to TX_CLK rise 10 Mb/s Serial mode 25 ns T2.13.4 TXD_0, TX_EN Data Hold from TX_CLK rise 10 Mb/s Serial mode 0 ns

8.2.14 10 Mb/s Serial Mode Receive Timing

Valid Data

T2.13.4

T2.13.2

T2.14.1

RX_CLK

T2.14.2

RXD[0] RX_DV

Parameter Description Notes Min Typ Max Units

T2.14.1 RX_CLK High/Low Time 35 50 65 ns T2.14.2 RX_CLK fall to RXD_0, RX_DV Delay 10 Mb/s Serial mode -10 10 ns

Note: RX_CLK may be held high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated.

Valid Data

T2.14.1

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8.2 AC Specs (Continued)

8.2.15 10B ASE-T Transmit Timing (Start of Packet)

TX_CLK

TX_EN

TXD

T2.15.2

PMD Output Pair

T2.15.1

Parameter Description Notes Min Typ Max Units

T2.15.1 Transmit Output Delay from the

Falling Edge of TX_CLK

T2.15.2 Transmit Output Delay from the

Rising Edge of TX_CLK

10 Mb/s MII mode 3.5 bits

10 Mb/s Serial mode 3.5 bits

DP83849IF

Note: 1 bit time = 100 ns in 10Mb/s.

8.2.16 10BASE-T Transmit Timing (End of Packet)

TX_CLK

TX_EN

PMD Output Pair

Parameter Description Notes Min Typ Max Units

T2.16.1 End of Packet High Time

(with ‘0’ ending bit)

T2.16.2 End of Packet High Time

(with ‘1’ ending bit)

T2.16.2

250 300 ns

T2.16.1

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8.2 AC Specs (Continued)

8.2.17 10BASE-T Receive Timing (Start of Packet)

TPRD±

T2.17.1

CRS

RX_CLK

T2.17.2

RX_DV

RXD[3:0]

DP83849IF

1st SFD bit decoded

T2.17.3

Parameter Description Notes Min Typ Max Units

T2.17.1 Carrier Sense Turn On Delay (PMD

Input Pair to CRS) T2.17.2 RX_DV Latency 10 bits T2.17.3 Receive Data Latency Me asurement shown from SFD 8 bits

Note: 10BASE-T RX_DV Latency is measured from first bit of preamble on the wire to the assertion of RX_DV Note: 1 bit time = 100 ns in 10 Mb/s mode.

8.2.18 10BASE-T Receive Timing (End of Packet)

630 1000 ns

Parameter Description Notes Min Typ Max Units

T2.18.1 Carrier Sense Turn Off Delay 1.0 µs

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8.2 AC Specs (Continued)

8.2.19 10 Mb/s Heartbeat Timing

TX_EN

DP83849IF

TX_CLK

T2.19.1

COL

Parameter Description Notes Min Typ Max Units

T2.19.1 CD Heartbeat Delay 10 Mb/s half-duplex mode 1200 ns T2.19.2 CD Heartbeat Duration 10 Mb/s half-duplex mode 1000 ns

8.2.20 10 Mb /s Jabber Timing

TXE

T2.20.1

PMD Output Pair

T2.19.2

T2.20.2

COL

Parameter Description Notes Min Typ Max Units

T2.20.1 Jabber Activation Time 85 ms T2.20.2 Jabber Deactivation Time 500 ms

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8.2 AC Specs (Continued)

8.2.21 10BASE-T Normal Link Pulse Timing

T2.21.2

T2.21.1

Normal Link Pulse(s)

Parameter Description Notes Min Typ Max Units

T2.21.1 Pulse Width 100 ns T2.21.2 Pulse Period 16 ms

Note: These specifications represent transmit timings.

8.2.22 Auto-Negotiation Fast Link Pulse (FLP) Timing

T2.22.2

DP83849IF

T2.22.3

T2.22.1

Fast Link Pulse(s)

clock pulse

T2.22.4

FLP Burst FLP Burst

Parameter Description Notes Min Typ Max Units

T2.22.1 Clock, Data Pulse Width 100 ns T2.22.2 Clock Pulse to Clock Pulse

T2.22.3 Clock Pulse to Data Pulse

T2.22.4 Burst Width 2 ms T2.22.5 FLP Burst to FLP Burst Period 16 ms

Period

data pulse

T2.22.5

Data = 1 62 µs

clock pulse

T2.22.1

125 µs

Note: These specifications represent transmit timings.

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8.2 AC Specs (Continued)

8.2.23 100BASE-TX Signal Detect Timing

PMD Input Pair

T2.23.1

T2.23.2

SD+ internal

Parameter Description Notes Min Typ Max Units

T2.23.1 SD Internal Turn-on Time 1 ms T2.23.2 SD Internal Turn-off Time 350 µs

Note: The signal amplitude on PMD Input Pair must be TP-PMD compliant.

DP83849IF

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8.2 AC Specs (Continued)

8.2.24 100 Mb/s Internal Loopback Timing

TX_CLK

TX_EN

TXD[3:0]

DP83849IF

CRS

RX_CLK

RX_DV

RXD[3:0]

Parameter Description Notes Min Typ Max Units

T2.24.1 TX_EN to RX_DV Loopback 100 Mb/s internal loopback mode 240 ns

Note1: Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time” of up to 550 µs during which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is based on device delays after the initial 550µs “dead-time”.

Note2: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.

T2.24.1

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National Semiconductor DP83849IF Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

1.0 Pin Descriptions

1.1 Serial Management Interface

1.2 MAC Data Interface

1.3 Clock Interface

1.4 LED Interface

1.5 JTAG Interface

1.6 Reset and Power Down

1.7 Strap Options

1.8 10 Mb/s and 100 Mb/s PMD Interface

1.9 Special Connections

1.10 Power Supply Pins

1.11 Package Pin Assignments

2.0 Configuration

2.1 Media Configuration

2.2 Auto-Negotiation

2.2.1 Auto-Negotiation Pin Control

2.2.2 Auto-Negotiation Register Control

2.2.3 Auto-Negotia tion Para llel Detection

2.2.5 Enabling Auto-Negotiation via Software

2.2.6 Auto-Negotiation Complete Time

2.3 Auto-MDIX

2.2.4 Auto-Negotiation Rest art

2.4.1 MII Isolate Mode

2.5 LED Interface

2.5.1 LEDs

2.5.2 LED Direct Control

2.6 Half Duplex vs. Full Duplex

2.7 Internal Loopback

2.8 BIST

3.0 MAC Interface

3.2 Reduced MII Interface

3.3 10 Mb Serial Network Interface (SNI)

3.4 Single Clock MII Mode

3.5 Flexible MII Port Assignment

3.5.1 RX MII Port Mapping

3.5.2 TX MII Port Mapping

3.5.3 Common Flexible MII Port Configurations

3.5.4 Strapped Extender or Media Converter Mode

3.5.5 Notes and Restrictions

3.6 802.3u MII Serial Management Interface

3.6.1 Seri al Managemen t Register Access

3.6.2 Serial Management Access Protocol

3.6.3 Serial Management Preamble Suppression

3.6.4 Simultaneous Register Write

4.0 Architecture

4.1 100BASE-TX TRANSMITTER

4.1.1 Code-group Encoding and Injection

4.1.2 Scrambler

4.2 100BASE-TX RECEIVER

4.1.3 NRZ to NRZI Encoder

4.1.4 Binary to MLT-3 Convertor

4.2.1 Analog Front End

4.2.2 Digital Signal Processor

4.2.3 Signal Detect

4.2.4 MLT-3 to NRZI Decoder

4.2.5 NRZI to NRZ

4.2.6 Serial to Parallel

4.2.7 Descrambler

4.2.10 100BASE-TX Link Integrity Monitor

4.2.11 Bad SSD Detection

4.3 100BASE-FX Operation

4.2.8 Code-group Alignment

4.2.9 4B/5B Decoder

4.3.1 100BASE-FX Transmit

4.3.2 100BASE-FX Receive

4.3.3 Far-End Fault

4.4 10BASE-T TRANSCEIVER MODULE

4.4.1 Operational Modes

4.4.2 Smart Squelch

4.4.3 Collision Detection and SQE

4.4.4 Carrier Sense

4.4.5 Normal Link Pulse Detection/Generation

4.4.7 Automatic Link Polarity Detection and Correcti on

4.4.8 Transmit and Receive Filtering

4.4.9 Transmitter

4.4.6 Jabber Function