Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver
General Description
The DP83848I is a robust fully featured 10/100 single
port Physical Layer device offering low power consumption, including several intelligent power down
states. These low power modes increase overall product reliability due to decreased power dissipation. Supporting multiple intelligent power modes allows the
application to use the absolute minimum amount of
power needed for operation. In addition to low power,
the DP83848I is optimized for cable length performance far exceeding IEEE specifications.
The DP83848I includes a 25MHz clock out. This
means that the application can be designed with a
minimum of external parts, which in turn results in the
lowest possible total cost of the solution.
The DP83848I easily interfaces to twisted pair media
via an external transformer and fully supports JTAG
IEEE specification 1149.1 for ease of manufacturing.
Additionally both MII and RMII are supported ensuring
ease and flexibility of design.
The DP83848I features integrated sublayers to support both 10BASE-T and 100BASE-TX Ethernet protocols, which ensures compatibility and interoperability
with all other standards based Ethernet solutions.
The DP83848I is offered in a small form factor (48 pin
LQFP) so that a minimum of board space is needed.
Applications
• High End Peripheral Devices
• Industrial Controls and Factory Automation
• General Embedded Applications
Features
• Low-power 3.3V, 0.18µm CMOS technology
• Low power consumption < 270mW Typical
• 3.3V MAC Interface
• Auto-MDIX for 10/100 Mb/s
• Energy Detection Mode
• 25 MHz clock out
• SNI Interface (configurable)
• RMII Rev. 1.2 Interface (configurable)
• MII Serial Management Interface (MDC and MDIO)
• IEEE 802.3u MII
• IEEE 802.3u Auto-Negotiation and Parallel Detection
• IEEE 802.3u ENDEC, 10BASE-T transceivers and filters
• IEEE 802.3u PCS, 100BASE-TX transceivers and filters
The DP83848I pins are classified into the following interface categories (each interface is described in the sections
that follow):
— Serial Management Interface
— MAC Data Interface
— Clock Interface
— LED Interface
—JTAG Interface
— Reset and Power Down
— Strap Options
— 10/100 Mb/s PMD Interface
— Special Connect Pins
— Power and Ground pins
1.1 Serial Management Interface
Signal NameTypePin #Description
MDCI31MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO
MDIOI/O30MANAGEMENT DATA I/O: Bi-directional management instruc-
Note: Strapping pin option. Please see Section 1.7 for strap
definitions.
All DP83848I signal pins are I/O cells regardless of the particular use. The definitions below define the functionality of
the I/O cells for each pin.
ternal pull-ups or pull-downs. If the default
strap value is needed to be changed then an
external 2.2 kΩ resistor should be used.
Please see
management data input/output serial interface which may be
asynchronous to transmit and receive clocks. The maximum clock
rate is 25 MHz with no minimum clock rate.
tion/data signal that may be sourced by the station management
entity or the PHY. This pin requires a 1.5 kΩ pullup resistor.
Section 1.7 for details.)
DP83848I
1.2 MAC Data Interface
Signal NameTypePin #Description
TX_CLKO1MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100
Mb/s mode or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz
reference clock.
Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive.
SNI TRANSMIT CLOCK: 10 MHz Transmit clock output in 10 Mb
SNI mode. The MAC should source TX_EN and TXD_0 using this
clock.
TX_EN I, PD2MII TRANSMIT ENABLE: Active high input indicates the pres-
ence of valid data inputs on TXD[3:0].
RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0].
SNI TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD_0.
TXD_0
TXD_1
TXD_2
TXD_3
I
S, I, PD
3
4
5
6
MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0],
that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s
mode or 25 MHz in 100 Mb/s mode).
RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0],
that accept data synchronous to the 50 MHz reference clock.
SNI TRANSMIT DATA: Transmit data SNI input pin, TXD_0, that
accept data synchronous to the TX_CLK (10 MHz in 10 Mb/s SNI
mode).
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Signal NameTypePin #Description
RX_CLKO38MII RECEIVE CLOCK: Provides the 25 MHz recovered receive
DP83848I
RX_DV S, O, PD39MII RECEIVE DATA VALID: Asserted high to indicate that valid
RX_ERS, O, PU41MII RECEIVE ERROR: Asserted high synchronously to RX_CLK
RXD_0
RXD_1
RXD_2
RXD_3
CRS/CRS_DVS, O, PU40MII CARRIER SENSE: Asserted high to indicate the receive me-
COLS, O, PU42MII COLLISION DETECT: Asserted high to indicate detection of
S, O, PD43
44
45
46
clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.
Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive.
SNI RECEIVE CLOCK: Provides the 10 MHz recovered receive
clocks for 10 Mb/s SNI mode.
data is present on the corresponding RXD[3:0]. MII mode by de
fault with internal pulldown.
RMII Synchronous Receive Data Valid: This signal provides the
RMII Receive Data Valid indication independent of Carrier Sense.
This pin is not used in SNI mode.
to indicate that an invalid symbol has been detected within a re
ceived packet in 100 Mb/s mode.
RMII RECEIVE ERROR: Assert high synchronously to X1 whenever it detects a media error and RXDV is asserted in 100 Mb/s
mode.
This pin is not required to be used by a MAC, in either MII or RMII
mode, since the Phy is required to corrupt data on a receive error.
This pin is not used in SNI mode.
MII RECEIVE DATA: Nibble wide receive data signals driven synchronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2.5 MHz
for 10 Mb/s mode). RXD[3:0] signals contain valid data when
RX_DV is asserted.
RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1 clock, 50 MHz.
SNI RECEIVE DATA: Receive data signal, RXD_0, driven synchronously to the RX_CLK. RXD_0 contains valid data when CRS
is asserted. RXD[3:1] are not used in this mode.
dium is non-idle.
RMII CARRIER SENSE/RECEIVE DATA VALID: This signal
combines the RMII Carrier and Receive Data Valid indications.
For a detailed description of this signal, see the RMII Specifica
tion.
SNI CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. It is used to frame valid receive data on the
RXD_0 signal.
a collision condition (simultaneous transmit and receive activity)
in 10 Mb/s and 100 Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with heartbeat enabled this
pin is also asserted for a duration of approximately 1µs at the end
of transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is no heartbeat function during 10
Mb/s full duplex operation.
RMII COLLISION DETECT: Per the RMII Specification, no COL
signal is required. The MAC will recover CRS from the CRS_DV
signal and use that along with its TX_EN signal to determine col
lision.
SNI COLLISION DETECT: Asserted high to indicate detection of
a collision condition (simultaneous transmit and receive activity)
in 10 Mb/s SNI mode.
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1.3 Clock Interface
Signal NameType Pin #Description
X1 I34CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock
X2O33CRYSTAL OUTPUT: This pin is the primary clock reference out-
25MHz_OUTO2525 MHz CLOCK OUTPUT:
reference input for the DP83848I and must be connected to a 25
MHz 0.005% (
ther an external crystal resonator connected across pins X1 and
X2, or an external CMOS-level oscillator source connected to pin
X1 only.
RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode and must be connected to a 50 MHz
0.005% (
put to connect to an external 25 MHz crystal resonator device.
This pin must be left unconnected if an external CMOS oscillator
clock source is used.
In MII mode, this pin provides a 25 MHz clock output to the system.
In RMII mode, this pin provides a 50 MHz clock output to the system.
This allows other devices to use the reference clock from the
DP83848I without requiring additional clock sources.
+50 ppm) clock source. The DP83848I supports ei-
+50 ppm) CMOS-level oscillator source.
DP83848I
1.4 LED Interface
See Table 3 for LED Mode Selection.
Signal NameTypePin #Description
LED_LINKS, O, PU28LINK LED: In Mode 1, this pin indicates the status of the LINK.
LED_SPEEDS, O, PU27SPEED LED: The LED is ON when device is in 100 Mb/s and OFF
LED_ACT/COLS, O, PU26ACTIVITY LED: In Mode 1, this pin is the Activity LED which is
The LED will be ON when Link is good.
LINK/ACT LED: In Mode 2 and Mode 3, this pin indicates transmit
and receive activity in addition to the status of the Link. The LED
will be ON when Link is good. It will blink when the transmitter or
receiver is active.
when in 10 Mb/s. Functionality of this LED is independent of mode
selected.
ON when activity is present on either Transmit or Receive.
COLLISION/DUPLEX LED: In Mode 2, this pin by default indicates Collision detection. For Mode 3, this LED output may be
programmed to indicate Full-duplex status instead of Collision.
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1.5 JTAG Interface
DP83848I
TCKI, PU8TEST CLOCK
TDII, PU12TEST DATA INPUT
TDOO9TEST OUTPUT
TMSI, PU10TEST MODE SELECT
TRST#I, PU11TEST RESET: Active low asynchronous test reset.
Signal NameTypePin #Description
This pin has a weak internal pullup.
This pin has a weak internal pullup.
This pin has a weak internal pullup.
This pin has a weak internal pullup.
1.6 Reset and Power Down
Signal NameTypePin #Description
RESET_NI, PU29RESET: Active Low input that initializes or re-initializes the
PWR_DOWN/INTI, OD, PU7See Section 5.5 for detailed description.
DP83848I. Asserting this pin low for at least 1 µs will force a reset
process to occur. All internal registers will re-initialize to their de
fault states as specified for each bit in the Register Block section.
All strap options are re-initialized as well.
The default function of this pin is POWER DOWN.
POWER DOWN: The pin is an active low input in this mode and
should be asserted low to put the device in a Power Down mode.
INTERRUPT: The pin is an open drain output in this mode and will
be asserted low when an interrupt condition occurs. Although the
pin has a weak internal pull-up, some applications may require an
external pull-up resister. Register access is required for the pin to
be used as an interrupt mechanism. See
Mechanism for more details on the interrupt mechanisms.
Section 5.5.2 Interrupt
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1.7 Strap Options
The DP83848I uses many of the functional pins as strap
options. The values of these pins are sampled during reset
and used to strap the device into specific modes of opera
tion. The strap option pin assignments are defined below.
The functional pin name is indicated in parentheses.
Signal NameType Pin #Description
PHYAD0 (COL)
PHYAD1 (RXD_0)
PHYAD2 (RXD_1)
PHYAD3 (RXD_2)
PHYAD4 (RXD_3)
S, O, PU
S, O, PD
42
43
44
45
46
PHY ADDRESS [4:0]: The DP83848I provides five PHY address
pins, the state of which are latched into the PHYCTRL register at
system Hardware-Reset.
The DP83848I supports PHY Address strapping values 0
(<00000>) through 31 (<11111>). A PHY Address of 0 puts the part into the MII Isolate Mode. The MII isolate mode must be se
lected by strapping Phy Address 0; changing to Address 0 by register write will not put the Phy in the MII isolate mode. Please refer
to section 2.3 for additional information.
PHYAD0 pin has weak internal pull-up resistor.
PHYAD[4:1] pins have weak internal pull-down resistors.
A 2.2 kΩ resistor should be used for pull-down or pull-up to
change the default strap option. If the default option is
required, then there is no need for external pull-up or pull
down resistors. Since these pins may have alternate func
tions after reset is deasserted, they should not be connected directly to VCC or GND.
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Signal NameType Pin #Description
AN_EN (LED_ACT/COL)
AN_1 (LED_SPEED)
AN_0 (LED_LINK)
S, O, PU26
27
28
Auto-Negotiation Enable: When high, this enables Auto-Negotiation with the capability set by ANO and AN1 pins. When low, this
puts the part into Forced Mode with the capability set by AN0 and
AN1 pins.
AN0 / AN1: These input pins control the forced or advertised operating mode of the DP83848I according to the following table.
The value on these pins is set by connecting the input pins to
GND (0) or V
NEVER be connected directly to GND or VCC.
The value set at this input is latched into the DP83848I at Hardware-Reset.
The float/pull-down status of these pins are latched into the Basic
Mode Control Register and the Auto_Negotiation Advertisement
Register during Hardware-Reset.
The default is 111 since these pins have internal pull-ups.
(1) through 2.2 kΩ resistors. These pins should
CC
AN_EN AN1 AN0Forced Mode
00010BASE-T, Half-Duplex
00110BASE-T, Full-Duplex
010100BASE-TX, Half-Duplex
011100BASE-TX, Full-Duplex
AN_EN AN1 AN0Advertised Mode
10010BASE-T, Half/Full-Duplex
101100BASE-TX, Half/Full-Duplex
11010BASE-T Half-Duplex
100BASE-TX, Half-Duplex
11110BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
DP83848I
MII_MODE (RX_DV)
SNI_MODE (TXD_3)
LED_CFG (CRS)S, O, PU40LED CONFIGURATION: This strapping option determines the
MDIX_EN (RX_ER)S, O, PU41MDIX ENABLE: Default is to enable MDIX. This strapping option
S, O, PD39
MII MODE SELECT: This strapping option pair determines the
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operating mode of the MAC Data Interface. Default operation (No
pull-ups) will enable normal MII Mode of operation. Strapping
MII_MODE high will cause the device to be in RMII or SNI mode
of operation, determined by the status of the SNI_MODE strap.
Since the pins include internal pull-downs, the default values are
0.
The following table details the configurations:
MII_MODE SNI_MODEMAC Interface
Mode
0XMII Mode
10RMII Mode
1110 Mb SNI Mode
mode of operation of the LED pins. Default is Mode 1. Mode 1 and
Mode 2 can be controlled via the strap option. All modes are con
figurable via register access.
SeeTable 3 for LED Mode Selection.
disables Auto-MDIX. An external pull-down will disable AutoMDIX mode.
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1.8 10 Mb/s and 100 Mb/s PMD Interface
DP83848I
TD-, TD+I/O16, 17Differential common driver transmit output (PMD Output Pair).
These differential outputs are automatically configured to either
10BASE-T or 100BASE-TX signaling.
In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair.
These pins require 3.3V bias for operation.
puts are automatically configured to accept either 100BASE-TX
or 10BASE-T signaling.
In Auto-MDIX mode of operation, this pair can be used as the
Transmit Output pair.
These pins require 3.3V bias for operation.
1.9 Special Connections
Signal NameTypePin #Description
RBIASI24Bias Resistor Connection. A 4.87 kΩ 1% resistor should be con-
PFBOUTO23Power Feedback Output. Parallel caps, 10µ F (Tantalum pre-
PFBIN1
PFBIN2
RESERVEDI/O20, 21RESERVED: These pins must be pulled-up through 2.2 kΩ resis-
I18
37
nected from RBIAS to GND.
ferred) and 0.1µF, should be placed close to the PFBOUT. Con-
nect this pin to PFBIN1 (pin 18) and PFBIN2 (pin 37). See
Section 5.4 for proper placement pin.
Power Feedback Input. These pins are fed with power from
PFBOUT pin. A small capacitor of 0.1µF should be connected
close to each pin.
Note: Do not supply power to these pins other than from
PFBOUT.
tors to AVDD33 supply.
1.10 Power Supply Pins
Signal NamePin #Description
IOVDD3332, 48I/O 3.3V Supply
IOGND35, 47I/O Ground
DGND36Digital Ground
AVDD3322Analog 3.3V Supply
AGND15, 19Analog Ground
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1.11 Package Pin Assignments
VBH48A Pin # Pin Name
1TX_CLK
2TX_EN
3TXD_0
4TXD_1
5TXD_2
6TXD_3/SNI_MODE
7PWR_DOWN/INT
8TCK
9TDO
10TMS
11TRST#
12TDI
13RD -
14RD +
15AGND
16TD -
17TD +
18PFBIN1
19AGND
20RESERVED
21RESERVED
22AVDD33
23PFBOUT
24RBIAS
2525MHz_OUT
26LED_ACT/COL/AN_EN
27LED_SPEED/AN1
28LED_LINK/AN0
29RESET_N
30MDIO
31MDC
32IOVDD33
33X2
34X1
35IOGND
36DGND
37PFBIN2
38RX_CLK
39RX_DV/MII_MODE
40CRS/CRS_DV/LED_CFG
DP83848I
VBH48A Pin # Pin Name
41RX_ER/MDIX_EN
42COL/PHYAD0
43RXD_0/PHYAD1
44RXD_1/PHYAD2
45RXD_2/PHYAD3
46RXD_3/PHYAD4
47IOGND
48IOVDD33
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2.0 Configuration
This section includes information on the various configuration options available with the DP83848I. The configuration
options described below include:
DP83848I
— Auto-Negotiation
— PHY Address and LEDs
— Half Duplex vs. Full Duplex
— Isolate mode
— Loopback mode
—BIST
2.1 Auto-Negotiation
The Auto-Negotiation function provides a mechanism for
exchanging configuration information between two ends of
a link segment and automatically selecting the highest per
formance mode of operation supported by both devices.
Fast Link Pulse (FLP) Bursts provide the signalling used to
communicate Auto-Negotiation abilities between two
devices at each end of a link segment. For further detail
regarding Auto-Negotiation, refer to Clause 28 of the IEEE
802.3u specification. The DP83848I supports four different
Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full
Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex),
so the inclusion of Auto-Negotiation ensures that the high
est performance protocol will be selected based on the
advertised ability of the Link Partner. The Auto-Negotiation
function within the DP83848I can be controlled either by
internal register access or by the use of the AN_EN, AN1
and AN0 pins.
2.1.1 Auto-Negotiation Pin Control
The state of AN_EN, AN0 and AN1 determines whether the
DP83848I is forced into a specific mode or Auto-Negotiation will advertise a specific ability (or set of abilities) as
given in
be selected without requiring internal register access.
The state of AN_EN, AN0 and AN1, upon power-up/reset,
determines the state of bits [8:5] of the ANAR register.
The Auto-Negotiation function selected at power-up or
reset can be changed at any time by writing to the Basic
Mode Control Register (BMCR) at address 0x00h.
Table 1. These pins allow configuration options to
Tabl e 1. Auto-Negotiation Modes
AN_ENAN1 AN0Forced Mode
00010BASE-T, Half-Duplex
00110BASE-T, Full-Duplex
010100BASE-TX, Half-Duplex
011100BASE-TX, Full-Duplex
AN_EN AN1 AN0Advertised Mode
10010BASE-T, Half/Full-Duplex
101100BASE-TX, Half/Full-Duplex
11010BASE-T Half-Duplex
100BASE-TX, Half-Duplex
11110BASE-T, Half/Full-Duplex
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100BASE-TX, Half/Full-Duplex
2.1.2 Auto-Negotiation Register Control
When Auto-Negotiation is enabled, the DP83848I transmits
the abilities programmed into the Auto-Negotiation Advertisement register (ANAR) at address 04h via FLP Bursts.
Any combination of 10 Mb/s, 100 Mb/s, Half-Duplex, and
Full Duplex modes may be selected.
Auto-Negotiation Priority Resolution:
— (1) 100BASE-TX Full Duplex (Highest Priority)
— (2) 100BASE-TX Half Duplex
— (3) 10BASE-T Full Duplex
— (4) 10BASE-T Half Duplex (Lowest Priority)
The Basic Mode Control Register (BMCR) at address 00h
provides control for enabling, disabling, and restarting the
Auto-Negotiation process. When Auto-Negotiation is dis
abled, the Speed Selection bit in the BMCR controls
switching between 10 Mb/s or 100 Mb/s operation, and the
Duplex Mode bit controls switching between full duplex
operation and half duplex operation. The Speed Selection
and Duplex Mode bits have no effect on the mode of oper
ation when the Auto-Negotiation Enable bit is set.
The Link Speed can be examined through the PHY Status
Register (PHYSTS) at address 10h after a Link is
achieved.
The Basic Mode Status Register (BMSR) indicates the set
of available abilities for technology types, Auto-Negotiation
ability, and Extended Register Capability. These bits are
permanently set to indicate the full functionality of the
DP83848I (only the 100BASE-T4 bit is not set since the
DP83848I does not support that function).
The BMSR also provides status on:
— Whether or not Auto-Negotiation is complete
— Whether or not the Link Partner is advertising that a re-
mote fault has occurred
— Whether or not valid link has been established
— Support for Management Frame Preamble suppression
The Auto-Negotiation Advertisement Register (ANAR)
indicates the Auto-Negotiation abilities to be advertised by
the DP83848I. All available abilities are transmitted by
default, but any ability can be suppressed by writing to the
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ANAR. Updating the ANAR to suppress an ability is one
way for a management agent to change (restrict) the tech
nology that is used.
The Auto-Negotiation Link Partner Ability Register
(ANLPAR) at address 05h is used to receive the base link
code word as well as all next page code words during the
negotiation. Furthermore, the ANLPAR will be updated to
either 0081h or 0021h for parallel detection to either 100
Mb/s or 10 Mb/s respectively.
The Auto-Negotiation Expansion Register (ANER) indicates additional Auto-Negotiation status. The ANER provides status on:
— Whether or not a Parallel Detect Fault has occurred
— Whether or not the Link Partner supports the Next Page
function
— Whether or not the DP83848I supports the Next Page
function
— Whether or not the current page being exchanged by
Auto-Negotiation has been received
— Whether or not the Link Partner supports Auto-Negotia-
tion
2.1.3 Auto-Negotiation Parallel Detection
The DP83848I supports the Parallel Detection function as
defined in the IEEE 802.3u specification. Parallel Detection
requires both the 10 Mb/s and 100 Mb/s receivers to moni
tor the receive signal and report link status to the AutoNegotiation function. Auto-Negotiation uses this informa
tion to configure the correct technology in the event that the
Link Partner does not support Auto-Negotiation but is
transmitting link signals that the 100BASE-TX or 10BASET PMAs recognize as valid link signals.
If the DP83848I completes Auto-Negotiation as a result of
Parallel Detection, bits 5 and 7 within the ANLPAR register
will be set to reflect the mode of operation present in the
Link Partner. Note that bits 4:0 of the ANLPAR will also be
set to 00001 based on a successful parallel detection to
indicate a valid 802.3 selector field. Software may deter
mine that negotiation completed via Parallel Detection by
reading a zero in the Link Partner Auto-Negotiation Able bit
once the Auto-Negotiation Complete bit is set. If configured
for parallel detect mode and any condition other than a sin
gle good link occurs then the parallel detect fault bit will be
set.
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2.1.4 Auto-Negotiation Restart
Once Auto-Negotiation has completed, it may be restarted
at any time by setting bit 9 (Restart Auto-Negotiation) of the
BMCR to one. If the mode configured by a successful AutoNegotiation loses a valid link, then the Auto-Negotiation
process will resume and attempt to determine the configu
ration for the link. This function ensures that a valid configuration is maintained if the cable becomes disconnected.
A renegotiation request from any entity, such as a management agent, will cause the DP83848I to halt any transmit
data and link pulse activity until the break_link_timer
expires (~1500 ms). Consequently, the Link Partner will go
into link fail and normal Auto-Negotiation resumes. The
DP83848I will resume Auto-Negotiation after the
break_link_timer has expired by issuing FLP (Fast Link
Pulse) bursts.
2.1.5 Enabling Auto-Negotiation via Software
It is important to note that if the DP83848I has been initialized upon power-up as a non-auto-negotiating device
(forced technology), and it is then required that Auto-Negotiation or re-Auto-Negotiation be initiated via software,
12 (Auto-Negotiation Enable) of the Basic Mode Control
bit
Register (BMCR) must first be cleared and then set for any
Auto-Negotiation function to take effect.
2.1.6 Auto-Negotiation Complete Time
Parallel detection and Auto-Negotiation take approximately
2-3 seconds to complete. In addition, Auto-Negotiation with
next page should take approximately 2-3 seconds to com
plete, depending on the number of next pages sent.
Refer to Clause 28 of the IEEE 802.3u standard for a full
description of the individual timers related to Auto-Negotiation.
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2.2 Auto-MDIX
When enabled, this function utilizes Auto-Negotiation to
determine the proper configuration for transmission and
reception of data and subsequently selects the appropriate
MDI pair for MDI/MDIX operation. The function uses a ran
dom seed to control switching of the crossover circuitry.
This implementation complies with the corresponding IEEE
802.3 Auto-Negotiation and Crossover Specifications.
Auto-MDIX is enabled by default and can be configured via
strap or via PHYCR (0x19h) register, bits [15:14].
Neither Auto-Negotiation nor Auto-MDIX is required to be
enabled in forcing crossover of the MDI pairs. Forced
crossover can be achieved through the FORCE_MDIX bit,
bit 14 of PHYCR (0x19h) register.
Note: Auto-MDIX will not work in a forced mode of operation.
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DP83848I
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2.3 PHY Address
The 5 PHY address inputs pins are shared with the
RXD[3:0] pins and COL pin as shown below.
DP83848I
Tabl e 2. PHY Address Mapping
Pin #PHYAD FunctionRXD Function
42PHYAD0COL
43PHYAD1RXD_0
44PHYAD2RXD_1
45PHYAD3RXD_2
46PHYAD4RXD_3
The DP83848I can be set to respond to any of 32 possible
PHY addresses via strap pins. The information is latched
into the PHYCR register (address 19h, bits [4:0]) at device
power-up and hardware reset. The PHY Address pins are
shared with the RXD and COL pins. Each DP83848I or port
sharing an MDIO bus in a system must have a unique
physical address.
The DP83848I supports PHY Address strapping values 0
(<0 0 0 0 0 > ) t h r o u g h 3 1 (<11111 >). St r a p p i n g PHY Address 0 puts the part into Isolate Mode. It should also be noted
that selecting PHY Address 0 via an MDIO write to PHYCR
will not put the device in Isolate Mode. See
more information.
For further detail relating to the latch-in timing requirements
of the PHY Address pins, as well as the other hardware
configuration pins, refer to the Reset summary in
Section 6.0.
Section 2.3.1for
Since the PHYAD[0] pin has weak internal pull-up resistor
and PHYAD[4:1] pins have weak internal pull-down resis
tors, the default setting for the PHY address is 00001
(01h).
Refer to Figure 2 for an example of a PHYAD connection to
external components. In this example, the PHYAD strapping results in address 00011 (03h).
2.3.1 MII Isolate Mode
The DP83848I can be put into MII Isolate mode by writing
to bit 10 of the BMCR register or by strapping in Physical
Address 0. It should be noted that selecting Physical
Address 0 via an MDIO write to PHYCR will not put the
device in the MII isolate mode.
When in the MII isolate mode, the DP83848I does not
respond to packet data present at TXD[3:0], TX_EN inputs
and presents a high impedance on the TX_CLK, RX_CLK,
RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When
in Isolate mode, the DP83848I will continue to respond to
all management transactions.
While in Isolate mode, the PMD output pair will not transmit
packet data but will continue to source 100BASE-TX
scrambled idles or 10BASE-T normal link pulses.
The DP83848I can Auto-Negotiate or parallel detect to a
specific technology depending on the receive signal at the
PMD input pair. A valid link can be established for the
receiver even when the DP83848I is in Isolate mode.
-
RXD_3
PHYAD4= 0
RXD_2
Figure 2. PHYAD Strapping Example
RXD_1
PHYAD2 = 0PHYAD3 = 0
RXD_0
PHYAD1 = 1
2.2kΩ
COL
PHYAD0 = 1
VCC
www.national.com18
2.4 LED Interface
The DP83848I supports three configurable Light Emitting
Diode (LED) pins. The device supports three LED configu
rations: Link, Speed, Activity and Collision. Function are
Tab le 3. LED Mode Select
ModeLED_CFG[1]
(bit 6)
1don’t care1ON for Good Link
200ON for Good Link
310ON for Good Link
LED_CFG[0]
(bit 5)
or (pin40)
LED_LINKLED_SPEEDLED_ACT/COL
OFF for No Link
BLINK for Activity
BLINK for Activity
multiplexed among the LEDs. The PHY Control Register
(PHYCR) for the LEDs can also be selected through
address 19h, bits [6:5].
See Table 3 for LED Mode selection.
ON in 100 Mb/s
OFF in 10 Mb/s
ON in 100 Mb/s
OFF in 10 Mb/s
ON in 100 Mb/s
OFF in 10 Mb/s
ON for Activity
OFF for No Activity
ON for Collision
OFF for No Collision
ON for Full Duplex
OFF for Half Duplex
DP83848I
The LED_LINK pin in Mode 1 indicates the link status of
the port. In 100BASE-T mode, link is established as a
result of input receive amplitude compliant with the TPPMD specifications which will result in internal generation
of signal detect. A 10 Mb/s Link is established as a result of
the reception of at least seven consecutive normal Link
Pulses or the reception of a valid 10BASE-T packet. This
will cause the assertion of LED_LINK. LED_LINK will deas
sert in accordance with the Link Loss Timer as specified in
the IEEE 802.3 specification.
The LED_LINK pin in Mode 1 will be OFF when no LINK is
present.
The LED_LINK pin in Mode 2 and Mode 3 will be ON to
indicate Link is good and BLINK to indicate activity is
present on either transmit or receive activity.
The LED_SPEED pin indicates 10 or 100 Mb/s data rate of
the port. The standard CMOS driver goes high when operating in 100 Mb/s operation. The functionality of this LED is
independent of mode selected.
The LED_ACT/COL pin in Mode 1 indicates the presence
of either transmit or receive activity. The LED will be ON for
Activity and OFF for No Activity. In Mode 2, this pin indi
cates the Collision status of the port. The LED will be ON
for Collision and OFF for No Collision.
The LED_ACT/COL pin in Mode 3 indicates the presence
of Duplex status for 10 Mb/s or 100 Mb/s operation. The
LED will be ON for Full Duplex and OFF for Half Duplex.
In 10 Mb/s half duplex mode, the collision LED is based on
the COL signal.
Since these LED pins are also used as strap options, the
polarity of the LED is dependent on whether the pin is
pulled up or down.
-
-
Specifically, when the LED outputs are used to drive LEDs
directly, the active state of each output driver is dependent
on the logic level sampled by the corresponding AN input
upon power-up/reset. For example, if a given AN input is
resistively pulled low then the corresponding output will be
configured as an active high driver. Conversely, if a given
AN input is resistively pulled high, then the corresponding
output will be configured as an active low driver.
Refer to Figure 3 for an example of AN connections to
external components. In this example, the AN strapping
results in Auto-Negotiation with 10/100 Half/Full-Duplex
advertised.
The adaptive nature of the LED outputs helps to simplify
potential implementation issues of these dual purpose pins.
LED_ACT/COL
AN_EN = 1
2.2kΩ
LED_SPEED
AN1 = 1
2.2kΩ
110Ω
110Ω
2.2kΩ
LED_LINK
AN0 = 1
110Ω
VCC
2.4.1 LEDs
Since the Auto-Negotiation (AN) strap options share the
LED output pins, the external components required for
strapping and LED usage must be considered in order to
avoid contention.
Figure 3. AN Strapping and LED Loading Example
19 www.national.com
2.4.2 LED Direct Control
The DP83848I provides another option to directly control
any or all LED outputs through the LED Direct Control Reg
ister (LEDCR), address 18h. The register does not provide
DP83848I
read access to LEDs.
2.5 Half Duplex vs. Full Duplex
The DP83848I supports both half and full duplex operation
at both 10 Mb/s and 100 Mb/s speeds.
Half-duplex relies on the CSMA/CD protocol to handle collisions and network access. In Half-Duplex mode, CRS
responds to both transmit and receive activity in order to
maintain compliance with the IEEE 802.3 specification.
Since the DP83848I is designed to support simultaneous
transmit and receive activity it is capable of supporting fullduplex switched applications with a throughput of up to 200
Mb/s per port when operating in 100BASE-TX mode.
Because the CSMA/CD protocol does not apply to fullduplex operation, the DP83848I disables its own internal
collision sensing and reporting functions and modifies the
behavior of Carrier Sense (CRS) such that it indicates only
receive activity. This allows a full-duplex capable MAC to
operate properly.
All modes of operation (100BASE-TX and 10BASE-T) can
run either half-duplex or full-duplex. Additionally, other than
CRS and Collision reporting, all remaining MII signaling
remains the same regardless of the selected duplex mode.
It is important to understand that while Auto-Negotiation
with the use of Fast Link Pulse code words can interpret
and configure to full-duplex operation, parallel detection
can not recognize the difference between full and halfduplex from a fixed 10 Mb/s or 100 Mb/s link partner over
twisted pair. As specified in the 802.3u specification, if a
far-end link partner is configured to a forced full duplex
100BASE-TX ability, the parallel detection state machine in
the partner would be unable to detect the full duplex capa
bility of the far-end link partner. This link segment would
negotiate to a half duplex 100BASE-TX configuration
(same scenario for 10 Mb/s).
2.6 Internal Loopback
The DP83848I includes a Loopback Test mode for facilitat-
-
ing system diagnostics. The Loopback mode is selected
through bit 14 (Loopback) of the Basic Mode Control Reg
ister (BMCR). Writing 1 to this bit enables MII transmit data
to be routed to the MII receive outputs. Loopback status
may be checked in bit 3 of the PHY Status Register
(PHYSTS). While in Loopback mode the data will not be
transmitted onto the media. To ensure that the desired
operating mode is maintained, Auto-Negotiation should be
disabled before selecting the Loopback mode.
2.7 BIST
The DP83848I incorporates an internal Built-in Self Test
(BIST) circuit to accommodate in-circuit testing or diagnos
tics. The BIST circuit can be utilized to test the integrity of
the transmit and receive data paths. BIST testing can be
performed with the part in the internal loopback mode or
externally looped back using a loopback cable fixture.
The BIST is implemented with independent transmit and
receive paths, with the transmit block generating a continuous stream of a pseudo random sequence. The user can
select a 9 bit or 15 bit pseudo random sequence from the
PSR_15 bit in the PHY Control Register (PHYCR). The
received data is compared to the generated pseudo-ran
dom data by the BIST Linear Feedback Shift Register
(LFSR) to determine the BIST pass/fail status.
The pass/fail status of the BIST is stored in the BIST status
bit in the PHYCR register. The status bit defaults to 0 (BIST
fail) and will transition on a successful comparison. If an
error (mis-compare) occurs, the status bit is latched and is
cleared upon a subsequent write to the Start/Stop bit.
For transmit VOD testing, the Packet BIST Continuous
Mode can be used to allow continuous data transmission,
setting BIST_CONT_MODE, bit 5, of CDCTRL1 (0x1Bh).
-
The number of BIST errors can be monitored through the
BIST Error Count in the CDCTRL1 (0x1Bh), bits [15:8].
-
-
-
www.national.com20
3.0 Functional Description
The DP83848I supports several modes of operation using
the MII interface pins. The options are defined in the follow
ing sections and include:
— MII Mode
— RMII Mode
— 10 Mb Serial Network Interface (SNI)
The modes of operation can be selected by strap options
or register control. For RMII mode, it is required to use the
strap option, since it requires a 50 MHz clock instead of the
normal 25 MHz.
In each of these modes, the IEEE 802.3 serial management interface is operational for device configuration and
status. The serial management interface of the MII allows
for the configuration and control of multiple PHY devices,
gathering of status, error information, and the determina
tion of the type and capabilities of the attached PHY(s).
3.1 MII Interface
The DP83848I incorporates the Media Independent Interface (MII) as specified in Clause 22 of the IEEE 802.3u
standard. This interface may be used to connect PHY
devices to a MAC in 10/100 Mb/s systems. This section
describes the nibble wide MII data interface.
The nibble wide MII data interface consists of a receive bus
and a transmit bus each with control signals to facilitate
data transfer between the PHY and the upper layer (MAC).
3.1.1 Nibble-wide MII Data Interface
Clause 22 of the IEEE 802.3u specification defines the
Media Independent Interface. This interface includes a
dedicated receive bus and a dedicated transmit bus. These
two data buses, along with various control and status sig
nals, allow for the simultaneous exchange of data between
the DP83848I and the upper layer agent (MAC).
The receive interface consists of a nibble wide data bus
RXD[3:0], a receive error signal RX_ER, a receive data
valid flag RX_DV, and a receive clock RX_CLK for syn
chronous transfer of the data. The receive clock operates
at either 2.5 MHz to support 10 Mb/s operation modes or at
25 MHz to support 100 Mb/s operational modes.
The transmit interface consists of a nibble wide data bus
TXD[3:0], a transmit enable control signal TX_EN, and a
transmit clock TX_CLK which runs at either 2.5 MHz or 25
MHz.
Additionally, the MII includes the carrier sense signal CRS,
as well as a collision detect signal COL. The CRS signal
asserts to indicate the reception of data from the network
or as a function of transmit data in Half Duplex mode. The
COL signal asserts as an indication of a collision which can
occur during half-duplex operation when both a transmit
and receive operation occur simultaneously.
3.1.2 Collision Detect
For Half Duplex, a 10BASE-T or 100BASE-TX collision is
detected when the receive and transmit channels are
active simultaneously. Collisions are reported by the COL
signal on the MII.
-
-
-
-
If the DP83848I is transmitting in 10 Mb/s mode when a
collision is detected, the collision is not reported until seven
bits have been received while in the collision state. This
prevents a collision being reported incorrectly due to noise
on the network. The COL signal remains set for the dura
tion of the collision.
If a collision occurs during a receive operation, it is immediately reported by the COL signal.
When heartbeat is enabled (only applicable to 10 Mb/s
operation), approximately 1
each packet, a Signal Quality Error (SQE) signal of approx
imately 10 bit times is generated (internally) to indicate
successful transmission. SQE is reported as a pulse on the
COL signal of the MII.
3.1.3 Carrier Sense
Carrier Sense (CRS) is asserted due to receive activity,
once valid data is detected via the squelch function during
10 Mb/s operation. During 100 Mb/s operation CRS is
asserted when a valid link (SD) and two non-contiguous
zeros are detected on the line.
For 10 or 100 Mb/s Half Duplex operation, CRS is asserted
during either packet transmission or reception.
For 10 or 100 Mb/s Full Duplex operation, CRS is asserted
only due to receive activity.
CRS is deasserted following an end of packet.
µs after the transmission of
-
-
3.2 Reduced MII Interface
The DP83848I incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII specification
(rev1.2) from the RMII Consortium. This interface may be
used to connect PHY devices to a MAC in 10/100 Mb/s
systems using a reduced number of pins. In this mode,
data is transferred 2-bits at a time using the 50 MHz
RMII_REF clock for both transmit and receive. The follow
ing pins are used in RMII mode:
— TX_EN
—TXD[1:0]
— RX_ER (optional for Mac)
— CRS_DV
— RXD[1:0]
— X1 (RMII Reference clock is 50 MHz)
In addition, the RMII mode supplies an RX_DV signal
which allows for a simpler method of recovering receive
data without having to separate RX_DV from the CRS_DV
indication. This is especially useful for systems which do
not require CRS, such as systems that only support fullduplex operation. This signal is also useful for diagnostic
testing where it may be desirable to loop Receive RMII
data directly to the transmitter.
Since the reference clock operates at 10 times the data
rate for 10 Mb/s operation, transmit data is sampled every
10 clocks. Likewise, receive data will be generated every
10th clock so that an attached device can sample the data
every 10 clocks.
RMII mode requires a 50 MHz oscillator be connected to
the device X1 pin. A 50 MHz crystal is not supported.
-
DP83848I
21 www.national.com
To tolerate potential frequency differences between the 50
MHz reference clock and the recovered receive clock, the
receive RMII function includes a programmable elasticity
buffer. The elasticity buffer is programmable to minimize
DP83848I
propagation delay based on expected packet size and
clock accuracy. This allows for supporting a range of
packet sizes including jumbo frames.
Table 4. Supported packet sizes at +/-50ppm +/-100ppm for each clock
Start Threshold
RBR[1:0]
1 (4-bits)2 bits2400 bytes1200 bytes
2 (8-bits)6 bits7200 bytes3600 bytes
3 (12-bits)10 bits12000 bytes6000 bytes
0 (16-bits)14 bits16800 bytes8400 bytes
Latency ToleranceRecommended Packet Size
The elasticity buffer will force Frame Check Sequence
errors for packets which overrun or underrun the FIFO.
Underrun and Overrun conditions can be reported in the
RMII and Bypass Register (RBR). The following table indi
cates how to program the elasticity buffer fifo (in 4-bit increments) based on expected max packet size and clock
accuracy. It assumes both clocks (RMII Reference clock
and far-end Transmitter clock) have the same accuracy.
at +/- 50ppm
Recommended Packet Size
at +/- 100ppm
-
3.3 10 Mb Serial Network Interface (SNI)
The DP83848I incorporates a 10 Mb Serial Network Interface (SNI) which allows a simple serial data interface for 10
Mb only devices. This is also referred to as a 7-wire interface. While there is no defined standard for this interface, it
is based on early 10 Mb physical layer devices. Data is
clocked serially at 10 MHz using separate transmit and
receive paths. The following pins are used in SNI mode:
—TX_CLK
—TX_EN
—TXD[0]
—RX_CLK
—RXD[0]
— CRS
—COL
3.4 802.3u MII Serial Management Interface
3.4.1 Serial Management Register Access
The serial management MII specification defines a set of
thirty-two 16-bit status and control registers that are acces
sible through the management interface pins MDC and
MDIO. The DP83848I implements all the required MII reg
isters as well as several optional registers. These registers
are fully described in Section 7.0. A description of the serial
management access protocol follows.
3.4.2 Serial Management Access Protocol
The serial control interface consists of two pins, Management Data Clock (MDC) and Management Data Input/Output (MDIO). MDC has a maximum clock rate of 25 MHz
and no minimum rate. The MDIO line is bi-directional and
may be shared by up to 32 devices. The MDIO frame for
mat is shown below in Tab le 5 .
The MDIO pin requires a pull-up resistor (1.5 kΩ) which,
during IDLE and turnaround, will pull MDIO high. In order to
initialize the MDIO interface, the station management entity
sends a sequence of 32 contiguous logic ones on MDIO to
provide the DP83848I with a sequence that can be used to
establish synchronization. This preamble may be gener
ated either by driving MDIO high for 32 consecutive MDC
clock cycles, or by simply allowing the MDIO pull-up resis
tor to pull the MDIO pin high during which time 32 MDC
clock cycles are provided. In addition 32 MDC clock cycles
should be used to re-sync the device if an invalid start,
opcode, or turnaround bit is detected.
The DP83848I waits until it has received this preamble
sequence before responding to any other transaction.
Once the DP83848I serial management port has been ini
tialized no further preamble sequencing is required until
after a power-on/reset, invalid Start, invalid Opcode, or
invalid turnaround bit has occurred.
The Start code is indicated by a <01> pattern. This assures
the MDIO line transitions from the default idle line state.
Turnaround is defined as an idle bit time inserted between
the Register Address field and the Data field. To avoid contention during a read transaction, no device shall actively
drive the MDIO signal during the first bit of Turnaround.
The addressed DP83848I drives the MDIO with a zero for
the second bit of turnaround and follows this with the
required data.
between MDC and the MDIO as driven/received by the Sta-
tion (STA) and the DP83848I (PHY) for a typical register
read access.
For write transactions, the station management entity
writes data to the addressed DP83848I thus eliminating the
requirement for MDIO Turnaround. The Turnaround time is
filled by the management entity by inserting <10>.
shows the timing relationship for a typical MII register write
access.
The DP83848I supports a Preamble Suppression mode as
indicated by a one in bit 6 of the Basic Mode Status Regis
ter (BMSR, address 01h.) If the station management entity
(i.e. MAC or other management controller) determines that
all PHYs in the system support Preamble Suppression by
returning a one in this bit, then the station management
entity need not generate preamble for each management
transaction.
The DP83848I requires a single initialization sequence of
32 bits of preamble following hardware/software reset. This
Z
Z
0 0 011000100000000
TA
0 0 000000000000
1000
TA
Register Data
Register Data
Z
Idle
requirement is generally met by the mandatory pull-up
resistor on MDIO in conjunction with a continuous MDC, or
the management access made to determine whether Pre
amble Suppression is supported.
While the DP83848I requires an initial preamble sequence
of 32 bits for management initialization, it does not require
a full 32-bit sequence between each subsequent transac
tion. A minimum of one idle bit between management transactions is required as specified in the IEEE 802.3u
specification.
ZZ
Z
Idle
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23 www.national.com
4.0 Architecture
This section describes the operations within each transceiver module, 100BASE-TX and 10BASE-T. Each operation consists of several functional blocks and described in
The 100BASE-TX transmitter consists of several functional
blocks which convert synchronous 4-bit nibble data, as pro
vided by the MII, to a scrambled MLT-3 125 Mb/s serial
data stream. Because the 100BASE-TX TP-PMD is integrated, the differential output pins, PMD Output Pair, can
be directly routed to the magnetics.
The block diagram in Figure 6. provides an overview of
each functional block within the 100BASE-TX transmit section.
The Transmitter section consists of the following functional
blocks:
— Code-group Encoder and Injection block
— Scrambler block (bypass option)
— NRZ to NRZI encoder block
— Binary to MLT-3 converter / Common Driver
The bypass option for the functional blocks within the
100BASE-TX transmitter provides flexibility for applications
where data conversion is not always required. The
DP83848I implements the 100BASE-TX transmit state
machine diagram as specified in the IEEE 802.3u Stan
dard, Clause 24.
-
125MHZ CLOCK
BP_SCR
100BASE-TX
LOOPBACK
TX_CLK
DIVIDE
BY 5
MLT[1:0]
TXD[3:0] /
TX_EN
4B5B CODE-
GROUP
ENCODER &
5B PARALLEL
TO SERIAL
SCRAMBLER
MUX
NRZ TO NRZI
ENCODER
BINARY
TO MLT-3 /
COMMON
DRIVER
Figure 6. 100BASE-TX Transmit Block Diagram
www.national.com24
PMD OUTPUT PAIR
Tab le 5. 4B5B CCode-group Encoding and Injection
6.
DATA CODES
0111100000
1010010001
2101000010
3101010011
4010100100
5010110101
6011100110
7011110111
8100101000
9100111001
A101101010
B101111011
C110101100
D110111101
E111001110
F111011111
IDLE AND CONTROL CODES
H00100HALT code-group - Error code
I11111Inter-Packet IDLE - 0000 (Note 1)
J11000First Start of Packet - 0101 (Note 1)
K10001Second Start of Packet - 0101 (Note 1)
T01101First End of Packet - 0000 (Note 1)
R00111Second End of Packet - 0000 (Note 1)
INVALID CODES
V00000
V00001
V00010
V00011
V00101
V00110
V01000
V01100
Note: Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER asserted.
DP83848I
The code-group encoder converts 4-bit (4B) nibble data
generated by the MAC into 5-bit (5B) code-groups for
transmission. This conversion is required to allow control
data to be combined with packet data code-groups. Refer
Tab l e 5 for 4B to 5B code-group mapping details.
to
The code-group encoder substitutes the first 8-bits of the
MAC preamble with a J/K code-group pair (11000 10001)
upon transmission. The code-group encoder continues to
replace subsequent 4B preamble and data nibbles with
corresponding 5B code-groups. At the end of the transmit
packet, upon the deassertion of Transmit Enable signal
from the MAC, the code-group encoder injects the T/R
code-group pair (01101 00111) indicating the end of the
frame.
After the T/R code-group pair, the code-group encoder
continuously injects IDLEs into the transmit data stream
until the next transmit packet is detected (reassertion of
Transmit Enable).
4.1.1 Scrambler
The scrambler is required to control the radiated emissions
at the media connector and on the twisted pair cable (for
25 www.national.com
100BASE-TX applications). By scrambling the data, the
total energy launched onto the cable is randomly distrib
uted over a wide frequency range. Without the scrambler,
energy levels at the PMD and on the cable could peak
DP83848I
beyond FCC limitations at frequencies related to repeating
5B sequences (i.e., continuous transmission of IDLEs).
The scrambler is configured as a closed loop linear feedback shift register (LFSR) with an 11-bit polynomial. The
output of the closed loop LFSR is X-ORd with the serial
NRZ data from the code-group encoder. The result is a
scrambled data stream with sufficient randomization to
decrease radiated emissions at certain frequencies by as
much as 20 dB. The DP83848I uses the PHY_ID (pins
PHYAD [4:0]) to set a unique seed value.
4.1.2 NRZ to NRZI Encoder
After the transmit data stream has been serialized and
scrambled, the data must be NRZI encoded in order to
comply with the TP-PMD standard for 100BASE-TX trans
mission over Category-5 Unshielded twisted pair cable.
4.1.3 Binary to MLT-3 Convertor
The Binary to MLT-3 conversion is accomplished by converting the serial binary data stream output from the NRZI
encoder into two binary data streams with alternately
phased logic one events. These two binary streams are
then fed to the twisted pair output driver which converts the
voltage to current and alternately drives either side of the
transmit transformer primary winding, resulting in a MLT-3
signal.
The 100BASE-TX MLT-3 signal sourced by the PMD Output Pair common driver is slew rate controlled. This should
be considered when selecting AC coupling magnetics to
ensure TP-PMD Standard compliant transition times (3 ns
< Tr < 5 ns).
The 100BASE-TX transmit TP-PMD function within the
DP83848I is capable of sourcing only MLT-3 encoded data.
Binary output from the PMD Output Pair is not possible in
100 Mb/s mode.
4.2 100BASE-TX RECEIVER
The 100BASE-TX receiver consists of several functional
blocks which convert the scrambled MLT-3 125 Mb/s serial
data stream to synchronous 4-bit nibble data that is pro
vided to the MII. Because the 100BASE-TX TP-PMD is
integrated, the differential input pins, RD±, can be directly
routed from the AC coupling magnetics.
See Figure 7 for a block diagram of the 100BASE-TX
receive function. This provides an overview of each functional block within the 100BASE-TX receive section.
The Receive section consists of the following functional
blocks:
— Analog Front End
— Digital Signal Processor
— Signal Detect
— MLT-3 to Binary Decoder
— NRZI to NRZ Decoder
— Serial to Parallel
— Descrambler
— Code Group Alignment
—4B/5B Decoder
— Link Integrity Monitor
— Bad SSD Detection
4.2.1 Analog Front End
In addition to the Digital Equalization and Gain Control, the
DP83848I includes Analog Equalization and Gain Control
in the Analog Front End. The Analog Equalization reduces
the amount of Digital Equalization required in the DSP.
4.2.2 Digital Signal Processor
The Digital Signal Processor includes Adaptive Equalization with Gain Control and Base Line Wander Compensation.
-
www.national.com26
DP83848I
RX_DV/CRS
RX_DATA
VALID SSD
DETECT
RX_CLKRXD[3:0] / RX_ER
4B/5B DECODER
SERIAL TO
PARALLEL
CODE GROUP
ALIGNMENT
DESCRAMBLER
NRZI TO NRZ
DECODER
MLT-3 TO BINARY
DECODER
LINK
INTEGRITY
MONITOR
SIGNAL
DETECT
DIGITAL
SIGNAL
PROCESSOR
ANALOG
FRONT
END
RD +/−
Figure 7. 100BASE-TX Receive Block Diagram
27 www.national.com
4.2.2.1 Digital Adaptive Equalization and Gain Control
When transmitting data at high speeds over copper twisted
pair cable, frequency dependent attenuation becomes a
concern. In high-speed twisted pair signalling, the fre
DP83848I
quency content of the transmitted signal can vary greatly
during normal operation based primarily on the random
ness of the scrambled data stream. This variation in signal
attenuation caused by frequency variations must be com
pensated to ensure the integrity of the transmission.
In order to ensure quality transmission when employing
MLT-3 encoding, the compensation must be able to adapt
to various cable lengths and cable types depending on the
installed environment. The selection of long cable lengths
for a given implementation, requires significant compensa
tion which will over-compensate for shorter, less attenuating lengths. Conversely, the selection of short or
intermediate cable lengths requiring less compensation will
cause serious under-compensation for longer length
cables. The compensation or equalization must be adap
tive to ensure proper conditioning of the received signal
independent of the cable length.
The DP83848I utilizes an extremely robust equalization
scheme referred as ‘Digital Adaptive Equalization.’
The Digital Equalizer removes ISI (inter symbol interfer-
-
ence) from the receive data stream by continuously adapting to provide a filter with the inverse frequency response
-
of the channel. Equalization is combined with an adaptive
gain control stage. This enables the receive 'eye pattern' to
be opened sufficiently to allow very reliable data recovery.
The curves given in Figure 8 illustrate attenuation at certain
frequencies for given cable lengths. This is derived from
the worst case frequency vs. attenuation figures as speci
-
fied in the EIA/TIA Bulletin TSB-36. These curves indicate
the significant variations in signal attenuation that must be
compensated for by the receive adaptive equalization cir
cuit.
-
-
-
Figure 8. EIA/TIA Attenuation vs. Frequency for 0, 50,
www.national.com28
100, 130 & 150 meters of CAT 5 cable
4.2.2.2 Base Line Wander Compensation
DP83848I
Figure 9. 100BASE-TX BLW Event
The DP83848I is completely ANSI TP-PMD compliant and
includes Base Line Wander (BLW) compensation. The
BLW compensation block can successfully recover the TPPMD defined “killer” pattern.
BLW can generally be defined as the change in the average DC content, relatively short period over time, of an AC
coupled digital transmission over a given transmission
medium. (i.e., copper wire).
BLW results from the interaction between the low frequency components of a transmitted bit stream and the frequency response of the AC coupling component(s) within
the transmission system. If the low frequency content of
the digital bit stream goes below the low frequency pole of
the AC coupling transformers then the droop characteris
tics of the transformers will dominate resulting in potentially
serious BLW.
The digital oscilloscope plot provided in Figure 9 illustrates
the severity of the BLW event that can theoretically be generated during 100BASE-TX packet transmission. This
event consists of approximately 800 mV of DC offset for a
period of 120 µs. Left uncompensated, events such as this
can cause packet loss.
4.2.3 Signal Detect
The signal detect function of the DP83848I is incorporated
to meet the specifications mandated by the ANSI FDDI TP-
-
PMD Standard as well as the IEEE 802.3 100BASE-TX
Standard for both voltage thresholds and timing parame
ters.
Note that the reception of normal 10BASE-T link pulses
and fast link pulses per IEEE 802.3u Auto-Negotiation by
the 100BASE-TX receiver do not cause the DP83848I to
assert signal detect.
4.2.4 MLT-3 to NRZI Decoder
The DP83848I decodes the MLT-3 information from the
Digital Adaptive Equalizer block to binary NRZI data.
4.2.5 NRZI to NRZ
In a typical application, the NRZI to NRZ decoder is
required in order to present NRZ formatted data to the
descrambler.
4.2.6 Serial to Parallel
The 100BASE-TX receiver includes a Serial to Parallel
converter which supplies 5-bit wide data symbols to the
PCS Rx state machine.
-
29 www.national.com
4.2.7 Descrambler
A serial descrambler is used to de-scramble the received
NRZ data. The descrambler has to generate an identical
data scrambling sequence (N) in order to recover the origi
DP83848I
nal unscrambled data (UD) from the scrambled data (SD)
as represented in the equations:
SDUDN⊕()=
UDSDN⊕()=
Synchronization of the descrambler to the original scrambling sequence (N) is achieved based on the knowledge
that the incoming scrambled data stream consists of
scrambled IDLE data. After the descrambler has recog
nized 12 consecutive IDLE code-groups, where an
unscrambled IDLE code-group in 5B NRZ is equal to five
co n se c u t i v e o n es ( 11111 ) , i t w i l l s y n c h r o n i z e t o t h e r e c e i v e
data stream and generate unscrambled data in the form of
unaligned 5B code-groups.
In order to maintain synchronization, the descrambler must
continuously monitor the validity of the unscrambled data
that it generates. To ensure this, a line state monitor and a
hold timer are used to constantly monitor the synchroniza
tion status. Upon synchronization of the descrambler the
hold timer starts a 722 µs countdown. Upon detection of
sufficient IDLE code-groups (58 bit times) within the 722
period, the hold timer will reset and begin a new count
down. This monitoring operation will continue indefinitely
given a properly operating network connection with good
signal integrity. If the line state monitor does not recognize
sufficient unscrambled IDLE code-groups within the 722
period, the entire descrambler will be forced out of the cur
rent state of synchronization and reset in order to reacquire synchronization.
4.2.10 100BASE-TX Link Integrity Monitor
The 100 Base TX Link monitor ensures that a valid and stable link is established before enabling both the Transmit
-
and Receive PCS layer.
Signal detect must be valid for 395us to allow the link monitor to enter the 'Link Up' state, and enable the transmit and
receive functions.
4.2.11 Bad SSD Detection
A Bad Start of Stream Delimiter (Bad SSD) is any transition
-
from consecutive idle code-groups to non-idle code-groups
which is not prefixed by the code-group pair /J/K.
If this condition is detected, the DP83848I will assert
RX_ER and present RXD[3:0] = 1110 to the MII for the
cycles that correspond to received 5B code-groups until at
least two IDLE code groups are detected. In addition, the
False Carrier Sense Counter register (FCSCR) will be
incremented by one.
Once at least two IDLE code groups are detected, RX_ER
and CRS become de-asserted.
µs
4.3 10BASE-T TRANSCEIVER MODULE
-
The 10BASE-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision, heartbeat, loopback, jabber, and link integrity functions, as
µs
defined in the standard. An external filter is not required on
the 10BASE-T interface since this is integrated inside the
DP83848I. This section focuses on the general 10BASE-T
system level operation.
4.2.8 Code-group Alignment
The code-group alignment module operates on unaligned
5-bit data from the descrambler (or, if the descrambler is
bypassed, directly from the NRZI/NRZ decoder) and con
verts it into 5B code-group data (5 bits). Code-group alignment occurs after the J/K code-group pair is detected.
Once the J/K code-group pair (11000 10001) is detected,
subsequent data is aligned on a fixed boundary.
4.2.9 4B/5B Decoder
The code-group decoder functions as a look up table that
translates incoming 5B code-groups into 4B nibbles. The
code-group decoder first detects the J/K code-group pair
preceded by IDLE code-groups and replaces the J/K with
MAC preamble. Specifically, the J/K 10-bit code-group pair
is replaced by the nibble pair (0101 0101). All subsequent
5B code-groups are converted to the corresponding 4B
nibbles for the duration of the entire packet. This conver
sion ceases upon the detection of the T/R code-group pair
denoting the End of Stream Delimiter (ESD) or with the
reception of a minimum of two IDLE code-groups.
-
-
4.3.1 Operational Modes
The DP83848I has two basic 10BASE-T operational
modes:
— Half Duplex mode
— Full Duplex mode
Half Duplex Mode
In Half Duplex mode the DP83848I functions as a standard
IEEE 802.3 10BASE-T transceiver supporting the
CSMA/CD protocol.
Full Duplex Mode
In Full Duplex mode the DP83848I is capable of simultaneously transmitting and receiving without asserting the
collision signal. The DP83848I's 10 Mb/s ENDEC is
designed to encode and decode simultaneously.
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4.3.2 Smart Squelch
The smart squelch is responsible for determining when
valid data is present on the differential receive inputs. The
DP83848I implements an intelligent receive squelch to
ensure that impulse noise on the receive inputs will not be
mistaken for a valid signal. Smart squelch operation is
independent of the 10BASE-T operational mode.
The squelch circuitry employs a combination of amplitude
and timing measurements (as specified in the IEEE 802.3
10BSE-T standard) to determine the validity of data on the
twisted pair inputs (refer to
The signal at the start of a packet is checked by the smart
squelch and any pulses not exceeding the squelch level
(either positive or negative, depending upon polarity) will
be rejected. Once this first squelch level is overcome cor
rectly, the opposite squelch level must then be exceeded
Figure 10).
-
within 150 ns. Finally the signal must again exceed the
original squelch level within a 150 ns to ensure that the
input waveform will not be rejected. This checking proce
dure results in the loss of typically three preamble bits at
the beginning of each packet.
Only after all these conditions have been satisfied will a
control signal be generated to indicate to the remainder of
the circuitry that valid data is present. At this time, the
smart squelch circuitry is reset.
Valid data is considered to be present until the squelch
level has not been generated for a time longer than 150 ns,
indicating the End of Packet. Once good data has been
detected, the squelch levels are reduced to minimize the
effect of noise causing premature End of Packet detection.
When in Half Duplex, a 10BASE-T collision is detected
when the receive and transmit channels are active simulta
neously. Collisions are reported by the COL signal on the
MII. Collisions are also reported when a jabber condition is
detected.
The COL signal remains set for the duration of the collision.
If the PHY is receiving when a collision is detected it is
reported immediately (through the COL pin).
When heartbeat is enabled, approximately 1 µs after the
transmission of each packet, a Signal Quality Error (SQE)
signal of approximately 10-bit times is generated to indi
cate successful transmission. SQE is reported as a pulse
on the COL signal of the MII.
The SQE test is inhibited when the PHY is set in full duplex
mode. SQE can also be inhibited by setting the
HEARTBEAT_DIS bit in the 10BTSCR register.
-
-
>150 ns
end of packet
4.3.4 Carrier Sense
Carrier Sense (CRS) may be asserted due to receive activity once valid data is detected via the squelch function.
For 10 Mb/s Half Duplex operation, CRS is asserted during
either packet transmission or reception.
For 10 Mb/s Full Duplex operation, CRS is asserted only
during receive activity.
CRS is deasserted following an end of packet.
4.3.5 Normal Link Pulse Detection/Generation
The link pulse generator produces pulses as defined in the
IEEE 802.3 10BASE-T standard. Each link pulse is nomi
nally 100 ns in duration and transmitted every 16 ms in the
absence of transmit data.
Link pulses are used to check the integrity of the connection with the remote end. If valid link pulses are not
received, the link detector disables the 10BASE-T twisted
pair transmitter, receiver and collision detection functions.
When the link integrity function is disabled
(FORCE_LINK_10 of the 10BTSCR register), a good link is
forced and the 10BASE-T transceiver will operate regard
less of the presence of link pulses.
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-
31 www.national.com
4.3.6 Jabber Function
The jabber function monitors the DP83848I's output and
disables the transmitter if it attempts to transmit a packet of
longer than legal size. A jabber timer monitors the transmit
DP83848I
ter and disables the transmission if the transmitter is active
for approximately 85 ms.
Once disabled by the Jabber function, the transmitter stays
disabled for the entire time that the ENDEC module's inter
nal transmit enable is asserted. This signal has to be deasserted for approximately 500 ms (the “unjab” time)
before the Jabber function re-enables the transmit outputs.
The Jabber function is only relevant in 10BASE-T mode.
4.3.7 Automatic Link Polarity Detection and Correction
The DP83848I's 10BASE-T transceiver module incorporates an automatic link polarity detection circuit. When
three consecutive inverted link pulses are received, bad
polarity is reported.
A polarity reversal can be caused by a wiring error at either
end of the cable, usually at the Main Distribution Frame
(MDF) or patch panel in the wiring closet.
The bad polarity condition is latched in the 10BTSCR register. The DP83848I's 10BASE-T transceiver module corrects for this error internally and will continue to decode
received data correctly. This eliminates the need to correct
the wiring error immediately.
4.3.8 Transmit and Receive Filtering
External 10BASE-T filters are not required when using the
DP83848I, as the required signal conditioning is integrated
-
into the device.
Only isolation transformers and impedance matching resistors are required for the 10BASE-T transmit and receive
interface. The internal transmit filtering ensures that all the
-
harmonics in the transmit signal are attenuated by at least
30 dB.
4.3.9 Transmitter
The encoder begins operation when the Transmit Enable
input (TX_EN) goes high and converts NRZ data to preemphasized Manchester data for the transceiver. For the
duration of TX_EN, the serialized Transmit Data (TXD) is
encoded for the transmit-driver pair (PMD Output Pair).
TXD must be valid on the rising edge of Transmit Clock
(TX_CLK). Transmission ends when TX_EN deasserts.
The last transition is always positive; it occurs at the center
of the bit cell if the last bit is a one, or at the end of the bit
cell if the last bit is a zero.
4.3.10 Receiver
The decoder detects the end of a frame when no additional
mid-bit transitions are detected. Within one and a half bit
times after the last bit, carrier sense is de-asserted.
Receive clock stays active for five more bit times after CRS
goes low, to guarantee the receive timings of the controller.
www.national.com32
5.0 Design Guidelines
5.1 TPI Network Circuit
Figure 11 shows the recommended circuit for a 10/100
Mb/s twisted pair interface. To the right is a partial list of
recommended transformers. It is important that the user
realize that variations with PCB and component character
istics requires that the application be tested to ensure that
the circuit meets the requirements of the intended application.
Typically, ESD precautions are predominantly in effect
when handling the devices or board before being installed
in a system. In those cases, strict handling procedures
DP83848I
need be implemented during the manufacturing process to
greatly reduce the occurrences of catastrophic ESD
events. After the system is assembled, internal compo
nents are less sensitive from ESD events.
See Section 8.0 for ESD rating.
5.3 Clock In (X1) Requirements
The DP83848I supports an external CMOS level oscillator
source or a crystal resonator device.
capacitor values will vary with the crystal vendors; check
with the vendor for the recommended loads.
The oscillator circuit is designed to drive a parallel reso-
nance AT cut crystal with a minimum drive level of 100µW
and a maximum of 500
µW. If a crystal is specified for a
lower drive level, a current limiting resistor should be
placed in series between X2 and the crystal.
As a starting point for evaluating an oscillator circuit, if the
requirements for the crystal are not known, C
should be set at 33 pF, and R
should be set at 0Ω.
1
L1
and C
Specification for 25 MHz crystal are listed in Tab l e 9 .
L2
X1
X2
Oscillator
If an external clock source is used, X1 should be tied to the
clock source and X2 should be left floating.
R
1
Specifications for CMOS oscillators: 25 MHz in MII Mode
and 50 MHz in RMII Mode are listed in
Table 7 and Tabl e 8 .
C
L1
C
Crystal
A 25 MHz, parallel, 20 pF load crystal resonator should be
used if a crystal source is desired. Figure 12 shows a typi-
Figure 12. Crystal Oscillator Circuit
cal connection for a crystal resonator circuit. The load
Table6.
Tabl e 7. 25 MHz Oscillator Specification
ParameterMinTypMaxUnitsCondition
Frequency25MHz
Frequency
+50ppmOperational Temperature
Tolerance
Frequency
+50ppm1 year aging
Stability
Rise / Fall Time6nsec20% - 80%
Jitter
Jitter
800
800
1
1
psecShort term
psecLong term
Symmetry40%60%Duty Cycle
1
This limit is provided as a guideline for component selection and to guaranteed by production testing.
Refer to AN-1548, “PHYTER 100 Base-TX Reference Clock Jitter Tolerance,“ for details on jitter performance.
L2
www.national.com34
Tabl e 8. 50 MHz Oscillator Specification
ParameterMinTypMaxUnitsCondition
Frequency50MHz
Frequency
+50ppmOperational Temperature
Tolerance
Frequency
+50ppmOperational Temperature
Stability
Rise / Fall Time6nsec20% - 80%
Jitter
Jitter
800
800
1
1
psecShort term
psecLong term
Symmetry40%60%Duty Cycle
1
This limit is provided as a guideline for component selection and to guaranteed by production testing.
Refer to AN-1548, “PHYTER 100 Base-TX Reference Clock Jitter Tolerance,“ for details on jitter performance.
Tabl e 9. 25 MHz Crystal Specification
ParameterMinTypMaxUnitsCondition
Frequency25MHz
Frequency
Tolerance
Frequency
+50ppmOperational
Temperature
+50ppm1 year aging
Stability
Load Capacitance2540pF
DP83848I
5.4 Power Feedback Circuit
To ensure correct operation for the DP83848I, parallel caps
with values of 10
placed close to pin 23 (PFBOUT) of the device.
Pin 18 (PFBIN1) and pin 37 (PFBIN2) must be connected
to pin 23 (PFBOUT), each pin requires a small capacitor
µF). See Figure 13 below for proper connections.
(.1
Pin 23 (
PFBOUT
Pin 18 (PFBIN1)
Pin 37 (PFBIN2)
Figure 13. Power Feeback Connection
µF (Tantalum) and 0.1 µF should be
)
10 µF
+
.1 µF
-
.1 µF
.1 µF
5.5 Power Down/Interrupt
The Power Down and Interrupt functions are multiplexed
on pin 7 of the device. By default, this pin functions as a
power down input and the interrupt function is disabled.
Setting bit 0 (INT_OE) of MICR (0x11h) will configure the
pin as an active low interrupt output.
5.5.1 Power Down Control Mode
The PWR_DOWN/INT pin can be asserted low to put the
device in a Power Down mode. This is equivalent to setting
bit 11 (Power Down) in the Basic Mode Control Register,
BMCR (0x00h). An external control signal can be used to
drive the pin low, overcoming the weak internal pull-up
resistor. Alternatively, the device can be configured to ini
tialize into a Power Down state by use of an external pulldown resistor on the PWR_DOWN/INT pin. Since the
device will still respond to management register accesses,
setting the INT_OE bit in the MICR register will disable the
PWR_DOWN/INT input, allowing the device to exit the
Power Down state.
5.5.2 Interrupt Mechanisms
The interrupt function is controlled via register access. All
interrupt sources are disabled by default. Setting bit 1
(INTEN) of MICR (0x11h) will enable interrupts to be out
put, dependent on the interrupt mask set in the lower byte
of the MISR (0x12h). The PWR_DOWN/INT pin is asyn
chronously asserted low when an interrupt condition
occurs. The source of the interrupt can be determined by
reading the upper byte of the MISR. One or more bits in the
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-
-
35 www.national.com
MISR will be set, denoting all currently pending interrupts.
Reading of the MISR clears ALL pending interrupts.
Example: To generate an interrupt on a change of link status or on a change of energy detect power state, the steps
DP83848I
would be:
— Write 0003h to MICR to set INTEN and INT_OE
— Write 0060h to MISR to set ED_INT_EN and
LINK_INT_EN
— Monitor PWR_DOWN/INT pin
When PWR_DOWN/INT pin asserts low, user would read
the MISR register to see if the ED_INT or LINK_INT bits
are set, i.e. which source caused the interrupt. After read
ing the MISR, the interrupt bits should clear and the
PWR_DOWN/INT pin will deassert.
5.6 Energy Detect Mode
When Energy Detect is enabled and there is no activity on
the cable, the DP83848I will remain in a low power mode
while monitoring the transmission line. Activity on the line
will cause the DP83848I to go through a normal power up
sequence. Regardless of cable activity, the DP83848I will
occasionally wake up the transmitter to put ED pulses on
the line, but will otherwise draw as little power as possible.
Energy detect functionality is controlled via register Energy
Detect Control (EDCR), address 0x1Dh.
-
www.national.com36
6.0 Reset Operation
The DP83848I includes an internal power-on reset (POR)
function and does not need to be explicitly reset for normal
operation after power up. If required during normal opera
DP83848I
tion, the device can be reset by a hardware or software
reset.
6.1 Hardware Reset
A hardware reset is accomplished by applying a low pulse
(TTL level), with a duration of at least 1
RESET_N. This will reset the device such that all registers
will be reinitialized to default values and the hardware con
µs, to the
figuration values will be re-latched into the device (similar
to the power-up/reset operation).
6.2 Software Reset
A software reset is accomplished by setting the reset bit
(bit 15) of the Basic Mode Control Register (BMCR). The
period from the point in time when the reset bit is set to the
point in time when software reset has concluded is approx
imately 1 µs.
The software reset will reset the device such that all registers will be reset to default values and the hardware configuration values will be maintained. Software driver code
must wait 3
-
further serial MII operations with the DP83848I.
µs following a software reset before allowing
-
www.national.com37
7.0 Register Block
DP83848I
1Eh-1Fh30-31RWRESERVEDRESERVED
Offset
HexDecimal
00h0RWBMCRBasic Mode Control Register
01h1ROBMSRBasic Mode Status Register
02h2ROPHYIDR1PHY Identifier Register #1
03h3ROPHYIDR2PHY Identifier Register #2
04h4RWANARAuto-Negotiation Advertisement Register
05h5RWANLPARAuto-Negotiation Link Partner Ability Register (Base Page)
05h5RWANLPARNPAuto-Negotiation Link Partner Ability Register (Next Page)
06h6RWANERAuto-Negotiation Expansion Register
07h7RWANNPTRAuto-Negotiation Next Page TX
08h-Fh8-15RWRESERVEDRESERVED
10h16ROPHYSTSPHY Status Register
11h17RWMICRMII Interrupt Control Register
12h18ROMISRMII Interrupt Status Register
13h19RWRESERVEDRESERVED
14h20ROFCSCRFalse Carrier Sense Counter Register
15h21RORECRReceive Error Counter Register
16h22RWPCSRPCS Sub-Layer Configuration and Status Register
17h23RWRBRRMII and Bypass Register
18h24RWLEDCRLED Direct Control Register
19h25RWPHYCRPHY Control Register
1Ah26RW10BTSCR10Base-T Status/Control Register
1Bh27RWCDCTRL1CD Test Control Register and BIST Extensions Register
Register NameAddrTagBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Basic Mode Control Register
Basic Mode Status Register
PHY Identifier Register 1
PHY Identifier Register 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Regis-
ter (Base Page)
Auto-Negotiation Link Partner Ability Regis-
ter Next Page
Auto-Negotiation Expansion Register
Auto-Negotiation Next Page TX Register
RESERVED
PHY Status Register
MII Interrupt Control Register
MII Interrupt Status and Misc. Control Reg-
ister
RESERVED
False Carrier Sense Counter Register
Receive Error Counter Register
PCS Sub-Layer Configuration and Status
Register
39www.national.com
RX_RD_
Sel
PHY
_DIS
PTR[0]
ADDR
JABBER
Re-
CDPatt-
T
ED_DAT
A_COUN
Re-
served
served
DP83848I
RX_RD_
RX_UNF
RX_OVF
RMII_RE
RMII_M
Re-
Re-
Re-
Re-
Re-
PTR[1]
_STS
_STS
V1_0
ODE
served
served
served
served
served
Sel
DIS
PHY
ADDR
HEART_
Re-
PHY
ADDR
PHY
PHY
LED_
LED_
BP_STR
BIST_ST
ADDR
ADDR
CNFG[0]
CNFG[1]
ETCH
ART
STATUS
Re-
POLARI-
Re-
LP_DIS FORC_
LOOPBA
SQUELC
SQUELC
served
served
TY
served
LINK_10
CK_10_
H
H
DIS
SPDLED LNKLED ACTLED
TLED
DRV_AC
KLED
DRV_LN
DLED
DRV_SP
Re-
served
Re-
served
Re-
served
Re-
served
Re-
served
Re-
CDPatt-
p
Re-
10Meg_
Patt_Ga
Re-
Re-
served
Re-
N_10
CDPattE
Re-
ODE
BIST_C
ONT_M
Re-
Re-
served
Re-
Re-
served
Re-
OUNT
ROR_C
BIST_ER
Re-
OUNT
ROR_C
BIST_ER
Re-
BIST_ER
ROR_C
OUNT
T
ED_DAT
ED_DAT
ED_DAT
ED_ERR
ED_ERR
ED_ERR
ED_ERR
ED_DAT
ED_ERR
ED_PW
A_COUN
T
A_COUN
T
A_COUN
_COUNT
_COUNT
_COUNT
_COUNT
A_MET
_MET
R_STAT
E
Re-
served
Re-
served
Re-
served
Re-
served
Re-
served
Re-
served
Re-
served
Re-
served
Re-
served
Re-
served
served
served
served
served
served
served
served
served
served
served
BIST_fe PSR_15 BIST_
TX
PAUSE_
RX
PAUSE_
MDIX
FORCE_
N
19hPHYCR MDIX_E
H
SQUELC
RANGE
ERROR
RANGE
ERROR
100
BASE T
REJECT
10BT_S
ERIAL
ERIAL
1Ah10BT_S
Re-
OUNT
served
ROR_C
BIST_ER
Re-
OUNT
served
ROR_C
BIST_ER
Re-
ROR_C
ROR_C
ROR_C
1
OUNT
OUNT
OUNT
served
Re-
served
Re-
served
served
1ChRe-
BIST_ER
BIST_ER
BIST_ER
1BhCDCTRL
ED_MAN ED_BUR
ED_AUT
1DhEDCRED_EN ED_AUT
ST_DIS
N
O_DOW
O_UP
Re-
served
Re-
served
Re-
served
Re-
served
Re-
served
served
1Eh-1Fh Re-
Re-
Re-
Re-
Table 11. Register Table
Re-
Re-
17hRBRRe-
served
served
Re-
served
served
Re-
served
served
Re-
served
served
served
served
18hLEDCR Re-
Register NameAddrTagBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9Bit 8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
RMII and Bypass Register
LED Direct Control Register
PHY Control Register
10Base-T Status/Control Register
CD Test Control and BIST Extensions Reg-
ister
RESERVED
Energy Detect Control Register
RESERVED
www.national.com40
7.1 Register Definition
In the register definitions under the ‘Default’ heading, the following definitions hold true:
— RW=Read Write access
— SC=Register sets on event occurrence and Self-Clears when event ends
— RW/SC =Read Write access/Self Clearing bit
— RO=Read Only access
— COR = Clear on Read
— RO/COR=Read Only, Clear on Read
— RO/P=Read Only, Permanently set to a default value
— LL=Latched Low and held until read, based upon the occurrence of the corresponding event
—LH=Latched High and held until read, based upon the occurrence of the corresponding event
DP83848I
41 www.national.com
7.1.1 Basic Mode Control Register (BMCR)
Tab le 12. Basic Mode Control Register (BMCR), address 0x00
DP83848I
BitBit NameDefaultDescription
15Reset0, RW/SCReset:
14Loopback0, RWLoopback:
13Speed SelectionStrap, RWSpeed Select:
12Auto-Negotiation
Enable
11Power Down0, RWPower Down:
10Isolate0, RWIsolate:
9Restart Auto-
Negotiation
8Duplex Mode Strap, RWDuplex Mode:
1 = Initiate software Reset / Reset in Process.
0 = Normal operation.
This bit, which is self-clearing, returns a value of one until the reset
process is complete. The configuration is re-strapped.
1 = Loopback enabled.
0 = Normal operation.
The loopback function enables MII transmit data to be routed to the MII
receive data path.
Setting this bit may cause the descrambler to lose synchronization and
produce a 500 µs “dead time” before any valid data will appear at the
MII receive outputs.
When auto-negotiation is disabled writing to this bit allows the port
speed to be selected.
1 = 100 Mb/s.
0 = 10 Mb/s.
Strap, RWAuto-Negotiation Enable:
Strap controls initial value at reset.
1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this bit is set.
0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed
and duplex mode.
1 = Power down.
0 = Normal operation.
Setting this bit powers down the PHY. Only the register block is enabled during a power down condition. This bit is OR’d with the input
from the PWR_DOWN/INT pin. When the active low
PWR_DOWN/INT pin is asserted, this bit will be set.
1 = Isolates the Port from the MII with the exception of the serial management.
0 = Normal operation.
0, RW/SCRestart Auto-Negotiation:
1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If Auto-Negotiation is disabled (bit 12 = 0), this bit is ignored. This
bit is self-clearing and will return a value of 1 until Auto-Negotiation is
initiated, whereupon it will self-clear. Operation of the Auto-Negotiation
process is not affected by the management entity clearing this bit.
0 = Normal operation.
When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be selected.
1 = Full Duplex operation.
0 = Half Duplex operation.
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Table 12. Basic Mode Control Register (BMCR), address 0x00 (Continued)
BitBit NameDefaultDescription
7Collision Test0, RWCollision Test:
1 = Collision test enabled.
0 = Normal operation.
When set, this bit will cause the COL signal to be asserted in response
to the assertion of TX_EN within 512-bit times. The COL signal will be
de-asserted within 4-bit times in response to the de-assertion of
TX_EN.
6:0RESERVED0, RORESERVED: Write ignored, read as 0.
DP83848I
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7.1.2 Basic Mode Status Register (BMSR)
Tabl e 13. Basic Mode Status Register (BMSR), address 0x01
1Jabber Detect0, RO/LHJabber Detect: This bit only has meaning in 10 Mb/s mode.
0Extended Capability1, RO/PExtended Capability:
0 = Device not able to perform 100BASE-T4 mode.
1, RO/P100BASE-TX Full Duplex Capable:
1 = Device able to perform 100BASE-TX in full duplex mode.
1, RO/P100BASE-TX Half Duplex Capable:
1 = Device able to perform 100BASE-TX in half duplex mode.
1, RO/P10BASE-T Full Duplex Capable:
1 = Device able to perform 10BASE-T in full duplex mode.
1, RO/P10BASE-T Half Duplex Capable:
1 = Device able to perform 10BASE-T in half duplex mode.
1, RO/PPreamble suppression Capable:
1 = Device able to perform management transaction with preamble
suppressed, 32-bits of preamble needed only once after reset, invalid
opcode or invalid turnaround.
0 = Normal management operation.
0, ROAuto-Negotiation Complete:
1 = Auto-Negotiation process complete.
0 = Auto-Negotiation process not complete.
1 = Remote Fault condition detected (cleared on read or by reset).
Fault criteria: Far End Fault Indication or notification from Link Part
ner of Remote Fault.
0 = No remote fault condition detected.
1 = Device is able to perform Auto-Negotiation.
0 = Device is not able to perform Auto-Negotiation.
1 = Valid link established (for either 10 or 100 Mb/s operation).
0 = Link not established.
The criteria for link validity is implementation specific. The occurrence
of a link failure condition will causes the Link Status bit to clear. Once
cleared, this bit may only be set by establishing a good link condition
and a read via the management interface.
1 = Jabber condition detected.
0 = No Jabber.
This bit is implemented with a latching function, such that the occurrence of a jabber condition causes it to set until it is cleared by a read
to this register by the management interface or by a reset.
1 = Extended register capabilities.
0 = Basic register set capabilities only.
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The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83848I. The Identifier consists of a
concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision num
ber. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is
intended to support network management. National's IEEE assigned OUI is 080017h.
7.1.3 PHY Identifier Register #1 (PHYIDR1)
Tab le 14. PHY Identifier Register #1 (PHYIDR1), address 0x02
BitBit NameDefaultDescription
15:0OUI_MSB<0010 0000 0000
0000>, RO/P
7.1.4 PHY Identifier Register #2 (PHYIDR2)
Tab le 15. PHY Identifier Register #2 (PHYIDR2), address 0x03
BitBit NameDefaultDescription
15:10OUI_LSB<0101 11>, RO/P OUI Least Significant Bits:
9:4VNDR_MDL<00 1001>, RO/P Vendor Model Number:
3:0MDL_REV<0000>, RO/PModel Revision Number:
OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are
stored in bits 15 to 0 of this register. The most significant two bits
of the OUI are ignored (the IEEE standard refers to these as bits 1
and 2).
Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10
of this register respectively.
The six bits of vendor model number are mapped from bits 9 to 4
(most significant bit to bit 9).
Four bits of the vendor model revision number are mapped from
bits 3 to 0 (most significant bit to bit 3). This field will be incremented
for all major device changes.
11ASM_DIR0, RWAsymmetric PAUSE Support for Full Duplex Links:
The ASM_DIR bit indicates that asymmetric PAUSE is supported.
Encoding and resolution of PAUSE bits is defined in IEEE 802.3
Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolu
tion status is reported in PHYCR[13:12].
1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer and the pause function as specified in
clause 31 and annex 31B of 802.3u.
0= No MAC based full duplex flow control.
10PAUSE0, RWPAUSE Support for Full Duplex Links:
The PAUSE bit indicates that the device is capable of providing the
symmetric PAUSE functions as defined in Annex 31B.
Encoding and resolution of PAUSE bits is defined in IEEE 802.3
Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolu
tion status is reported in PHYCR[13:12].
1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer and the pause function as specified in
clause 31 and annex 31B of 802.3u.
0= No MAC based full duplex flow control.
9T40, RO/P100BASE-T4 Support:
1= 100BASE-T4 is supported by the local device.
0 = 100BASE-T4 not supported.
8TX_FDStrap, RW100BASE-TX Full Duplex Support:
1 = 100BASE-TX Full Duplex is supported by the local device.
0 = 100BASE-TX Full Duplex not supported.
7TXStrap, RW100BASE-TX Support:
1 = 100BASE-TX is supported by the local device.
0 = 100BASE-TX not supported.
610_FDStrap, RW10BASE-T Full Duplex Support:
1 = 10BASE-T Full Duplex is supported by the local device.
0 = 10BASE-T Full Duplex not supported.
510Strap, RW10BASE-T Support:
1 = 10BASE-T is supported by the local device.
0 = 10BASE-T not supported.
4:0Selector<00001>, RWProtocol Selection Bits:
These bits contain the binary encoded protocol selector supported
by this port. <00001> indicates that this device supports IEEE
802.3u.
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7.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content
changes after the successful auto-negotiation if Next-pages are supported.
0 = Link Partner does not desire Next Page Transfer.
14ACK0, ROAcknowledge:
1 = Link Partner acknowledges reception of the ability data word.
0 = Not acknowledged.
The Auto-Negotiation state machine will automatically control the
this bit based on the incoming FLP bursts. Software should not attempt to write to this bit.
13MP0, ROMessage Page:
1 = Message Page.
0 = Unformatted Page.
12ACK20, ROAcknowledge 2:
1 = Link Partner does have the ability to comply to next page message.
0 = Link Partner does not have the ability to comply to next page
message.
11Toggle0, ROToggle:
1 = Previous value of the transmitted Link Code word equalled 0.
0 = Previous value of the transmitted Link Code word equalled 1.
10:0CODE<000 0000 0000>, ROCode:
This field represents the code field of the next page transmission.
If the MP bit is set (bit 13 of this register), then the code shall be
interpreted as a “Message Page,” as defined in annex 28C of
Clause 28. Otherwise, the code shall be interpreted as an “Unfor
matted Page,” and the interpretation is application specific.
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7.1.8 Auto-Negotiate Expansion Register (ANER)
This register contains additional Local Device and Link Partner status information.
1 = indicates that the Link Partner supports Auto-Negotiation.
0 = indicates that the Link Partner does not support Auto-Negotiation.
7.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR)
This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.
Tab le 20. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07
BitBit NameDefaultDescription
15NP0, RWNext Page Indication:
0 = No other Next Page Transfer desired.
1 = Another Next Page desired.
14RESERVED0, RORESERVED: Writes ignored, read as 0.
13MP1, RWMessage Page:
1 = Message Page.
0 = Unformatted Page.
12ACK20, RWAcknowledge2:
1 = Will comply with message.
0 = Cannot comply with message.
Acknowledge2 is used by the next page function to indicate that Local Device has the ability to comply with the message received.
11TOG_TX0, ROToggle:
1 = Value of toggle bit in previously transmitted Link Code Word
was 0.
0 = Value of toggle bit in previously transmitted Link Code Word
was 1.
Toggle is used by the Arbitration function within Auto-Negotiation
to ensure synchronization with the Link Partner during Next Page
exchange. This bit shall always take the opposite value of the Tog
gle bit in the previously exchanged Link Code Word.
10:0CODE<000 0000 0001>, RWThis field represents the code field of the next page transmission.
If the MP bit is set (bit 13 of this register), then the code shall be
interpreted as a "Message Page”, as defined in annex 28C of IEEE
802.3u. Otherwise, the code shall be interpreted as an "Unformat
ted Page”, and the interpretation is application specific.
The default value of the CODE represents a Null Page as defined
in Annex 28C of IEEE 802.3u.
DP83848I
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7.2 Extended Registers
7.2.1 PHY Status Register (PHYSTS)
This register provides a single location within the register set for quick access to commonly accessed information.
DP83848I
Tab le 21. PHY Status Register (PHYSTS), address 0x10
BitBit NameDefaultDescription
15RESERVED0, RORESERVED: Write ignored, read as 0.
14MDI-X mode0, ROMDI-X modeas reported by the Auto-Negotiation logic:
This bit will be affected by the settings of the MDIX_EN and
FORCE_MDIX bits in the PHYCR register. When MDIX is en
abled, but not forced, this bit will update dynamically as the
Auto-MDIX algorithm swaps between MDI and MDI-X configurations.
1 = MDI pairs swapped
(Receive on TPTD pair, Transmit on TPRD pair)
0 = MDI pairs normal
(Receive on TRD pair, Transmit on TPTD pair)
13Receive Error Latch0, RO/LHReceive Error Latch:
This bit will be cleared upon a read of the RECR register.
1 = Receive error event has occurred since last read of RXERCNT
(address 0x15, Page 0).
0 = No receive error event has occurred.
12Polarity Status0, ROPolarity Status:
This bit is a duplication of bit 4 in the 10BTSCR register. This bit will
be cleared upon a read of the 10BTSCR register, but not upon a
read of the PHYSTS register.
1 = Inverted Polarity detected.
0 = Correct Polarity detected.
11False Carrier Sense
Latch
10Signal Detect0, RO/LL100Base-TX unconditional Signal Detect from PMD.
9Descrambler Lock0, RO/LL100Base-TX Descrambler Lock from PMD.
8Page Received0, ROLink Code Word Page Received:
7MII Interrupt0, ROMII Interrupt Pending:
6Remote Fault0, RORemote Fault:
0, RO/LHFalse Carrier Sense Latch:
This bit will be cleared upon a read of the FCSR register.
1 = False Carrier event has occurred since last read of FCSCR (address 0x14).
0 = No False Carrier event has occurred.
This is a duplicate of the Page Received bit in the ANER register,
but this bit will not be cleared upon a read of the PHYSTS register.
1 = A new Link Code Word Page has been received. Cleared on
read of the ANER (address 0x06, bit 1).
0 = Link Code Word Page has not been received.
1 = Indicates that an internal interrupt is pending. Interrupt source
can be determined by reading the MISR Register (0x12h). Reading
the MISR will clear the Interrupt.
0= No interrupt pending.
1 = Remote Fault condition detected (cleared on read of BMSR (address 01h) register or by reset). Fault criteria: notification from Link
Partner of Remote Fault via Auto-Negotiation.
0 = No remote fault condition detected.
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Table 21. PHY Status Register (PHYSTS), address 0x10 (Continued)
BitBit NameDefaultDescription
5Jabber Detect0, ROJabber Detect: This bit only has meaning in 10 Mb/s mode
This bit is a duplicate of the Jabber Detect bit in the BMSR register,
except that it is not cleared upon a read of the PHYSTS register.
1 = Jabber condition detected.
0 = No Jabber.
4Auto-Neg Complete0, ROAuto-Negotiation Complete:
1 = Auto-Negotiation complete.
0 = Auto-Negotiation not complete.
3Loopback Status0, ROLoopback:
1 = Loopback enabled.
0 = Normal operation.
2Duplex Status0, RODuplex:
This bit indicates duplex status and is determined from Auto-Negotiation or Forced Modes.
1 = Full duplex mode.
0 = Half duplex mode.
Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid link or if Auto-Negotiation is disabled and
there is a valid link.
1Speed Status0, ROSpeed10:
This bit indicates the status of the speed and is determined from
Auto-Negotiation or Forced Modes.
1 = 10 Mb/s mode.
0 = 100 Mb/s mode.
Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid link or if Auto-Negotiation is disabled and
there is a valid link.
0Link Status0, ROLink Status:
This bit is a duplicate of the Link Status bit in the BMSR register,
except that it will not be cleared upon a read of the PHYSTS register.
1 = Valid link established (for either 10 or 100 Mb/s operation)
0 = Link not established.
DP83848I
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7.2.2 MII Interrupt Control Register (MICR)
This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Energy
Detect State Change, Link State Change,
any of the counters becoming half-full. The individual interrupt events must be enabled by setting bits in the MII Inter-
DP83848I
Speed Status Change, Duplex Status Change, Auto-Negotiation Complete or
rupt Status and Event Control Register (MISR).
Tabl e 22. MII Interrupt Control Register (MICR), address 0x11
BitBit NameDefaultDescription
15:3Reserved0, ROReserved: Write ignored, Read as 0
2TINT0, RWTest Interrupt:
Forces the PHY to generate an interrupt to facilitate interrupt testing. Interrupts will continue to be generated as long as this bit remains set.
1 = Generate an interrupt
0 = Do not generate interrupt
1INTEN0, RWInterrupt Enable:
Enable interrupt dependent on the event enables in the MISR register.
1 = Enable event based interrupts
0 = Disable event based interrupts
0INT_OE0, RWInterrupt Output Enable:
Enable interrupt events to signal via the PWR_DOWN/INT pin by
configuring the PWR_DOWN/INT pin as an output.
1 = PWR_DOWN/INT is an Interrupt Output
0 = PWR_DOWN/INT is a Power Down Input
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7.2.3 MII Interrupt Status and Misc. Control Register (MISR)
This register contains event status and enables for the interrupt function. If an event has occurred since the last read of
this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set, an interrupt
will be generated if the event occurs. The MICR register controls must also be set to allow interrupts. The status indi
cations in this register will be set even if the interrupt is not enabled
Tab le 23. MII Interrupt Status and Misc. Control Register (MISR), address 0x12
15Reserved0, RORESERVED: Writes ignored, Read as 0
14ED_INT0, RO/COREnergy Detect interrupt:
1 = Energy detect interrupt is pending and is cleared by the current
read.
0 = No energy detect interrupt pending.
13LINK_INT0, RO/CORChange of Link Status interrupt:
1 = Change of link status interrupt is pending and is cleared by the
current read.
0 = No change of link status interrupt pending.
12SPD_INT0, RO/CORChange of speed status interrupt:
1 = Speed status change interrupt is pending and is cleared by the
current read.
0 = No speed status change interrupt pending.
11DUP_INT0, RO/CORChange of duplex status interrupt:
1 = Duplex status change interrupt is pending and is cleared by
the current read.
1 = Receive error counter half-full interrupt is pending and is
cleared by the current read.
0 = No receive error carrier counter half-full interrupt pending.
7RESERVED0, RORESERVED: Writes ignored, Read as 0
6ED_INT_EN0, RWEnable Interrupt on energy detect event
5LINK_INT_EN0, RWEnable Interrupt on change of link status
4SPD_INT_EN0, RWEnable Interrupt on change of speed status
3DUP_INT_EN0, RWEnable Interrupt on change of duplex status
2ANC_INT_EN0, RWEnable Interrupt on Auto-negotiation complete event
1FHF_INT_EN0, RWEnable Interrupt on False Carrier Counter Register half-full event
0RHF_INT_EN0, RWEnable Interrupt on Receive Error Counter Register half-full event
DP83848I
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7.2.4 False Carrier Sense Counter Register (FCSCR)
This counter provides information required to implement the “False Carriers” attribute within the MAU managed object
class of Clause 30 of the IEEE 802.3u specification.
DP83848I
Tabl e 24. False Carrier Sense Counter Register (FCSCR), address 0x14
BitBit NameDefaultDescription
15:8RESERVED0, RORESERVED: Writes ignored, Read as 0
This 8-bit counter increments on every false carrier event. This
counter sticks when it reaches its max count (FFh).
7.2.5 Receiver Error Counter Register (RECR)
This counter provides information required to implement the “Symbol Error During Carrier” attribute within the PHY managed object class of Clause 30 of the IEEE 802.3u specification.
15:8RESERVED0, RORESERVED: Writes ignored, Read as 0
7:0RXERCNT[7:0]0, RO / CORRX_ER Counter:
When a valid carrier is present and there is at least one occurrence
of an invalid data symbol, this 8-bit counter increments for each re
ceive error detected. This event can increment only once per valid
carrier event. If a collision is present, the attribute will not incre
ment. The counter sticks when it reaches its max count.
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7.2.6 100 Mb/s PCS Configuration and Status Register (PCSR)
Tab le 26. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16
BitBit NameDefaultDescription
15:13RESERVED<00>, RORESERVED: Writes ignored, Read as 0.
12RESERVED0RESERVED:
Must be zero.
11RESERVED0RESERVED:
Must be zero.
10TQ_EN
9SD FORCE PMA
8SD_OPTION1, RWSignal Detect Option:
7DESC_TIME0, RWDescrambler Timeout:
6RESERVED0RESERVED:
5FORCE_100_OK0, RWForce 100Mb/s Good Link:
4RESERVED0RESERVED:
3RESERVED0RESERVED:
2NRZI_BYPASS0, RWNRZI Bypass Enable:
1RESERVED0RESERVED:
0RESERVED0RESERVED:
0, RW
0,RW
100Mbs True Quiet Mode Enable:
1 = Transmit True Quiet Mode.
0 = Normal Transmit Mode.
Signal Detect Force PMA:
1 = Forces Signal Detection in PMA.
0 = Normal SD operation.
1 = Enhanced signal detect algorithm.
0 = Reduced signal detect algorithm.
Increase the descrambler timeout. When set this should allow the
device to receive larger packets (>9k bytes) without loss of synchronization.
This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed.
DP83848I
BitBit NameDefaultDescription
15:6RESERVED0, RORESERVED: Writes ignored, read as 0.
5RMII_MODEStrap, RWReduced MII Mode:
4RMII_REV1_00, RWReduce MII Revision 1.0:
3RX_OVF_STS0, RORX FIFO Over Flow Status:
2RX_UNF_STS0, RORX FIFO Under Flow Status:
1:0ELAST_BUF[1:0]01, RWReceive Elasticity Buffer. This field controls the Receive Elastic-
Table 27. RMII and Bypass Register (RBR), addresses 0x17
0 = Standard MII Mode
1 = Reduced MII Mode
0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet
to indicate deassertion of CRS.
1 = (RMII revision 1.0) CRS_DV will remain asserted until final data
is transferred. CRS_DV will not toggle at the end of a packet.
0 = Normal
1 = Overflow detected
0 = Normal
1 = Underflow detected
ity Buffer which allows for frequency variation tolerance between
the 50MHz RMII clock and the recovered data. The following values indicate the tolerance in bits for a single packet. The minimum
setting allows for standard Ethernet frame sizes at +/-50ppm accu
racy for both RMII and Receive clocks. For greater frequency tolerance the packet lengths may be scaled (i.e. for +/-100ppm, the
packet lengths need to be divided by 2).
00 = 14 bit tolerance (up to 16800 byte packets)
01 = 2 bit tolerance (up to 2400 byte packets)
10 = 6 bit tolerance (up to 7200 byte packets)
11 = 10 bit tolerance (up to 12000 byte packets)
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7.2.8 LED Direct Control Register (LEDCR)
This register provides the ability to directly control any or all LED outputs. It does not provide read access to LEDs.
Tab le 28. LED Direct Control Register (LEDCR), address 0x18
BitBit NameDefaultDescription
15:6RESERVED0, RORESERVED: Writes ignored, read as 0.
5DRV_SPDLED0, RW1 = Drive value of SPDLED bit onto LED_SPD output
0 = Normal operation
4DRV_LNKLED0, RW1 = Drive value of LNKLED bit onto LED_LNK output
0 = Normal operation
3DRV_ACTLED0, RW1 = Drive value of ACTLED bit onto LED_ACT/COL output
0 = Normal operation
2SPDLED0, RWValue to force on LED_SPD output
1LNKLED0, RWValue to force on LED_LNK output
0ACTLED0, RWValue to force on LED_ACT/COL output
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7.2.9 PHY Control Register (PHYCR)
Tabl e 29. PHY Control Register (PHYCR), address 0x19
BitBit NameDefaultDescription
15MDIX_ENStrap, RWAuto-MDIX Enable:
1 = Enable Auto-neg Auto-MDIX capability.
0 = Disable Auto-neg Auto-MDIX capability.
The Auto-MDIX algorithm requires that the Auto-Negotiation Enable bit in the BMCR register to be set. If Auto-Negotiation is not
enabled, Auto-MDIX should be disabled as well.
14FORCE_MDIX0, RWForce MDIX:
1 = Force MDI pairs to cross.
(Receive on TPTD pair, Transmit on TPRD pair)
0 = Normal operation.
13PAUSE_RX0, ROPause Receive Negotiated:
Indicates that pause receive should be enabled in the MAC. Based
on ANAR[11:10] and ANLPAR[11:10] settings.
This function shall be enabled according to IEEE 802.3 Annex 28B
Table 28B-3, “Pause Resolution”, only if the Auto-Negotiated High
est Common Denominator is a full duplex technology.
12PAUSE_TX0, ROPause Transmit Negotiated:
Indicates that pause transmit should be enabled in the MAC. Based
on ANAR[11:10] and ANLPAR[11:10] settings.
This function shall be enabled according to IEEE 802.3 Annex 28B
Table 28B-3, “Pause Resolution”, only if the Auto-Negotiated High
est Common Denominator is a full duplex technology.
11BIST_FE0, RW/SCBIST Force Error:
1 = Force BIST Error.
0 = Normal operation.
This bit forces a single error, and is self clearing.
10PSR_150, RWBIST Sequence select:
1 = PSR15 selected.
0 = PSR9 selected.
9BIST_STATUS0, LL/ROBIST Test Status:
1 = BIST pass.
0 = BIST fail. Latched, cleared when BIST is stopped.
For a count number of BIST errors, see the BIST Error Count in the
CDCTRL1 register.
8BIST_START0, RWBIST Start:
1 = BIST start.
0 = BIST stop.
7BP_STRETCH0, RWBypass LED Stretching:
This will bypass the LED stretching and the LEDs will reflect the internal value.
1 = Bypass LED stretching.
0 = Normal operation.
DP83848I
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Table 29. PHY Control Register (PHYCR), address 0x19 (Continued)
BitBit NameDefaultDescription
DP83848I
6
5
4:0PHYADDR[4:0]Strap, RWPHY Address: PHY address for port.
LED_CNFG[1]
LED_CNFG[0]
0, RW
Strap, RW
LEDs Configuration
LED_CNFG[1] LED_ CNFG[0] Mode Description
Don’t care1Mode 1
00Mode 2
10Mode 3
In Mode 1, LEDs are configured as follows:
LED_LINK = ON for Good Link, OFF for No Link
LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s
LED_ACT/COL = ON for Activity, OFF for No Activity
In Mode 2, LEDs are configured as follows:
LED_LINK = ON for good Link, BLINK for Activity
LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s
LED_ACT/COL = ON for Collision, OFF for No Collision
Full Duplex, OFF for Half Duplex
In Mode 3, LEDs are configured as follows:
LED_LINK = ON for Good Link, BLINK for Activity
LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s
LED_ACT/COL = ON for Full Duplex, OFF for Half Duplex
Places 10 Mb/s transmit and receive functions in Serial Network
Interface (SNI) Mode of operation. Has no effect on 100 Mb/s
operation.
14:12RESERVED0, RWRESERVED:
Must be zero.
11:9SQUELCH100, RWSquelch Configuration:
Used to set the Squelch ‘ON’ threshold for the receiver.
Default Squelch ON is 330mV peak.
8LOOPBACK_10_D
IS
0, RW In half-duplex mode, default 10BASE-T operation loops Transmit
data to the Receive data in addition to transmitting the data on the
physical medium. This is for consistency with earlier 10BASE2 and
10BASE5 implementations which used a shared medium. Setting
this bit disables the loopback function.
This bit does not affect loopback due to setting BMCR[14].
This bit is a duplication of bit 12 in the PHYSTS register. Both bits
will be cleared upon a read of 10BTSCR register, but not upon a
read of the PHYSTS register.
1 = Inverted Polarity detected.
0 = Correct Polarity detected.
3RESERVED0, RWRESERVED:
Must be zero.
2RESERVED1, RWRESERVED:
Must be set to one.
1HEARTBEAT_DIS0, RWHeartbeat Disable: This bit only has influence in half-duplex 10Mb
mode.
1 = Heartbeat function disabled.
0 = Heartbeat function enabled.
When the device is operating at 100Mb or configured for full
duplex operation, this bit will be ignored - the heartbeat func
tion is disabled.
0JABBER_DIS0, RWJabber Disable:
Applicable only in 10BASE-T.
1 = Jabber function disabled.
0 = Jabber function enabled.
DP83848I
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7.2.11 CD Test and BIST Extensions Register (CDCTRL1)
Tabl e 31. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B
DP83848I
BitBit NameDefaultDescription
15:8BIST_ERROR_CO
UNT
7:6RESERVED0, RWRESERVED:
5BIST_CONT_MOD
E
4CDPATTEN_100, RWCD Pattern Enable for 10Mb:
3RESERVED0, RWRESERVED:
210MEG_PATT_GA
P
1:0CDPATTSEL[1:0]00, RWCD Pattern Select[1:0]:
0, ROBIST ERROR Counter:
0, RWPacket BIST Continuous Mode:
0, RWDefines gap between data or NLP test sequences:
Counts number of errored data nibbles during Packet BIST. This
value will reset when Packet BIST is restarted. The counter sticks
when it reaches its max count.
Must be zero.
Allows continuous pseudo random data transmission without any
break in transmission. This can be used for transmit VOD testing.
This is used in conjunction with the BIST controls in the PHYCR
Register (0x19h). For 10Mb operation, jabber function must be dis
abled, bit 0 of the 10BTSCR (0x1Ah), JABBER_DIS = 1.
11 = Constant Manchester 1s (10MHz sine wave) for harmonic distortion testing.
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7.2.12 Energy Detect Control (EDCR)
Tabl e 32. Energy Detect Control (EDCR), address 0x1D
BitBit NameDefaultDescription
15ED_EN0, RWEnergy Detect Enable:
Allow Energy Detect Mode.
When Energy Detect is enabled and Auto-Negotiation is disabled
via the BMCR register, Auto-MDIX should be disabled via the PHY
CR register.
14ED_AUTO_UP1, RWEnergy Detect Automatic Power Up:
Automatically begin power up sequence when Energy Detect Data
Threshold value (EDCR[3:0]) is reached. Alternatively, device
could be powered up manually using the ED_MAN bit (ECDR[12]).
13ED_AUTO_DOWN1, RWEnergy Detect Automatic Power Down:
Automatically begin power down sequence when no energy is detected. Alternatively, device could be powered down using the
ED_MAN bit (EDCR[12]).
12ED_MAN0, RW/SCEnergy Detect Manual Power Up/Down:
Begin power up/down sequence when this bit is asserted. When
set, the Energy Detect algorithm will initiate a change of Energy De
tect state regardless of threshold (error or data) and timer values.
In managed applications, this bit can be set after clearing the Energy Detect interrupt to control the timing of changing the power
state.
11ED_BURST_DIS0, RWEnergy Detect Bust Disable:
Disable bursting of energy detect data pulses. By default, Energy
Detect (ED) transmits a burst of 4 ED data pulses each time the CD
is powered up. When bursting is disabled, only a single ED data
pulse will be send each time the CD is powered up.
10ED_PWR_STATE0, ROEnergy Detect Power State:
Indicates current Energy Detect Power state. When set, Energy
Detect is in the powered up state. When cleared, Energy Detect is
in the powered down state. This bit is invalid when Energy Detect
is not enabled.
Threshold to determine the number of energy detect error events
that should cause the device to take action. Intended to allow averaging of noise that may be on the line. Counter will reset after approximately 2 seconds without any energy detect data events.
3:0ED_DATA_COUNT0001, RWEnergy Detect Data Threshold:
Threshold to determine the number of energy detect events that
should cause the device to take actions. Intended to allow averag
ing of noise that may be on the line. Counter will reset after approximately 2 seconds without any energy detect data events.
DP83848I
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8.0 Electrical Specifications
Note: All parameters are guaranteed by test, statistical analysis or design.
DP83848I
Absolute Maximum Ratings
Supply Voltage (VCC)-0.5 V to 4.2 V
DC Input Voltage (VIN)-0.5V to VCC + 0.5V
DC Output Voltage (V
Storage Temperature (T
Max case temp for TA = 85°C107 °C
Max. die temperature (Tj)150 °C
Lead Temp. (TL)
(Soldering, 10 sec.)
ESD Rating
(R
= 1.5k, C
ZAP
ZAP
Recommended Operating Conditions
Supply voltage (VCC)3.3 Volts + .3V
Industrial - Ambient Temperature (TA)
Power Dissipation (PD)267 mW
)-0.5V to VCC + 0.5V
OUT
)
STG
-65oC to 150°C
= 100 pF)
260 °C
4.0 kV
-40 to 85 °C
Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not
meant to imply that the device should be operated at these limits.
Thermal Characteristic
Theta Junction to Case (Tjc)
Theta Junction to Ambient (Tja) degrees Celsius/Watt - No Airflow @ 1.0W
MaxUnits
28.7°C / W
83.6°C / W
Note: This is done with a JEDEC (2 layer 2 oz CU.) thermal test board
8.1 DC Specs
SymbolPin TypesParameterConditionsMinTypMaxUnits
V
IH
V
IL
I
IH
I
IL
V
OL
V
OH
I
OZ
I
I/O
I
I/O
I
I/O
I
I/O
O,
I/O
O,
I/O
I/O,
O
Input High Voltage Nominal V
CC
2.0V
Input Low Voltage0.8V
Input High Current VIN = V
Input Low Current V
Output Low
= GND10µA
IN
IOL = 4 mA0.4V
CC
10µA
Voltage
Output High
IOH = -4 mAVcc - 0.5V
Voltage
TRI-STATE
Leakage
V
OUT
= V
CC
+ 10µA
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SymbolPin TypesParameterConditionsMinTypMaxUnits
DP83848I
V
TPTD_100
V
TPTDsym
V
TPTD_10
C
IN1
C
OUT1
SD
THon
SD
THoff
V
TH1
I
dd100
I
dd10
I
dd
PMD Output
Pair
PMD Output
Pair
PMD Output
Pair
100M Transmit
Voltage
100M Transmit
Voltage Symmetry
10M Transmit
Voltage
ICMOS Input
Capacitance
OCMOS Output
Capacitance
PMD Input
Pair
100BASE-TX
Signal detect turnon threshold
PMD Input
Pair
100BASE-TX
Signal detect turnoff threshold
PMD Input
Pair
10BASE-T Receive Threshold
Supply100BASE-TX
(Full Duplex)
Supply10BASE-T
(Full Duplex)
SupplyPower Down
Mode
0.9511.05V
+ 2%
2.22.52.8V
5pF
5pF
1000mV diff pk-pk
200mV diff pk-pk
585mV
81mA
92mA
14mA
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8.2 AC Specs
8.2.1 Power Up Timing
DP83848I
Hardware
RESET_N
Vcc
X1 clock
T2.1.1
32 clocks
MDC
T2.1.2
Latch-In of Hardware
Configuration Pins
input
Dual Function Pins
Become Enabled As Outputs
ParameterDescriptionNotesMinTypMaxUnits
T2.1.1Post Power Up Stabilization
time prior to MDC preamble for
register accesses
T2.1.2Hardware Configuration Latch-
in Time from power up
T2.1.3Hardware Configuration pins
transition to output drivers
MDIO is pulled high for 32-bit serial management initialization
X1 Clock must be stable for a min. of
167ms at power up.
Hardware Configuration Pins are described in the Pin Description section
X1 Clock must be stable for a min. of
167ms at power up.
T2.1.3
output
167ms
167ms
50ns
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8.2.2 Reset Timing
Vcc
X1 clock
Hardware
RESET_N
MDC
DP83848I
T2.2.1
T2.2.4
32 clocks
T2.2.2
Latch-In of Hardware
Configuration Pins
input
Dual Function Pins
Become Enabled As Outputs
ParameterDescriptionNotesMinTypMaxUnits
T2.2.1Post RESET Stabilization time
prior to MDC preamble for register accesses
T2.2.2Hardware Configuration Latch-
in Time from the Deassertion
of RESET (either soft or hard)
T2.2.3Hardware Configuration pins
transition to output drivers
T2.2.4RESET pulse widthX1 Clock must be stable for at min. of 1us
MDIO is pulled high for 32-bit serial management initialization
Hardware Configuration Pins are described in the Pin Description section
during RESET pulse low time.
T2.2.3
output
3µs
3µs
50ns
1µs
Note: It is important to choose pull-up and/or pull-down resistors for each of the hardware configuration pins that provide
fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver.
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8.2.3 MII Serial Management Timing
DP83848I
MDC
MDIO (output)
MDC
T2.3.1
T2.3.4
T2.3.2T2.3.3
MDIO (input)
ParameterDescriptionNotesMinTypMaxUnits
T2.3.1MDC to MDIO (Output) Delay Time030ns
T2.3.2MDIO (Input) to MDC Setup Time10ns
T2.3.3MDIO (Input) to MDC Hold Time10ns
T2.3.4MDC Frequency2.525MHz
8.2.4 100 Mb/s MII Transmit Timing
T2.4.1
TX_CLK
T2.4.2
TXD[3:0]
TX_EN
Valid Data
T2.4.1
T2.4.3
Valid Data
ParameterDescriptionNotesMinTypMax Units
T2.4.1TX_CLK High/Low Time100 Mb/s Normal mode162024ns
T2.4.2TXD[3:0], TX_EN Data Setup to TX_CLK100 Mb/s Normal mode10ns
T2.4.3TXD[3:0], TX_EN Data Hold from TX_CLK 100 Mb/s Normal mode0ns
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8.2.5 100 Mb/s MII Receive Timing
DP83848I
T2.5.1
RX_CLK
T2.5.1
T2.5.2
RXD[3:0]
RX_DV
RX_ER
ParameterDescriptionNotesMinTypMaxUnits
T2.5.1RX_CLK High/Low Time100 Mb/s Normal mode162024ns
T2.5.2RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode1030ns
Note: RX_CLK may be held low or high for a longer period of time during transition between reference and recovered
clocks. Minimum high and low times will not be violated.
8.2.6 100BASE-TX Transmit Packet Latency Timing
Valid Data
TX_CLK
TX_EN
TXD
PMD Output Pair
ParameterDescriptionNotesMinTypMaxUnits
T2.6.1TX_CLK to PMD Output Pair
Latency
Note: For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after
the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100
Mb/s mode.
Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the first bit of the “T” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
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8.2.8 100BASE-TX Transmit Timing (t
+1 rise
& Jitter)
R/F
DP83848I
T2.8.1
90%
T2.8.1
10%
-1 fall
10%
90%
T2.8.1
-1 rise
T2.8.1
PMD Output Pair
T2.8.2
PMD Output Pair
eye pattern
ParameterDescriptionNotesMinTypMaxUnits
T2.8.1100 Mb/s PMD Output Pair tR
and t
F
100 Mb/s tR and tF Mismatch500ps
+1 fall
T2.8.2
345ns
T2.8.2100 Mb/s PMD Output Pair
Transmit Jitter
Note: Normal Mismatch is the difference between the maximum and minimum of all rise and fall times
Note: Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude
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1.4ns
8.2.9 100BASE-TX Receive Packet Latency Timing
DP83848I
PMD Input Pair
CRS
RXD[3:0]
RX_DV
RX_ER
ParameterDescriptionNotesMinTypMaxUnits
T2.9.1Carrier Sense ON Delay100 Mb/s Normal mode20bits
T2.9.2Receive Data Latency100 Mb/s Normal mode24bits
Note: Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion
of Carrier Sense.
Note: 1 bit time = 10 ns in 100 Mb/s mode
Note: PMD Input Pair voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.
T2.10.1Carrier Sense OFF Delay100 Mb/s Normal mode24bits
Note: Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.
Note: 1 bit time = 10 ns in 100 Mb/s mode
DATA
(T/R)
T2.10.1
IDLE
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8.2.11 10 Mb/s MII Transmit Timing
DP83848I
T2.11.1
TX_CLK
T2.11.2
TXD[3:0]
TX_EN
ParameterDescriptionNotesMinTypMax Units
T2.11.1TX_CLK High/Low Time 10 Mb/s MII mode190200210ns
T2.11.2TXD[3:0], TX_EN Data Setup to TX_CLK fall 10 Mb/s MII mode25ns
T2.11.3TXD[3:0], TX_EN Data Hold from TX_CLK rise 10 Mb/s MII mode0ns
Note: An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII
signals are sampled on the falling edge of TX_CLK.
8.2.12 10 Mb/s MII Receive Timing
Valid Data
T2.11.1
T2.11.3
T2.12.1
RX_CLK
T2.12.2
RXD[3:0]
RX_DV
ParameterDescriptionNotesMinTypMaxUnits
T2.12.1RX_CLK High/Low Time160200240ns
T2.12.2RX_CLK to RXD[3:0], RX_DV Delay10 Mb/s MII mode100ns
T2.12.3RX_CLK rising edge delay from RXD[3:0],
RX_DV Valid
Note: RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks.
Minimum high and low times will not be violated.
T2.12.3
Valid Data
10 Mb/s MII mode100ns
T2.12.1
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8.2.13 10 Mb/s Serial Mode Transmit Timing
DP83848I
TX_CLK
TXD[0]
TX_EN
ParameterDescriptionNotesMinTypMax Units
T2.13.1TX_CLK High Time 10 Mb/s Serial mode202530ns
T2.13.2TX_CLK Low Time 10 Mb/s Serial mode707580ns
T2.13.3TXD_0, TX_EN Data Setup to TX_CLK rise 10 Mb/s Serial mode25ns
T2.13.4TXD_0, TX_EN Data Hold from TX_CLK rise 10 Mb/s Serial mode0ns
8.2.14 10 Mb/s Serial Mode Receive Timing
T2.13.1
T2.13.3
T2.13.4
Valid Data
T2.13.2
T2.14.1
RX_CLK
T2.14.1
T2.14.2
RXD[0]
RX_DV
ParameterDescriptionNotesMinTypMaxUnits
T2.14.1RX_CLK High/Low Time355065ns
T2.14.2RX_CLK fall to RXD_0, RX_DV Delay10 Mb/s Serial mode-1010ns
Note: RX_CLK may be held high for a longer period of time during transition between reference and recovered clocks.
Minimum high and low times will not be violated.
Valid Data
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8.2.15 10BASE-T Transmit Timing (Start of Packet)
TX_CLK
TX_EN
TXD
T2.15.2
PMD Output Pair
T2.15.1
ParameterDescriptionNotesMinTypMaxUnits
T2.15.1Transmit Output Delay from the
Falling Edge of TX_CLK
T2.15.2Transmit Output Delay from the
Rising Edge of TX_CLK
10 Mb/s MII mode3.5bits
10 Mb/s Serial mode3.5bits
DP83848I
Note: 1 bit time = 100 ns in 10Mb/s.
8.2.16 10BASE-T Transmit Timing (End of Packet)
TX_CLK
TX_EN
PMD Output Pair
PMD Output Pair
ParameterDescriptionNotesMinTypMaxUnits
T2.16.1End of Packet High Time
(with ‘0’ ending bit)
T2.16.2End of Packet High Time
(with ‘1’ ending bit)
00
T2.16.2
11
250300ns
250300ns
T2.16.1
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8.2.17 10BASE-T Receive Timing (Start of Packet)
DP83848I
101010101011
TPRD±
T2.17.1
CRS
RX_CLK
T2.17.2
RX_DV
1st SFD bit decoded
T2.17.3
RXD[3:0]
ParameterDescriptionNotesMinTypMaxUnits
T2.17.1Carrier Sense Turn On Delay (PMD
Input Pair to CRS)
T2.17.2RX_DV Latency10bits
T2.17.3Receive Data LatencyMeasurement shown from SFD8bits
Note: 10BASE-T RX_DV Latency is measured from first bit of preamble on the wire to the assertion of RX_DV
Note: 1 bit time = 100 ns in 10 Mb/s mode.
8.2.18 10BASE-T Receive Timing (End of Packet)
PMD Input Pair
RX_CLK
0000
1
PreambleSFDData
6301000ns
0
1
IDLE
CRS
ParameterDescriptionNotesMinTypMaxUnits
T2.18.1Carrier Sense Turn Off Delay1.0µs
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T2.18.1
8.2.19 10 Mb/s Heartbeat Timing
TX_EN
DP83848I
TX_CLK
T2.19.1
COL
ParameterDescriptionNotesMinTypMaxUnits
T2.19.1CD Heartbeat Delay All 10 Mb/s modes1200ns
T2.19.2CD Heartbeat Duration All 10 Mb/s modes1000ns
8.2.20 10 Mb/s Jabber Timing
TXE
T2.20.1
PMD Output Pair
T2.19.2
T2.20.2
COL
ParameterDescriptionNotesMinTypMaxUnits
T2.20.1Jabber Activation Time85ms
T2.20.2Jabber Deactivation Time500ms
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8.2.21 10BASE-T Normal Link Pulse Timing
DP83848I
T2.21.1
Normal Link Pulse(s)
ParameterDescriptionNotesMinTypMaxUnits
T2.21.1Pulse Width100ns
T2.21.2Pulse Period16ms
Note: These specifications represent transmit timings.
8.2.22 Auto-Negotiation Fast Link Pulse (FLP) Timing
T2.22.3
T2.22.1
Fast Link Pulse(s)
T2.21.2
T2.22.2
T2.22.1
clock
pulse
T2.22.4
FLP BurstFLP Burst
ParameterDescriptionNotesMinTypMaxUnits
T2.22.1Clock, Data Pulse Width100ns
T2.22.2Clock Pulse to Clock Pulse
T2.22.3Clock Pulse to Data Pulse
T2.22.4Burst Width2ms
T2.22.5FLP Burst to FLP Burst Period16ms
Note: These specifications represent transmit timings.
Period
Period
data
pulse
T2.22.5
Data = 162µs
clock
pulse
125µs
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8.2.23 100BASE-TX Signal Detect Timing
PMD Input Pair
T2.23.1
T2.23.2
SD+ internal
ParameterDescriptionNotesMinTypMaxUnits
T2.23.1SD Internal Turn-on Time1ms
T2.23.2SD Internal Turn-off Time350µs
Note: The signal amplitude on PMD Input Pair must be TP-PMD compliant.
8.2.24 100 Mb/s Internal Loopback Timing
TX_CLK
DP83848I
TX_EN
TXD[3:0]
CRS
RX_CLK
RX_DV
RXD[3:0]
ParameterDescriptionNotesMinTypMaxUnits
T2.24.1TX_EN to RX_DV Loopback100 Mb/s internal loopback mode240ns
T2.24.1
Note1: Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time”
of up to 550 µs during which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is
based on device delays after the initial 550µs “dead-time”.
Note2: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
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8.2.25 10 Mb/s Internal Loopback Timing
DP83848I
TX_CLK
TX_EN
TXD[3:0]
CRS
RX_CLK
RX_DV
RXD[3:0]
T2.25.1
ParameterDescriptionNotesMinTypMaxUnits
T2.25.1TX_EN to RX_DV Loopback10 Mb/s internal loopback mode2µs
Note: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
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8.2.26 RMII Transmit Timing
X1
DP83848I
T2.26.1
TXD[1:0]
TX_EN
T2.26.2
Valid Data
T2.26.3
T2.26.4
PMD Output Pair
ParameterDescriptionNotesMinTyp Max Units
T2.26.1X1 Clock Period50 MHz Reference Clock20ns
T2.26.2TXD[1:0], TX_EN, Data Setup
to X1 rising
T2.26.3TXD[1:0], TX_EN, Data Hold
T2.26.4X1 Clock to PMD Output Pair
from X1 rising
From X1 Rising edge to first bit of symbol 17bits
Latency
Symbol
4ns
2ns
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8.2.27 RMII Receive Timing
DP83848I
PMD Input Pair
X1
RX_DV
CRS_DV
T2.27.3
IDLE
(J/K)
T2.27.2
Data
T2.27.5
(TR)
T2.27.4
T2.27.1
T2.27.2
Data
T2.27.2
T2.27.2
RXD[1:0]
RX_ER
ParameterDescriptionNotesMinTypMaxUnits
T2.27.1X1 Clock Period50 MHz Reference Clock20ns
T2.27.2RXD[1:0], CRS_DV, RX_DV
and RX_ER output delay from
X1 rising
T2.27.3CRS ON delayFrom JK symbol on PMD Receive Pair to
initial assertion of CRS_DV
T2.27.4CRS OFF delayFrom TR symbol on PMD Receive Pair to
initial deassertion of CRS_DV
T2.27.5RXD[1:0] and RX_ER latencyFrom symbol on Receive Pair. Elasticity
buffer set to default value (01)
214ns
18.5bits
27bits
38bits
Note: Per the RMII Specification, output delays assume a 25pF load.
Note: CRS_DV is asserted asynchronously in order to minimize latency of control signals through the why. CRS_DV may
toggle synchronously at the end of the packet to indicate CRS deassertion.
Note: RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of
receive data.
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8.2.28 Isolation Timing
Clear bit 10 of BMCR
(return to normal operation
from Isolate mode)
T2.28.1
H/W or S/W Reset
(with PHYAD = 00000)
T2.28.2
MODE
ISOLATE
ParameterDescriptionNotesMinTypMaxUnits
T2.28.1From software clear of bit 10 in
the BMCR register to the transition from Isolate to Normal Mode
T2.28.2From Deassertion of S/W or H/W
Reset to transition from Isolate to
Normal mode
NORMAL
100µs
500µs
DP83848I
8.2.29 25 MHz_OUT Timing
X1
T2.29.2
T2.29.1T2.29.1
25 MHz_OUT
ParameterDescriptionNotesMinTypMaxUnits
T2.29.125 MHz_OUT High/Low TimeMII mode20ns
RMII mode10ns
T2.29.225 MHz_OUT propagation delayRelative to X18ns
Note: 25 MHz_OUT characteristics are dependent upon the X1 input characteristics.
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8.2.30 100 Mb/s X1 to TX_CLK Timing
DP83848I
X1
T2.30.1
TX_CLK
ParameterDescriptionNotesMinTypMaxUnits
T2.30.1X1 to TX_CLK delay100 Mb/s Normal mode05ns
Note: X1 to TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit
Mll data.
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Notes:
DP83848I
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9.0 Physical Dimensions
inches (millimeters) unless otherwise noted
Lead Quad Frame Package (LQFP)
NS Package Number VBH48A
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Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and
whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected
to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
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