National Semiconductor DP83816 Technical data

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September 2005

DP83816 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPHYTER-II

™

)

DP83816 10/100 Mb/s Integrated PCI Ethernet Media Access Controller and Physical Layer (MacPHYTER-II™)

General Description

DP83816 is a single-chip 10/100 Mb/s Ethernet Controller for the PCI bus. It is targeted at low-cost, high volume PC motherboards, adapter cards, and embedded systems. The DP83816 fully implements the V2.2 33 MHz PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83816 can support full duplex 10/100 Mb/s transmission and reception, with minimum interframe gap.

The DP83816 device is an integration of an enhanced version of the National Semiconductor PCI MAC/BIU (Media Access Controller/Bus Interface Unit) and a 3.3V CMOS physical layer interface.

Features

— IEEE 802.3 Compliant, PCI V2.2 MAC/BIU supports

traditional data rates of 10 Mb/s Ethernet and 100 Mb/s

Fast Ethernet (via internal phy) — Bus master - burst sizes of up to 128 dwords (512 bytes) — BIU compliant with PC 97 and PC 98 Hardware Design

Guides, PC 99 Hardware Design Guide draft, ACPI v1.0,

PCI Power Management Specification v1.1, OnNow

Device Class Power Management Reference

Specification - Network Device Class v1.0a — Wake on LAN (WOL) support compliant with PC98,

PC99, SecureOn, and OnNow, including directed

packets, Magic Packet, VLAN packets, ARP packets,

pattern match packets, and Phy status change — Clkrun function for PCI Mobile Design Guide — Virtual LAN (VLAN) and long frame support

— Support for IEEE 802.3x Full duplex flow control — Extremely flexible Rx packet filtration including: single

address perfect filter with MSb masking, broadcast, 512 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns

— Statistics gathered for support of RFC 1213 (MIB II),

RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing

CPU overhead for management — Internal 2 KB Transmit and 2 KB Receive data FIFOs — Serial EEPROM port with auto-load of configuration data

from EEPROM at power-on — Flash/PROM interface for remote boot support — Fully integrated IEEE 802.3/802.3u 3.3V CMOS physical

layer — IEEE 802.3 10BASE-T transceiver with integrated filters — IEEE 802.3u 100BASE-TX transceiver — Fully integrated ANSI X3.263 compliant TP-PMD

physical sublayer with adaptive equalization and

Baseline Wander compensation — IEEE 802.3u Auto-Negotiation - advertised features

configurable via EEPROM — Full Duplex support for 10 and 100 Mb/s data rates — Single 25 MHz reference clock — 144-pin LQFP package — Low power 3.3V CMOS design with typical consumption

of 383 mW operating, 297 mW during WOL and 53 mW

during sleep mode — IEEE 802.3u MII for connecting alternative external

Physical Layer Devices — 3.3V signalling with 5V tolerant I/O.

System Diagram

PCI Bus

10/100 Twisted Pair

DP83816

BIOS ROM

(optional)

MacPHYTER-II is a trademark of National Semiconductor Corporation. Magic Packet is a trademark of Advanced Micro Devices, Inc.

EEPROM (optional)

Isolation

Table of Contents

1.0 Connection Diagram . . . . . . . . . . . . . . . . . . 4

1.1 144 LQFP Package (VNG) . . . . . . . . . . . . 4

2.0 Pin Description . . . . . . . . . . . . . . . . . . . . . . 5

3.0 Functional Description . . . . . . . . . . . . . . . 11

3.1 MAC/BIU . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1.1 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1.2 Tx MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1.3 Rx MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Buffer Management . . . . . . . . . . . . . . . . . 13

3.2.1 Tx Buffer Manager . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2.2 Rx Buffer Manager . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2.3 Packet Recognition . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2.4 MIB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3 Interface Definitions . . . . . . . . . . . . . . . . . 14

3.3.1 PCI System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3.2 Boot PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3.3 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3.4 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.4 Physical Layer . . . . . . . . . . . . . . . . . . . . . 16

3.4.1 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.4.2 Auto-Negotiation Register Control . . . . . . . . . . . . . 16

3.4.3 Auto-Negotiation Parallel Detection . . . . . . . . . . . . 16

3.4.4 Auto-Negotiation Restart . . . . . . . . . . . . . . . . . . . . 17

3.4.5 Enabling Auto-Negotiation via Software . . . . . . . . 17

3.4.6 Auto-Negotiation Complete Time . . . . . . . . . . . . . . 17

3.5 LED Interfaces . . . . . . . . . . . . . . . . . . . . . 17

3.6 Half Duplex vs. Full Duplex . . . . . . . . . . . 18

3.7 Phy Loopback . . . . . . . . . . . . . . . . . . . . . 18

3.8 Status Information . . . . . . . . . . . . . . . . . . 18

3.9 100BASE-TX TRANSMITTER . . . . . . . . . 18

3.9.1 Code-group Encoding and Injection . . . . . . . . . . . 19

3.9.2 Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.9.3 NRZ to NRZI Encoder . . . . . . . . . . . . . . . . . . . . . . 20

3.9.4 Binary to MLT-3 Convertor / Common Driver . . . . 20

3.10 100BASE-TX Receiver . . . . . . . . . . . . . . 21

3.10.1 Input and Base Line Wander Compensation . . . . 21

3.10.2 Signal Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.10.3 Digital Adaptive Equalization . . . . . . . . . . . . . . . . 23

3.10.4 Line Quality Monitor . . . . . . . . . . . . . . . . . . . . . . . 24

3.10.5 MLT-3 to NRZI Decoder . . . . . . . . . . . . . . . . . . . . 24

3.10.6 Clock Recovery Module . . . . . . . . . . . . . . . . . . . . 25

3.10.7 NRZI to NRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.10.8 Serial to Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.10.9 De-scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.10.10 Code-group Alignment . . . . . . . . . . . . . . . . . . . . 25

3.10.11 4B/5B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.10.12 100BASE-TX Link Integrity Monitor . . . . . . . . . . 25

3.10.13 Bad SSD Detection . . . . . . . . . . . . . . . . . . . . . . 25

3.11 10BASE-T Transceiver Module . . . . . . . . 26

3.11.1 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . 26

3.11.2 Smart Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.11.3 Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . 26

3.11.4 Normal Link Pulse Detection/Generation . . . . . . .26

3.11.5 Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.11.6 Automatic Link Polarity Detection . . . . . . . . . . . . . 27

3.11.7 10BASE-T Internal Loopback . . . . . . . . . . . . . . . . 27

3.11.8 Transmit and Receive Filtering . . . . . . . . . . . . . . . 27

3.11.9 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.11.10 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.11.11 Far End Fault Indication . . . . . . . . . . . . . . . . . . . 27

3.12 802.3u MII . . . . . . . . . . . . . . . . . . . . . . . . 27

3.12.1 MII Access Configuration . . . . . . . . . . . . . . . . . . . 27

3.12.2 MII Serial Management . . . . . . . . . . . . . . . . . . . . 27

DP83816

3.12.3 MII Serial Management Access . . . . . . . . . . . . . 28

3.12.4 Serial Management Access Protocol . . . . . . . . . 28

3.12.5 Nibble-wide MII Data Interface . . . . . . . . . . . . . . 28

3.12.6 Collision Detection . . . . . . . . . . . . . . . . . . . . . . . 29

3.12.7 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.0 Register Set . . . . . . . . . . . . . . . . . . . . . . . . 30

4.1 Configuration Registers . . . . . . . . . . . . . . 30

4.1.1 Configuration Identification Register . . . . . . . . . . . 30

4.1.2 Configuration Command and Status Register . . . 31

4.1.3 Configuration Revision ID Register . . . . . . . . . . . 32

4.1.4 Configuration Latency Timer Register . . . . . . . . . 33

4.1.5 Configuration I/O Base Address Register . . . . . . . 33

4.1.6 Configuration Memory Address Register . . . . . . . 34

4.1.7 Configuration Subsystem Identification Register . 34

4.1.8 Boot ROM Configuration Register . . . . . . . . . . . . 35

4.1.9 Capabilities Pointer Register . . . . . . . . . . . . . . . . 35

4.1.10 Configuration Interrupt Select Register . . . . . . . . 36

4.1.11 Power Management Capabilities Register . . . . . 36

4.1.12 Power Management Control and Status Register 37

4.2 Operational Registers . . . . . . . . . . . . . . . 38

4.2.1 Command Register . . . . . . . . . . . . . . . . . . . . . . . . 39

4.2.2 Configuration and Media Status Register . . . . . . . 40

4.2.3 EEPROM Access Register . . . . . . . . . . . . . . . . . . 42

4.2.4 EEPROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.2.5 PCI Test Control Register . . . . . . . . . . . . . . . . . . . 43

4.2.6 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . 44

4.2.7 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . 45

4.2.8 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . 47

4.2.9 Interrupt Holdoff Register . . . . . . . . . . . . . . . . . . . 47

4.2.10 Transmit Descriptor Pointer Register . . . . . . . . . 48

4.2.11 Transmit Configuration Register . . . . . . . . . . . . . 48

4.2.12 Receive Descriptor Pointer Register . . . . . . . . . . 50

4.2.13 Receive Configuration Register . . . . . . . . . . . . . 51

4.2.14 CLKRUN Control/Status Register . . . . . . . . . . . . 52

4.2.15 Wake Command/Status Register . . . . . . . . . . . . 54

4.2.16 Pause Control/Status Register . . . . . . . . . . . . . . 56

4.2.17 Receive Filter/Match Control Register . . . . . . . . 57

4.2.18 Receive Filter/Match Data Register . . . . . . . . . . 58

4.2.19 Receive Filter Logic . . . . . . . . . . . . . . . . . . . . . . 59

4.2.20 Boot ROM Address Register . . . . . . . . . . . . . . . . 63

4.2.21 Boot ROM Data Register . . . . . . . . . . . . . . . . . . 63

4.2.22 Silicon Revision Register . . . . . . . . . . . . . . . . . . 63

4.2.23 Management Information Base Control Register 64

4.2.24 Management Information Base Registers . . . . . . 65

4.3 Internal PHY Registers . . . . . . . . . . . . . . . 66

4.3.1 Basic Mode Control Register . . . . . . . . . . . . . . . . 66

4.3.2 Basic Mode Status Register . . . . . . . . . . . . . . . . . 67

4.3.3 PHY Identifier Register #1 . . . . . . . . . . . . . . . . . . 68

4.3.4 PHY Identifier Register #2 . . . . . . . . . . . . . . . . . . 68

4.3.5 Auto-Negotiation Advertisement Register . . . . . . 68

4.3.6 Auto-Negotiation Link Partner Ability Register . . . 69

4.3.7 Auto-Negotiate Expansion Register . . . . . . . . . . . 70

4.3.8 Auto-Negotiation Next Page Transmit Register . . 70

4.3.9 PHY Status Register . . . . . . . . . . . . . . . . . . . . . . . 71

4.3.10 MII Interrupt Control Register . . . . . . . . . . . . . . . 73

4.3.11 MII Interrupt Status and Misc. Control Register . 73

4.3.12 False Carrier Sense Counter Register . . . . . . . . 74

4.3.13 Receiver Error Counter Register . . . . . . . . . . . . . 74

4.3.14 100 Mb/s PCS Configuration and Status Register 74

4.3.15 PHY Control Register . . . . . . . . . . . . . . . . . . . . . 75

4.3.16 10BASE-T Status/Control Register . . . . . . . . . . . 76

5.0 Buffer Management . . . . . . . . . . . . . . . . . . 77

5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.1.1 Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.1.2 Single Descriptor Packets . . . . . . . . . . . . . . . . . . 79

2 www.national.com

5.1.3 Multiple Descriptor Packets . . . . . . . . . . . . . . . . . . 80

5.1.4 Descriptor Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.2 Transmit Architecture . . . . . . . . . . . . . . . 81

5.2.1 Transmit State Machine . . . . . . . . . . . . . . . . . . . . . 81

5.2.2 Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . 83

5.3 Receive Architecture . . . . . . . . . . . . . . . . 84

5.3.1 Receive State Machine . . . . . . . . . . . . . . . . . . . . . 84

5.3.2 Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.0 Power Management and Wake-On-LAN. . 87

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 87

6.2 Definitions (for this document only) . . . . . 87

6.3 Packet Filtering . . . . . . . . . . . . . . . . . . . . 87

6.4 Power Management . . . . . . . . . . . . . . . . 87

6.4.1 D0 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.4.2 D1 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.4.3 D2 State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.4.4 D3hot State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.4.5 D3cold State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

6.5 Wake-On-LAN (WOL) Mode . . . . . . . . . . 88

6.5.1 Entering WOL Mode . . . . . . . . . . . . . . . . . . . . . . . 88

6.5.2 Wake Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.5.3 Exiting WOL Mode . . . . . . . . . . . . . . . . . . . . . . . . . 89

6.6 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . 89

6.6.1 Entering Sleep Mode . . . . . . . . . . . . . . . . . . . . . . 89

6.6.2 Exiting Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . 89

6.7 Pin Configuration for Power Management 89

7.0 DC and AC Specifications . . . . . . . . . . . . . 90

7.1 DC Specifications . . . . . . . . . . . . . . . . . . . 90

7.2 AC Specifications . . . . . . . . . . . . . . . . . . . 91

7.2.1 PCI Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . 91

7.2.2 X1 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 91

7.2.3 Power On Reset (PCI Active) . . . . . . . . . . . . . . . . 92

7.2.4 Non Power On Reset . . . . . . . . . . . . . . . . . . . . . . 92

7.2.5 POR PCI Inactive . . . . . . . . . . . . . . . . . . . . . . . . . 93

7.2.6 PCI Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

7.2.7 EEPROM Auto-Load . . . . . . . . . . . . . . . . . . . . . . 99

7.2.8 Boot PROM/FLASH . . . . . . . . . . . . . . . . . . . . . . 100

7.2.9 100BASE-TX Transmit . . . . . . . . . . . . . . . . . . . 101

7.2.10 10BASE-T Transmit End of Packet . . . . . . . . . 102

7.2.11 10 Mb/s Jabber Timing . . . . . . . . . . . . . . . . . . 102

7.2.12 10BASE-T Normal Link Pulse . . . . . . . . . . . . . 103

7.2.13 Auto-Negotiation Fast Link Pulse (FLP) . . . . . . 103

7.2.14 Media Independent Interface (MII) . . . . . . . . . . 104

List of Figures

Figure 3-1 DP83816 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 3-2 MAC/BIU Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 3-3 Ethernet Packet Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 3-4 DSP Physical Layer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 3-5 LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 3-6 100BASE-TX Transmit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 3-7 Binary to MLT-3 conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 3-8 100 M/bs Receive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 3-9 100BASE-TX BLW Event Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 3-10 EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT V cable . . . . . . . . 24

Figure 3-11 MLT-3 Signal Measured at AII after 0 meters of CAT V cable. . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 3-12 MLT-3 Signal Measured at AII after 50 meters of CAT V cable. . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 3-13 MLT-3 Signal Measured at AII after 100 meters of CAT V cable. . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 3-14 10BASE-T Twisted Pair Smart Squelch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 3-15 Typical MDC/MDIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 3-16 Typical MDC/MDIO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 4-1 Pattern Buffer Memory - 180h words (word = 18bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Figure 4-2 Hash Table Memory - 40h bytes addressed on word boundaries . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 5-1 Single Descriptor Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Figure 5-2 Multiple Descriptor Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Figure 5-3 List and Ring Descriptor Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Figure 5-4 Transmit Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Figure 5-5 Transmit State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Figure 5-6 Receive Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Figure 5-7 Receive State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

List of Tables

Table 3-1 4B5B Code-Group Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 3-2 Typical MDIO Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 4-1 Configuration Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 4-2 Operational Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 4-3 MIB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 5-1 DP83816 Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 5-2 cmdsts Common Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 5-3 Transmit Status Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 5-4 Receive Status Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 5-5 Transmit State Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Table 5-6 Receive State Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Table 6-1 Power Management Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Table 6-2 PM Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

DP83816

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1.0 Connection Diagram

1.1 144 LQFP Package (VNG)

VSS

AUXVDD

VSS

TXEN

TXCLK

CRS

DP83816

MA3/EEDI

MA4/EECLK

VSS

TXD3/MA15

COL/MA16

AUXVDD

TXD2/MA14

TXD1/MA13

VSS

TXD0/MA12

VSS

AUXVDD

RXDV/MA11

RXER/MA10

RXOE

RXD2/MA8

RXD3/MA9

RXD0/MA6

RXD1/MA7

VSS

AUXVDD

MDIO

MDC

RXCLK

MA5

VSS

IAUXVDD

VREF

RESERVED

NC NC

VSS

TPRDM

TPRDP

IAUXVDD

REGEN

VSS

RESERVED

VSS VSS

TPTDM

TPTDP

VSS

AUXVDD

VSS

AUXVDD

PMEN/CLKRUNN

PCICLK

INTAN

RSTN GNTN REQN

VSS AD31 AD30 AD29

PCIVDD

AD28 AD27 AD26

105

106

107

123456789

108

144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109

MA2/LED100N MA1/LED10N MA0/LEDACTN MD7 MD6 MD5 MD4/EEDO AUXVDD VSS MD3 MD2 MD1/CFGDISN MD0 MWRN MRDN MCSN EESEL RESERVED NC NC NC PWRGOOD 3VAUX AD0 AD1 AD2 AD3 PCIVDD AD4 AD5 VSS AD6 AD7 CBEN0 AD8 AD9

363534

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

323329

Pin1

Identification

DP83816

100

101

102

103

104

AD24

AD25

VSS

IDSEL

CBEN3

AD22

AD23

PCIVDD

AD20

AD21

AD19

AD18

AD16

AD17

VSS

CBEN2

FRAMEN

VSS

PAR

AD15

AD14

AD13

AD12

AD11

IRDYN

TRDYN

STOPN

PCIVDD

DEVSELN

PERRN

SERRN

CBEN1

AD10

PCIVDD

For Normal Operating Temperature - Order Number DP83816AVNG

See NS Package Number VNG144A

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2.0 Pin Description

PCI Bus Interface

DP83816

Symbol

AD[31-0] 66, 67, 68, 70,

CBEN[3-0] 75,

PCICLK 60 I Clock: This PCI Bus clock provides timing for all bus phases. The rising edge

DEVSELN 95 I/O Device Select: As a bus master, the DP83816 samples this signal to insure that the

FRAMEN 91 I/O Frame: As a bus master, this signal is asserted low to indicate the beginning and

LQFP Pin

No(s) Dir Description

I/O Address and Data: Multiplexed address and data bus. As a bus master, the 71, 72, 73, 74, 78, 79, 81, 82, 83, 86, 87, 88, 101, 102, 104, 105, 106, 108, 109, 110, 112,

113, 115, 116,

118, 119, 120,

121

89,

100,

111

DP83816 will drive address during the first bus phase. During subsequent phases, the DP83816 will either read or write data expecting the target to increment its address pointer. As a bus target, the DP83816 will decode each address on the bus and respond if it is the target being addressed.

I/O Bus Command/Byte Enable: During the address phase these signals define the

“bus command” or the type of bus transaction that will take place. During the data phase these pins indicate which byte lanes contain valid data. CBEN[0] applies to byte 0 (bits 7-0) and CBEN[3] applies to byte 3 (bits 31-24) in the Little Endian Mode. In Big Endian Mode, CBEN[3] applies to byte 0 (bits 31-24) and CBEN[0] applies to byte 3 (bits 7-0).

defines the start of each phase. The clock frequency ranges from 0 to 33 MHz.

destination address for the data transfer is recognized by a PCI target. As a target, the DP83816 asserts this signal low when it recognizes its address after FRAMEN is asserted.

duration of a bus transaction. Data transfer takes place when this signal is asserted. It is de-asserted before the transaction is in its final phase. As a target, the device monitors this signal before decoding the address to check if the current transaction is addressed to it.

GNTN 63 I Grant: This signal is asserted low to indicate to the DP83816 that it has been

IDSEL 76 I Initialization Device Select: This pin is sampled by the DP83816 to identify when

INTAN 61 O Interrupt A: This signal is asserted low when an interrupt condition occurs as

IRDYN 92 I/O Initiator Ready: As a bus master, this signal will be asserted low when the

PAR 99 I/O Parity: This signal indicates even parity across AD[31-0] and CBEN[3-0] including

PERRN 97 I/O Parity Error: The DP83816 as a master or target will assert this signal low to

REQN 64 O Request: The DP83816 will assert this signal low to request ownership of the bus

RSTN 62 I Reset: When this signal is asserted all PCI bus outputs of DP83816 will be in TRI-

granted ownership of the bus by the central arbiter. This input is used when the DP83816 is acting as a bus master.

configuration read and write accesses are intended for it.

defined in the Interrupt Status Register, Interrupt Mask, and Interrupt Enable registers.

DP83816 is ready to complete the current data phase transaction. This signal is used in conjunction with the TRYDN signal. Data transaction takes place at the rising edge of PCICLK when both IRDYN and TRDYN are asserted low. As a target, this signal indicates that the master has put the data on the bus.

the PAR pin. As a master, PAR is asserted during address and write data phases. As a target, PAR is asserted during read data phases.

indicate a parity error on any incoming data (except for special cycles). As a bus master, it will monitor this signal on all write operations (except for special cycles).

from the central arbiter.

STATE

and the device will be put into a known state.

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2.0 Pin Description (Continued)

PCI Bus Interface

DP83816

Symbol

SERRN 98 I/O System Error: This signal is asserted low by DP83816 during address parity errors

STOPN 96 I/O Stop: This signal is asserted low by the target device to request the master device

TRDYN 93 I/O Target Ready: As a master, this signal indicates that the target is ready for the data

PMEN/

CLKRUNN

3VAUX 122 I PCI Auxiliary Voltage Sense: This pin is used to sense the presence of a 3.3V

LQFP Pin

No(s) Dir Description

and system errors if enabled.

to stop the current transaction.

during write operation and with the data during read operation. As a target, this signal will be asserted low when the (target) device is ready to complete the current data phase transaction. This signal is used in conjunction with the IRDYN signal. Data transaction takes place at the rising edge of PCICLK when both IRDYN and TRDYN are asserted low.

59 I/O Power Management Event/Clock Run Function: This pin is a dual function pin.

The function of this pin is determined by the CLKRUN_EN bit 0 of the CLKRUN Control and Status register (CCSR). Default operation of this pin is PMEN.

Power Management Event: This signal is asserted low by the DP83816 to indicate that a power management event has occurred. For pin connection please refer to Section 6.7.

Clock Run Function: In this mode, this pin is used to indicate when the PCICLK will be stopped.

auxiliary supply in order to define the PME Support available. For pin connection please refer to Section 6.7.

This pin has an internal weak pull down.

PWRGOOD 123 I PCI bus power good: Connected to PCI bus 3.3V power, this pin is used to sense

the presence of PCI bus power during the D3 power management state.

This pin has an internal weak pull down.

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2.0 Pin Description (Continued)

Media Independent Interface (MII)

DP83816

Symbol

COL 28 I Collision Detect: The COL signal is asserted high asynchronously by the external

CRS 29 I Carrier Sense: This signal is asserted high asynchronously by the external PMD

MDC 5 O Management Data Clock: Clock signal with a maximum rate of 2.5 MHz used to

MDIO 4 I/O Management Data I/O: Bidirectional signal used to transfer management

RXCLK 6 I Receive Clock: A continuous clock, sourced by an external PMD device, that is

RXD3/MA9, RXD2/MA8, RXD1/MA7, RXD0/MA6

RXDV/MA11 15 IOReceive Data Valid: Indicates that the external PMD is presenting recovered and

LQFP Pin

No(s) Dir Description

PMD upon detection of a collision on the medium. It will remain asserted as long as the collision condition persists.

upon detection of a non-idle medium.

transfer management data for the external PMD on the MDIO pin.

information for the external PMD. (See Section 3.12.4 for details on connections when MII is used.)

recovered from the incoming data. During 100 Mb/s operation RXCLK is 25 MHz and during 10 Mb/s this is 2.5 MHz.

12, 11, 10,

IOReceive Data: Sourced from an external PMD, that contains data aligned on nibble

boundaries and are driven synchronous to RXCLK. RXD[3] is the most significant bit and RXD[0] is the least significant bit.

BIOS ROM Address: During external BIOS ROM access, these signals become part of the ROM address.

decoded nibbles on the RXD signals, and that RXCLK is synchronous to the recovered data in 100 Mb/s operation. This signal will encompass the frame, starting with the Start-of-Frame delimiter (JK) and excluding any End-of-Frame delimiter (TR).

BIOS ROM Address: During external BIOS ROM access, this signal becomes part of the ROM address.

RXER/MA10 14 IOReceive Error: Asserted high synchronously by the external PMD whenever it

detects a media error and RXDV is asserted in 100 Mb/s operation.

BIOS ROM Address: During external BIOS ROM access, this signal becomes part of the ROM address.

RXOE 13 O Receive Output Enable: Used to disable an external PMD while the BIOS ROM is

being accessed.

TXCLK 31 I Transmit Clock: A continuous clock that is sourced by the external PMD. During

100 Mb/s operation this is 25 MHz +/- 100 ppm. During 10 Mb/s operation this clock is 2.5 MHz +/- 100 ppm.

TXD3/MA15, TXD2/MA14, TXD1/MA13, TXD0/MA12

TXEN 30 O Transmit Enable: This signal is synchronous to TXCLK and provides precise

Note: MII is normally in TRI-STATE, unless enabled by CFG:EXT_PHY. See Section 4.2.2.

25, 24, 23,

OOTransmit Data: Signals which are driven synchronous to the TXCLK for

transmission to the external PMD. TXD[3] is the most significant bit and TXD[0] is the least significant bit.

BIOS ROM Address: During external BIOS ROM access, these signals become part of the ROM address.

framing for data carried on TXD[3-0] for the external PMD. It is asserted when TXD[3-0] contains valid data to be transmitted.

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2.0 Pin Description (Continued)

100BASE-TX/10BASE-T Interface

DP83816

Symbol

TPTDP, TPTDM 54, 53 A-O Transmit Data: Differential common output driver. This differential common output

TPRDP, TPRDM 46, 45 A-I Receive Data: Differential common input buffer. This differential common input can

LQFP Pin

No(s) Dir Description

is configurable to either 10BASE-T or 100BASE-TX signaling:

10BASE-T: Transmission of Manchester encoded 10BASE-T packet data as well as Link Pulses (including Fast Link Pulses for Auto-Negotiation purposes).

100BASE-TX: Transmission of ANSI X3T12 compliant MLT-3 data.

The DP83816 will automatically configure this common output driver for the proper signal type as a result of either forced configuration or Auto-Negotiation.

be configured to accept either 100BASE-TX or 10BASE-T signaling:

10BASE-T: Reception of Manchester encoded 10BASE-T packet data as well as normal Link Pulses and Fast Link Pulses for Auto-Negotiation purposes.

100BASE-TX: Reception of ANSI X3T12 compliant scrambled MLT-3 data.

The DP83816 will automatically configure this common input buffer to accept the proper signal type as a result of either forced configuration or Auto-Negotiation.

BIOS ROM/Flash Interface

Symbol

MCSN 129 O BIOS ROM/Flash Chip Select: During a BIOS ROM/Flash access, this signal is

LQFP Pin

No(s) Dir Description

used to select the ROM device.

MD7, MD6, MD5, MD4/EEDO, MD3, MD2, MD1/CFGDISN, MD0

MA5, MA4/EECLK, MA3/EEDI, MA2/LED100LNK, MA1/LED10LNK, MA0/LEDACT

MWRN 131 O BIOS ROM/Flash Write: During a BIOS ROM/Flash access, this signal is used to

MRDN 130 O BIOS ROM/Flash Read: During a BIOS ROM/Flash access, this signal is used to

Note: DP83816 supports NM27LV010 for the BIOS ROM interface device.

141, 140, 139,

138, 135,

134, 133,

132

3, 2,

1, 144, 143,

142

I/O BIOS ROM/Flash Data Bus: During a BIOS ROM/Flash access these signals are

used to transfer data to or from the ROM/Flash device.

MD[5:0] pins have internal weak pull ups.

MD6 and MD7 pins have internal weak pull downs.

O BIOS ROM/Flash Address: During a BIOS ROM/Flash access, these signals are

used to drive the ROM/Flash address.

enable data to be written to the Flash device.

enable data to be read from the Flash device.

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2.0 Pin Description (Continued)

Clock Interface

DP83816

Symbol

X1 17 I Crystal/Oscillator Input: This pin is the primary clock reference input for the

X2 18 O Crystal Output: This pin is used in conjunction with the X1 pin to connect to an

LQFP Pin

No(s) Dir Description

DP83816 and must be connected to a 25 MHz 0.005% (50ppm) clock source. The DP83816 device supports either an external crystal resonator connected across pins X1 and X2, or an external CMOS-level oscillator source connected to pin X1 only.

external 25 MHz crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock source is utilized. For more information see the definition for pin X1.

LED Interface

Symbol

LEDACTN/MA0 142 O TX/RX Activity: This pin is an output indicating transmit/receive activity. This pin is

LED100N/MA2 144 O 100 Mb/s Link: This pin is an output indicating the 100 Mb/s Link status. This pin is

LQFP Pin

No(s) Dir Description

driven low to indicate active transmission or reception, and can be used to drive a low current LED (<6 mA). The activity event is stretched to a minimum duration of approximately 50 ms.

driven low to indicate Good Link status for 100 Mb/s operation, and can be used to drive a low current LED (<6 mA).

LED10N/MA1 143 O 10 Mb/s Link: This pin is an output indicating the 10 Mb/s Link status. This pin is

driven low to indicate Good Link status for 10 Mb/s operation, and can be used to drive a low current LED (<6 mA).

Serial EEPROM Interface

Symbol

EESEL 128 O EEPROM Chip Select: This signal is used to enable an external EEPROM device.

EECLK/MA4 2 O EEPROM Clock: During an EEPROM access (EESEL asserted), this pin is an

EEDI/MA3 1 O EEPROM Data In: During an EEPROM access (EESEL asserted), this pin is an

EEDO/MD4 138 I EEPROM Data Out: During an EEPROM access (EESEL asserted), this pin is an

MD1/CFGDISN 133 I/O Configuration Disable: When pulled low at power-on time, disables load of

Note: DP83816 supports NMC93C46 for the EEPROM device.

LQFP Pin

No(s) Dir Description

output used to drive the serial clock to an external EEPROM device.

output used to drive opcode, address, and data to an external serial EEPROM device.

input used to retrieve EEPROM serial read data.

This pin has an internal weak pull up.

configuration data from the EEPROM. Use 1 KΩ to ground to disable configuration load.

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2.0 Pin Description (Continued)

External Reference Interface

DP83816

Symbol

VREF 40 I Bandgap Reference: External current reference resistor for internal Phy bandgap

LQFP Pin

No(s) Dir Description

circuitry. The value of this resistor is 10KΩ 1% metal film (100 ppm/ be connected from the VREF pin to analog ground.

C) which must

No Connects and Reserved

Symbol

NC 34, 42, 43, 36,

RESERVED 41, 50, 127 These pins are reserved and cannot be connected to any external logic or net.

REGEN 48 Reserved and cannot be connected to any external logic or net..

LQFP Pin

No(s) Dir Description

No Connect

37, 84, 85,

124, 125, 126

This pin has an internal weak pull down.

Supply Pins

Symbol

LQFP Pin

No(s) Dir Description

C1 19 S Connect to GND through 10uF and 0.1uF external capacitors in parallel.

IAUXVDD 39, 47 S Connect to isolated Aux 3.3V supply VDD

AUXVDD 9, 21, 27, 33,

56, 58, 137

PCIVDD 69, 80, 94,

107, 117

VSS 8, 16, 20, 26,

32, 35, 38, 44, 49, 51, 52, 55, 57, 65, 77, 90,

103, 114, 136

S Connect to Aux 3.3V supply VDD

S PCI VDD - connect to PCI bus 3.3V VDD

S VSS

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3.0 Functional Description

DP83816

DP83816 consists of a MAC/BIU (Media Access Controller/Bus Interface Unit), a physical layer interface, SRAM, and miscellaneous support logic. The MAC/BIU includes the PCI bus, BIOS ROM and EEPROM interfaces,

TPRDP/M

25 MHz Clk

3V DSP Physical Layer

SRAM

RX-2 KB

RAM

SRAM

RXFilter

.5 KB

SRAM

TX-2 KB

BIST

Logic

and an 802.3 MAC. The physical layer interface used is a single-port version of the 3.3V DsPhyterII. Internal memory consists of one - 0.5 KB and two - 2 KB SRAM blocks.

TPTDP/M

MII TX

MII RX

MII Mgt

Test data in

Test data out

MII RX MII TX

Interface

Logic

MII Mgt

BIOS ROM Cntl BIOS ROM Data EEPROM/LEDs

PCI CLK

PCI CNTL

PCI AD

Rx rd data

Tx rd data

Tx Addr

Tx wr data

Rx Addr

Rx wr data

MII Mgt

BROM/EE

MII TX

MII RX

MAC/BIU

DP83816

Figure 3-1 DP83816 Functional Block Diagram

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3.0 Functional Description (Continued)

DP83816

PCI Bus

Interface

PCI Bus

Data FIFO

Tx Buffer Manager

Data FIFO

Rx Buffer Manager

MIB

Rx Filter

Pkt Recog

Logic

SRAM

Tx MAC

Rx MAC

Physical Layer Interface

93C46

Serial

EEPROM

Figure 3-2 MAC/BIU Functional Block Diagram

Boot ROM/

Flash

3.1 MAC/BIU

The MAC/BIU is a derivative design from the DP83810 (Euphrates). The original MAC/BIU design has been optimized to improve logic efficiency and enhanced to add features consistent with current market needs and specification compliance. The MAC/BIU design blocks are discussed in this section.

3.1.1 PCI Bus Interface

This block implements PCI v2.2 bus protocols, and configuration space. Supports bus master reads and writes to CPU memory, and CPU access to on-chip register space. Additional functions provided include: configuration

MAC/BIU

control, serial EEPROM access with auto configuration load, interrupt control, power management control with support for PME or CLKRUN function.

3.1.1.1 Byte Ordering

The DP83816 can be configured to order the bytes of data on the AD[31:0] bus to conform to little endian or big endian ordering through the use of the Configuration Register, bit 0 (CFG:BEM). By default, the device is in little endian ordering. Byte ordering only affects data FIFOs. Register information remains bit aligned (i.e. AD[31] maps to bit 31 in any register space, AD[0] maps to bit 0, etc.).

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3.0 Functional Description (Continued)

Little Endian (CFG:BEM=0): The byte orientation for

receive and transmit data in system memory is as follows:

232431

Byte 0Byte 1Byte 2Byte 3

MSB

Big Endian (CFG:BEM=1): The byte orientation for receive and transmit data in system memory is as follows:

232431

LSB

3.1.1.2 PCI Bus Interrupt Control

PCI bus interrupts for the DP83816 are asynchronously performed by asserting pin INTAN. This pin is an open drain output. The source of the interrupt can be determined by reading the Interrupt Status Register (ISR). One or more bits in the ISR will be set, denoting all currently pending interrupts. Caution: Reading of the ISR clears ALL bits. Masking of specified interrupts can be accomplished by using the Interrupt Mask Register (IMR).

3.1.1.3 Timer

The Latency Timer described in CFGLAT:LAT defines the minimum number of bus clocks that the device will hold the bus. Once the device gains control of the bus and issues FRAMEN, the Latency Timer will begin counting down. If GNTN is de-asserted before the DP83816 has finished with the bus, the device will maintain ownership of the bus until the timer reaches zero (or has finished the bus transfer). The timer is an 8-bit counter.

3.1.2 Tx MAC

This block implements the transmit portion of 802.3 Media Access Control. The Tx MAC retrieves packet data from the Tx Buffer Manager and sends it out through the transmit portion. Additionally, the Tx MAC provides MIB control information for transmit packets.

3.1.3 Rx MAC

This block implements the receive portion of 802.3 Media Access Control. The Rx MAC retrieves packet data from the receive portion and sends it to the Rx Buffer Manager. Additionally, the Rx MAC provides MIB control information and packet address data for the Rx Filter.

LSB

C/BE[0]C/BE[1]C/BE[2]C/BE[3]

Byte 3Byte 2Byte 1Byte 0

C/BE[0]C/BE[1]C/BE[2]C/BE[3]

3.2 Buffer Management

The buffer management scheme used on the DP83816 allows quick, simple and efficient use of the frame buffer memory. Frames are saved in similar formats for both

0781516

MSB

DP83816

transmit and receive. The buffer management scheme also uses separate buffers and descriptors for packet information. This allows effective transfers of data from the receive buffer to the transmit buffer by simply transferring the descriptor from the receive queue to the transmit queue.

The format of the descriptors allows the packets to be saved in a number of configurations. A packet can be stored in memory with a single descriptor per single packet, or multiple descriptors per single packet. This flexibility allows the user to configure the DP83816 to maximize efficiency. Architecture of the specific system’s buffer memory, as well as the nature of network traffic, will determine the most suitable configuration of packet descriptors and fragments. Refer to the Buffer Management Section (Section 5.0) for more information.

3.2.1 Tx Buffer Manager

This block DMAs packet data from PCI memory space and places it in the 2 KB transmit FIFO, and pulls data from the FIFO to send to the Tx MAC. Multiple packets (4) may be present in the FIFO, allowing packets to be transmitted with minimum interframe gap. The way in which the FIFO is emptied and filled is controlled by the FIFO threshold values in the TXCFG register: FLTH (Tx Fill Threshold) and DRTH (Tx Drain Threshold). These values determine how full or empty the FIFO must be before the device requests the bus. Additionally, once the DP83816 requests the bus, it will attempt to empty or fill the FIFO as allowed by the MXDMA setting in the TXCFG register.

3.2.2 Rx Buffer Manager

This block retrieves packet data from the Rx MAC and places it in the 2 KB receive data FIFO, and pulls data from the FIFO for DMA to PCI memory space. The Rx Buffer Manager maintains a status FIFO, allowing up to 4 packets to reside in the FIFO at once. Similar to the transmit FIFO, the receive FIFO is controlled by the FIFO threshold value in the RXCFG register: DRTH (Rx Drain Threshold). This value determines the number of long words written into the FIFO from the MAC unit before a DMA request for system memory access occurs. Once the DP83816 gets the bus, it will continue to transfer the long words from the FIFO until the data in the FIFO is less than one long word, or has reached the end of the packet, or the max DMA burst size is reached (RXCFG:MXDMA).

3.2.3 Packet Recognition

The Receive packet filter and recognition logic allows software to control which packets are accepted based on destination address and packet type. Address recognition logic includes support for broadcast, multicast hash, and unicast addresses. The packet recognition logic includes support for WOL, Pause, and programmable pattern recognition.

The standard 802.3 Ethernet packet consists of the following fields: Preamble (PA), Start of Frame Delimiter (SFD), Destination Address (DA), Source Address (SA), Length (LEN), Data and Frame Check Sequence (FCS). All fields are fixed length except for the data field. During reception, the PA, SFD and FCS are stripped. During transmission, the DP83816 generates and appends the PA, SFD and FCS.

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3.0 Functional Description (Continued)

FCSDataLENSADAPA6BSFD

60b 4b 6B 2B 46B-1500B

Note: B = Bytes

b = bits

Figure 3-3 Ethernet Packet Format

3.2.4 MIB

The MIB block contains counters to track certain media events required by the management specifications RFC 1213 (MIB II), RFC 1398 (Ether-like MIB), and IEEE 802.3 LME. The counters provided are for events which are either difficult or impossible to be intercepted directly by software. Not all counters are implemented, however required counters can be calculated from the counters provided.

3.3 Interface Definitions

3.3.1 PCI System Bus

This interface allows direct connection of the DP83816 to a 33 MHz PCI system bus. The DP83816 supports zero wait state data transfers with burst sizes up to 128 dwords. The

DP83816

DP83816 conforms to 3.3V AC/DC specifications, but has 5V tolerant inputs.

3.3.2 Boot PROM

The BIOS ROM interface allows the DP83816 to read from and write data to an external ROM/Flash device.

3.3.3 EEPROM

The DP83816 supports the attachment of an external EEPROM. The EEPROM interface provides the ability for the DP83816 to read from and write data to an external serial EEPROM device. The DP83816 will auto-load values from the EEPROM to certain fields in PCI configuration space and operational space and perform a checksum to verify that the data is valid. Values in the external EEPROM allow default fields in PCI configuration space and I/O space to be overridden following a hardware reset. If the EEPROM is not present, the DP83816 initialization uses default values for the appropriate Configuration and Operational Registers. Software can read and write to the EEPROM using “bit-bang” accesses via the EEPROM Access Register (MEAR).

3.3.4 Clock

The clock interface provides the 25 MHz clock reference input for the DP83816 IC. The X1 input signal amplitude should be approximately 1V. This interface supports operation from a 25 MHz, 50 ppm CMOS oscillator, or a 25 MHz, 50 ppm, parallel, 20 pF load, < 40 Ω ESR crystal resonator. A 20pF crystal resonator would require C1 and

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3.0 Functional Description (Continued)

POWER ON

CONFIGURATION

PINS

MANAGEMENT

DP83816

MAC INTERFACE

SERIAL

TX_DATA

TRANSMIT CHANNELS &

STATE MACHINES

100 MB/S 10 MB/S

4B/5B

ENCODER

SCRAMBLER

PARALLEL TO

SERIAL

NRZ TO NRZI

ENCODER

BINARY TO

MLT-3

ENCODER

10/100 COMMON

OUTPUT DRIVER

TXCLK

TXD(3:0)

TX_DATA

NRZ TO

MANCHESTER

ENCODER

LINK PULSE

GENERATOR

TRANSMIT

FILTER

TXER

TXCLK

TXEN

MDIO

MDC

REGISTERS

MII

PHY ADDRESS

AUTO

NEGOTIATION

BASIC MODE

CONTROL

PCS CONTROL

10BASE-T

100BASE-X

FAR-END-FAULT

STATE MACHINE

AUTO-NEGOTIATION

STATE MACHINE

COL

CRS

RXEN

RXER

RXDV

RXD(3:0)

RX_DATARXCLK

RECEIVE CHANNELS &

STATE MACHINES

100 MB/S 10 MB/S

4B/5B

DECODER

CODE GROUP

ALIGNMENT

DESCRAMBLER

SERIAL TO

PARALLEL

NRZI TO NRZ

DECODER

CLOCK

RECOVERY

MLT-3 TO

BINARY

DECODER

ADAPTIVE

EQ AND BLW

COMP.

RXCLK

NCLK_50M

RX_DATA

RXCLK

MANCHESTER

TO NRZ

DECODER

CLOCK

RECOVERY

LINK PULSE

DETECTOR

RECEIVE

FILTER

SMART

SQUELCH

TD±

CLOCK

GENERATION

LED

DRIVERS

LEDS

SYSTEM CLOCK

REFERENCE

Figure 3-4 DSP Physical Layer Block Diagram

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10/100 COMMON

INPUT BUFFER

RD±

(ALSO FX_RD±)

3.0 Functional Description (Continued)

3.4 Physical Layer

The DP83816 has a full featured physical layer device with integrated PMD sub-layers to support both 10BASE-T and 100BASE-TX Ethernet protocols. The physical layer is designed for easy implementation of 10/100 Mb/s Ethernet home or office solutions. It interfaces directly to twisted pair media via an external transformer. The physical layer utilizes on chip Digital Signal Processing (DSP) technology and digital PLLs for robust performance under all operating conditions, enhanced noise immunity, and lower external component count when compared to analog solutions.

3.4.1 Auto-Negotiation

The Auto-Negotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest performance mode of operation supported by both devices. Fast Link Pulse (FLP) Bursts provide the signalling used to communicate Auto-Negotiation abilities between two devices at each end of a link segment. For further detail regarding Auto-Negotiation, refer to Clause 28 of the IEEE

802.3u specification. The DP83816 supports four different Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex), so the inclusion of Auto-Negotiation ensures that the highest performance protocol will be selected based on the advertised ability of the Link Partner. The Auto-Negotiation function within the DP83816 is controlled by internal register access. Auto-Negotiation will be set at powerup/reset, and also when a link status (up/valid) change occurs.

3.4.2 Auto-Negotiation Register Control

When Auto-Negotiation is enabled, the DP83816 transmits the abilities programmed into the Auto-Negotiation Advertisement register (ANAR) via FLP Bursts. Any combination of 10 Mb/s, 100 Mb/s, Half-Duplex, and Full Duplex modes may be selected. The default setting of bits [8:5] in the ANAR and bit 12 in the BMCR register are determined at power-up.

The BMCR provides software with a mechanism to control the operation of the DP83816. Bits 1 & 2 of the PHYSTS register are only valid if Auto-Negotiation is disabled or after Auto-Negotiation is complete. The Auto-Negotiation protocol compares the contents of the ANLPAR and ANAR registers and uses the results to automatically configure to the highest performance protocol common to the local and far-end port. The results of Auto-Negotiation may be accessed in register C0h (PHYSTS), bit 4: AutoNegotiation Complete, bit 2: Duplex Status and bit 1: Speed Status.

Auto-Negotiation Priority Resolution: — (1) 100BASE-TX Full Duplex (Highest Priority) — (2) 100BASE-TX Half Duplex

— (3) 10BASE-T Full Duplex — (4) 10BASE-T Half Duplex (Lowest Priority) The Basic Mode Control Register (BMCR) provides control

for enabling, disabling, and restarting the Auto-Negotiation process. When Auto-Negotiation is disabled the Speed Selection bit in the BMCR (bit 13) controls switching between 10 Mb/s or 100 Mb/s operation, and the Duplex Mode bit (bit 8) controls switching between full duplex operation and half duplex operation. The Speed Selection and Duplex Mode bits have no effect on the mode of

DP83816

operation when the Auto-Negotiation Enable bit (bit 12) is set.

The Basic Mode Status Register (BMSR) indicates the set of available abilities for technology types, Auto-Negotiation ability, and Extended Register Capability. These bits are permanently set to indicate the full functionality of the DP83816 (only the 100BASE-T4 bit is not set since the DP83816 does not support that function).

The BMSR also provides status on: — Auto-Negotiation complete (bit 5) — Link Partner advertising that a remote fault has occurred

(bit 4) — Valid link has been established (bit 2) — Support for Management Frame Preamble suppression

(bit 6) The Auto-Negotiation Advertisement Register (ANAR)

indicates the Auto-Negotiation abilities to be advertised by the DP83816. All available abilities are transmitted by default, but any ability can be suppressed by writing to the ANAR. Updating the ANAR to suppress an ability is one way for a management agent to change (force) the technology that is used.

The Auto-Negotiation Link Partner Ability Register (ANLPAR) is used to receive the base link code word as well as all next page code words during the negotiation. Furthermore, the ANLPAR will be updated to either 0081h or 0021h for parallel detection to either 100 Mb/s or 10 Mb/s respectively.

The Auto-Negotiation Expansion Register (ANER) indicates additional Auto-Negotiation status. The ANER provides status on:

— Parallel Detect Fault occurrence (bit 4) — Link Partner support of the Next Page function (bit 3) — DP83816 support of the Next Page function (bit 2). The

DP83816 supports the Next Page function. — Current page being exchanged by Auto-Negotiation has

been received (bit1) — Link Partner support of Auto-Negotiation (bit 0)

3.4.3 Auto-Negotiation Parallel Detection

The DP83816 supports the Parallel Detection function as defined in the IEEE 802.3u specification. Parallel Detection requires both the 10 Mb/s and 100 Mb/s receivers to monitor the receive signal and report link status to the Auto-Negotiation function. Auto-Negotiation uses this information to configure the correct technology in the event that the Link Partner does not support Auto-Negotiation yet is transmitting link signals that the 100BASE-TX or 10BASE-T PMAs (Physical Medium Attachments) recognize as valid link signals.

If the DP83816 completes Auto-Negotiation as a result of Parallel Detection, bits 5 and 7 within the ANLPAR register will be updated to reflect the mode of operation present in the Link Partner. Note that bits 4:0 of the ANLPAR will also be set to 00001 based on a successful parallel detection to indicate a valid 802.3 selector field. Software may determine that negotiation completed via Parallel Detection by reading the ANER (98h) register with bit 0, Link Partner Auto-Negotiation Able bit, being reset to a zero, once the Auto-Negotiation Complete bit, bit 5 of the BMSR (84h) register is set to a one. If configured for parallel detect

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3.0 Functional Description (Continued)

mode, and any condition other than a single good link occurs, then the parallel detect fault bit will set to a one, bit 4 of the ANER register (98h).

3.4.4 Auto-Negotiation Restart

Once Auto-Negotiation has completed, it may be restarted at any time by setting bit 9 (Restart Auto-Negotiation) of the BMCR to one. If the mode configured by a successful AutoNegotiation loses a valid link, then the Auto-Negotiation process will resume and attempt to determine the configuration for the link. This function ensures that a valid configuration is maintained if the cable becomes disconnected.

A renegotiation request from any entity, such as a management agent, will cause the DP83816 to halt any transmit data and link pulse activity until the break_link_timer expires (~1500 ms). Consequently, the Link Partner will go into link fail and normal AutoNegotiation resumes. The DP83816 will resume AutoNegotiation after the break_link_timer has expired by issuing FLP (Fast Link Pulse) bursts.

3.4.5 Enabling Auto-Negotiation via Software

It is important to note that if the DP83816 has been initialized upon power-up as a non-auto-negotiating device (forced technology), and it is then required that AutoNegotiation or re-Auto-Negotiation be initiated via software, bit 12 (Auto-Negotiation Enable) of the Basic Mode Control Register must first be cleared and then set for any AutoNegotiation function to take effect.

3.4.6 Auto-Negotiation Complete Time

Parallel detection and Auto-Negotiation take approximately 2-3 seconds to complete. In addition, Auto-Negotiation with next page should take approximately 2-3 seconds to complete, depending on the number of next pages sent.

Refer to Clause 28 of the IEEE 802.3u standard for a full description of the individual timers related to AutoNegotiation.

3.5 LED Interfaces

The DP83816 has parallel outputs to indicate the status of Activity (Transmit or Receive), 100 Mb/s Link, and 10 Mb/s Link.

The LEDACTN pin indicates the presence of transmit or receive activity. The standard CMOS driver goes low when RX or TX activity is detected in either 10 Mb/s or 100 Mb/s operation.

The LED100N pin indicates a good link at 100 Mb/s data rate. The standard CMOS driver goes low when this occurs. In 100BASE-T mode, link is established as a result of input receive amplitude compliant with TP-PMD specifications which will result in internal generation of signal detect. This signal will assert after the internal Signal Detect has remained asserted for a minimum of 500 us. The signal will de-assert immediately following the deassertion of the internal signal detect.

The LED10N pin indicates a good link at 10 Mb/s data rate. The standard CMOS driver goes low when this occurs. 10 Mb/s Link is established as a result of the reception of at least seven consecutive normal Link Pulses or the reception of a valid 10BASE-T packet. This will cause the assertion of this signal. the signal will de-assert in accordance with the Link Loss Timer as specified in IEEE

802.3. The DP83816 LED pins are capable of 6 mA. Connection

of these LED pins should ensure this is not overloaded. Using 2 mA LED devices the connection for the LEDs could be as shown in Figure 3-5.

LEDACTN

453 Ω

LED100N

453 Ω

LED10N

453 Ω

Figure 3-5 LED Loading Example

DP83816

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3.0 Functional Description (Continued)

3.6 Half Duplex vs. Full Duplex

The DP83816 supports both half and full duplex operation at both 10 Mb/s and 100 Mb/s speeds.

Half-duplex is the standard, traditional mode of operation which relies on the CSMA/CD protocol to handle collisions and network access. In Half-Duplex mode, CRS responds to both transmit and receive activity in order to maintain compliance with IEEE 802.3 specification.

Since the DP83816 is designed to support simultaneous transmit and receive activity it is capable of supporting fullduplex switched applications with a throughput of up to 200 Mb/s per port when operating in 100BASE-TX mode. Because the CSMA/CD protocol does not apply to fullduplex operation, the DP83816 disables its own internal collision sensing and reporting functions.

It is important to understand that while full Auto-Negotiation with the use of Fast Link Pulse code words can interpret and configure to support full-duplex, parallel detection can not recognize the difference between full and half-duplex from a fixed 10 Mb/s or 100 Mb/s link partner over twisted pair. Therefore, as specified in 802.3u, if a far-end link partner is transmitting forced full duplex 100BASE-TX for example, the parallel detection state machine in the receiving station would be unable to detect the full duplex capability of the far-end link partner and would negotiate to a half duplex 100BASE-TX configuration (same scenario for 10 Mb/s).

For full duplex operation, the following register bits must also be set:

— TXCFG:CSI (Carrier Sense Ignore) — TXCFG:HBI (HeartBeat Ignore) — RXCFG:ATX (Accept Transmit Packets) Additionally, the Auto-Negotiation Select bits in the

Configuration register must show full duplex support: — CFG:ANEG_SEL

3.7 Phy Loopback

The DP83816 includes a Phy Loopback Test mode for easy board diagnostics. The Loopback mode is selected through bit 14 (Loopback) of the Basic Mode Control Register (BMCR). Writing 1 to this bit enables transmit data to be routed to the receive path early in the physical layer cell. Loopback status may be checked in bit 3 of the PHY Status Register (C0h). While in Loopback mode the data will not be transmitted onto the media. This is true for either 10 Mb/s as well as 100 Mb/s data.

In 100BASE-TX Loopback mode the data is routed through the PCS and PMA layers into the PMD sublayer before it is

DP83816

looped back. Therefore, in addition to serving as a board diagnostic, this mode serves as quick functional verification of the device.

Note: A Mac Loopback can be performed via setting bit 29 (Mac Loopback) in the Tx Configuration Register.

3.8 Status Information

There are 3 pins that are available to convey status information to the user through LEDs to indicate the speed (10 Mb/s or 100 Mb/s) link status and receive or transmit activity.

10 Mb/s Link is established as a result of the reception of at least seven consecutive Normal Link Pulses or the reception of a valid 10BASE-T packet. LED10N will deassert in accordance with the Link Loss Timer specified in IEEE 802.3.

100BASE-T Link is established as a result of an input receive amplitude compliant with TP-PMD specifications which will result in internal generation of Signal Detect. LED100N will assert after the internal Signal Detect has remained asserted for a minimum of 500 µs. LED100N will de-assert immediately following the de-assertion of the internal Signal Detect.

Activity LED status indicates Receive or Transmit activity.

3.9 100BASE-TX TRANSMITTER

The 100BASE-TX transmitter consists of several functional blocks which convert synchronous 4-bit nibble data, to a scrambled MLT-3 125 Mb/s serial data stream. Because the 100BASE-TX TP-PMD is integrated, the differential output pins, TD±, can be directly routed to the magnetics.

The block diagram in Figure 3-6 provides an overview of each functional block within the 100BASE-TX transmit section.

The Transmitter section consists of the following functional blocks:

— Code-group Encoder and Injection block (bypass option) — Scrambler block (bypass option) — NRZ to NRZI encoder block — Binary to MLT-3 converter / Common Driver The bypass option for the functional blocks within the

100BASE-TX transmitter provides flexibility for applications such as 100 Mb/s repeaters where data conversion is not always required. The DP83816 implements the 100BASETX transmit state machine diagram as specified in the IEEE 802.3u Standard, Clause 24.

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3.0 Functional Description (Continued)

TXCLK

FROM CGM

DP83816

TXD(3:0)/TXER

4B5B CODE-

GROUP ENABLER

BP_4B5B

BP_SCR

100BASE-TX

LOOPBACK

MUX

5B PARALLEL

TO SERIAL

SCRAMBLER

MUX

NRZ TO NRZI

BINARY TO MLT-3/ COMMON

DRIVER

MUX

ENCODER

Figure 3-6 100BASE-TX Transmit Block Diagram

3.9.1 Code-group Encoding and Injection

The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups for transmission. This conversion is required to allow control data to be combined with packet data code-groups. Refer to Table 3-1 for 4B to 5B code-group mapping details.

The code-group encoder substitutes the first 8-bits of the MAC preamble with a J/K code-group pair (11000 10001) upon transmission. The code-group encoder continues to replace subsequent 4B preamble and data nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the de-assertion of Transmit Enable signal from the MAC, the code-group encoder injects the T/R code-group pair (01101 00111) indicating the end of frame.

After the T/R code-group pair, the code-group encoder continuously injects IDLEs into the transmit data stream until the next transmit packet is detected (re-assertion of Transmit Enable).

TD +/-

3.9.2 Scrambler

The scrambler is required to control the radiated emissions at the media connector and on the twisted pair cable (for 100BASE-TX applications). By scrambling the data, the total energy launched onto the cable is randomly distributed over a wide frequency range. Without the scrambler, energy levels at the PMD and on the cable could peak beyond FCC limitations at frequencies related to repeating 5B sequences (i.e., continuous transmission of IDLEs).

The scrambler is configured as a closed loop linear feedback shift register (LFSR) with an 11-bit polynomial. The output of the closed loop LFSR is X-ORd with the serial NRZ data from the code-group encoder. The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at certain frequencies by as much as 20 dB.

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3.0 Functional Description (Continued)

3.9.3 NRZ to NRZI Encoder

After the transmit data stream has been serialized and scrambled, the data must be NRZI encoded in order to comply with the TP-PMD standard for 100BASE-TX transmission over Category-5 un-shielded twisted pair cable. There is no ability to bypass this block within the DP83816.

binary_plus

binary_in

binary_minus

differential MLT-3

3.9.4 Binary to MLT-3 Convertor / Common Driver

The Binary to MLT-3 conversion is accomplished by converting the serial binary data stream output from the NRZI encoder into two binary data streams with alternately phased logic one events. These two binary streams are then fed to the twisted pair output driver which converts the voltage to current and alternately drives either side of the transmit transformer primary winding, resulting in a minimal current (20 mA max) MLT-3 signal. Refer to Figure 3-7

binary_in

binary_plus

COMMON

DRIVER

binary_minus

MLT-3

DP83816

Figure 3-7 Binary to MLT-3 conversion

Table 3-1 4B5B Code-Group Encoding/Decoding

Name PCS 5B Code-group Description/4B Value

DATA CODES

0 11110 0000 1 01001 0001 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 A 10110 1010

B 10111 1011 C 11010 1100 D 11011 1101 E 11100 1110 F 11101 1111

IDLE AND CONTROL CODES

H 00100 HALT code-group - Error code

I 11111 Inter-Packet IDLE - 0000

J 11000 First Start of Packet - 0101 K 10001 Second Start of Packet - 0101 T 01101 First End of Packet - 0000 R 00111 Second End of Packet - 0000

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3.0 Functional Description (Continued)

Table 3-1 4B5B Code-Group Encoding/Decoding

Name PCS 5B Code-group Description/4B Value

INVALID CODES

V 00000 V 00001 V 00010 V 00011 V 00101 V 00110 V 01000 V 01100 V 10000 V 11001

DP83816

The 100BASE-TX MLT-3 signal sourced by the TD± common driver output pins is slew rate controlled. This should be considered when selecting AC coupling magnetics to ensure TP-PMD Standard compliant transition times (3 ns < Tr < 5 ns).

The 100BASE-TX transmit TP-PMD function within the DP83816 is capable of sourcing only MLT-3 encoded data. Binary output from the TD± outputs is not possible in 100 Mb/s mode.

3.10 100BASE-TX Receiver

The 100BASE-TX receiver consists of several functional blocks which convert the scrambled MLT-3 125 Mb/s serial data stream to synchronous 4-bit nibble data that is provided to the MAC. Because the 100BASE-TX TP-PMD is integrated, the differential input pins, RD±, can be directly routed from the AC coupling magnetics.

See Figure 3-8 for a block diagram of the 100BASE-TX receive function. This provides an overview of each functional block within the 100BASE-TX receive section.

The Receive section consists of the following functional blocks:

—ADC — Input and BLW Compensation — Signal Detect — Digital Adaptive Equalization — MLT-3 to Binary Decoder — Clock Recovery Module — NRZI to NRZ Decoder — Serial to Parallel — De-scrambler (bypass option) — Code Group Alignment — 4B/5B Decoder (bypass option) — Link Integrity Monitor — Bad SSD Detection The bypass option for the functional blocks within the

100BASE-TX receiver provides flexibility for applications such as 100 Mb/s repeaters where data conversion is not always required.

3.10.1 Input and Base Line Wander Compensation

Unlike the DP83223V Twister, the DP83816 requires no external attenuation circuitry at its receive inputs, RD+/−. It accepts TP-PMD compliant waveforms directly, requiring only a 100Ω termination plus a simple 1:1 transformer.

The DP83816 is completely ANSI TP-PMD compliant and includes Base Line Wander (BLW) compensation. The BLW compensation block can successfully recover the TPPMD defined “killer” pattern and pass it to the digital adaptive equalization block.

BLW can generally be defined as the change in the average DC content, over time, of an AC coupled digital transmission over a given transmission medium. (i.e. copper wire).

BLW results from the interaction between the low frequency components of a transmitted bit stream and the frequency response of the AC coupling component(s) within the transmission system. If the low frequency content of the digital bit stream goes below the low frequency pole of the AC coupling transformers then the droop characteristics of the transformers will dominate resulting in potentially serious BLW.

The digital oscilloscope plot provided in Figure 3-9 illustrates the severity of the BLW event that can theoretically be generated during 100BASE-TX packet transmission. This event consists of approximately 800 mV of DC offset for a period of 120 us. Left uncompensated, events such as this can cause packet loss.

3.10.2 Signal Detect

The signal detect function of the DP83816 is incorporated to meet the specifications mandated by the ANSI FDDI TPPMD Standard as well as the IEEE 802.3 100BASE-TX Standard for both voltage thresholds and timing parameters.

Note that the reception of normal 10BASE-T link pulses and fast link pulses per IEEE 802.3u Auto-Negotiation by the 100BASE-TX receiver do not cause the DP83816 to assert signal detect.

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3.0 Functional Description (Continued)

DP83816

LINK INTEGRITY

MONITOR

RX_DATA VALID

SSD DETECT

RXCLK

BP_SCR

BP_RX

BP_4B5B

RXD(3:0)/RXER

MUX

4B/5B DECODER

SERIAL TO

PARALLEL

CODE GROUP

ALIGNMENT

MUX

CLOCK

RECOVERY

CLOCK

MODULE

DESCRAMBLER

NRZI TO NRZ

DECODER

MLT-3 TO BINARY

DECODER

DIGITAL

ADAPTIVE

EQUALIZATION

AGC

INPUT BLW

COMPENSATION

ADC

SIGNAL

DETECT

RD +/-

Figure 3-8 100 M/bs Receive Block Diagram

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3.0 Functional Description (Continued)

DP83816

Figure 3-9 100BASE-TX BLW Event Diagram

3.10.3 Digital Adaptive Equalization

When transmitting data at high speeds over copper twisted pair cable, frequency dependent attenuation becomes a concern. In high-speed twisted pair signalling, the frequency content of the transmitted signal can vary greatly during normal operation based primarily on the randomness of the scrambled data stream. This variation in signal attenuation caused by frequency variations must be compensated for to ensure the integrity of the transmission.

In order to ensure quality transmission when employing MLT-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. The selection of long cable lengths for a given implementation, requires significant compensation which will over-compensate for shorter, less attenuating lengths. Conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. Therefore, the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length.

The DP83816 utilizes an extremely robust equalization scheme referred to herein as ‘Digital Adaptive Equalization’. Traditional designs use a pseudo adaptive equalization scheme that determines the approximate cable length by monitoring signal attenuation at certain frequencies. This attenuation value was compared to the internal receive input reference voltage. This comparison would indicate the amount of equalization to use. Although this scheme is used successfully on the DP83223V twister,

it is sensitive to transformer mismatch, resistor variation and process induced offset. The DP83223V also required an external attenuation network to help match the incoming signal amplitude to the internal reference.

The Digital Equalizer removes ISI (Inter Symbol Interference) from the receive data stream by continuously adapting to provide a filter with the inverse frequency response of the channel. When used in conjunction with a gain stage, this enables the receive 'eye pattern' to be opened sufficiently to allow very reliable data recovery.

Traditionally 'adaptive' equalizers selected 1 of N filters in an attempt to match the cables characteristics. This approach will typically leave holes at certain cable lengths, where the performance of the equalizer is not optimized. The DP83816 equalizer is truly adaptive.

The curves given in Figure 3-10 illustrate attenuation at certain frequencies for given cable lengths. This is derived from the worst case frequency vs. attenuation figures as specified in the EIA/TIA Bulletin TSB-36. These curves indicate the significant variations in signal attenuation that must be compensated for by the receive adaptive equalization circuit.

Figure 3-11 represents a scrambled IDLE transmitted over zero meters of cable as measured at the AII (Active Input Interface) of the receiver. Figure 3-12 and Figure 3-13 represent the signal degradation over 50 and 100 meters of category V These plots show the extreme degradation of signal integrity and indicate the requirement for a robust adaptive equalizer.

cable respectively, also measured at the AII.

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3.0 Functional Description (Continued)

DP83816

2ns/div

Figure 3-10 EIA/TIA Attenuation vs. Frequency for 0, 50,

100, 130 & 150 meters of CAT V

cable

2ns/div

Figure 3-11 MLT-3 Signal Measured at AII after 0 meters

of CAT V cable

3.10.4 Line Quality Monitor

It is possible to determine the amount of Equalization being used by accessing certain test registers with the DSP engine. This provides a crude indication of connected cable length. This function allows for a quick and simple verification of the line quality in that any significant deviation from an expected register value (based on a known cable length) would indicate that the signal quality has deviated from the expected nominal case.

Figure 3-12 MLT-3 Signal Measured at AII after 50

meters of CAT V

cable

2ns/div

Figure 3-13 MLT-3 Signal Measured at AII after 100

meters of CAT V

3.10.5 MLT-3 to NRZI Decoder

The DP83816 decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary NRZI data.

cable

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3.0 Functional Description (Continued)

3.10.6 Clock Recovery Module

The Clock Recovery Module (CRM) accepts 125 Mb/s MLT3 data from the equalizer. The DPLL locks onto the 125 Mb/s data stream and extracts a 125 MHz recovered clock. The extracted and synchronized clock and data are used as required by the synchronous receive operations as generally depicted in Figure 3-8.

The CRM is implemented using an advanced all digital Phase Locked Loop (PLL) architecture that replaces sensitive analog circuitry. Using digital PLL circuitry allows the DP83816 to be manufactured and specified to tighter tolerances.

3.10.7 NRZI to NRZ

In a typical application, the NRZI to NRZ decoder is required in order to present NRZ formatted data to the descrambler (or to the code-group alignment block, if the descrambler is bypassed, or directly to the PCS, if the receiver is bypassed).

3.10.8 Serial to Parallel

The 100BASE-TX receiver includes a Serial to Parallel converter which supplies 5-bit wide data symbols to the PCS Rx state machine.

3.10.9 De-scrambler

A serial de-scrambler is used to de-scramble the received NRZ data. The de-scrambler has to generate an identical data scrambling sequence (N) in order to recover the original unscrambled data (UD) from the scrambled data (SD) as represented in the equations:

SD UD N⊕()= UD SD N⊕()=

Synchronization of the de-scrambler to the original scrambling sequence (N) is achieved based on the knowledge that the incoming scrambled data stream consists of scrambled IDLE data. After the de-scrambler has recognized 12 consecutive IDLE code-groups, where an unscrambled IDLE code-group in 5B NRZ is equal to five consecutive ones (11111), it will synchronize to the receive data stream and generate unscrambled data in the form of unaligned 5B code-groups.

In order to maintain synchronization, the de-scrambler must continuously monitor the validity of the unscrambled data that it generates. To ensure this, a line state monitor and a hold timer are used to constantly monitor the synchronization status. Upon synchronization of the descrambler the hold timer starts a 722 µs countdown. Upon detection of sufficient IDLE code-groups (58 bit times) within the 722 µs period, the hold timer will reset and begin a new countdown. This monitoring operation will continue indefinitely given a properly operating network connection with good signal integrity. If the line state monitor does not

DP83816

recognize sufficient unscrambled IDLE code-groups within the 722 µs period, the entire de-scrambler will be forced out of the current state of synchronization and reset in order to re-acquire synchronization.

3.10.10 Code-group Alignment

The code-group alignment module operates on unaligned 5-bit data from the de-scrambler (or, if the de-scrambler is bypassed, directly from the NRZI/NRZ decoder) and converts it into 5B code-group data (5 bits). Code-group alignment occurs after the J/K code-group pair is detected. Once the J/K code-group pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary.

3.10.11 4B/5B Decoder

The code-group decoder functions as a look up table that translates incoming 5B code-groups into 4B nibbles. The code-group decoder first detects the J/K code-group pair preceded by IDLE code-groups and replaces the J/K with MAC preamble. Specifically, the J/K 10-bit code-group pair is replaced by the nibble pair (0101 0101). All subsequent 5B code-groups are converted to the corresponding 4B nibbles for the duration of the entire packet. This conversion ceases upon the detection of the T/R codegroup pair denoting the End of Stream Delimiter (ESD) or with the reception of a minimum of two IDLE code-groups.

3.10.12 100BASE-TX Link Integrity Monitor

The 100 Base-TX Link monitor ensures that a valid and stable link is established before enabling both the Transmit and Receive PCS layer.

Signal detect must be valid for 395 µs to allow the link monitor to enter the 'Link Up' state, and enable the transmit and receive functions.

Signal detect can be forced active by setting Bit 1 of the PCSR.

Signal detect can be optionally ANDed with the descrambler locked indication by setting bit 8 of the PCSR. When this option is enabled, then De-scrambler 'locked' is required to enter the Link Up state, but only Signal detect is required to maintain the link in the link Up state.

3.10.13 Bad SSD Detection

A Bad Start of Stream Delimiter (Bad SSD) is any transition from consecutive idle code-groups to non-idle code-groups which is not prefixed by the code-group pair J/K.

If this condition is detected, the DP83816 will assert RXER and present RXD[3:0] = 1110 to the MAC for the cycles that correspond to received 5B code-groups until at least two IDLE code groups are detected. In addition, the False Carrier Event Counter will be incremented by one.

Once at least two IDLE code groups are detected, the error is reported to the MAC.

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3.0 Functional Description (Continued)

3.11 10BASE-T Transceiver Module

The 10BASE-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision, heartbeat, loopback, jabber, and link integrity functions, as defined in the standard. An external filter is not required on the 10BASE-T interface since this is integrated inside the DP83816. This section focuses on the general 10BASE-T system level operation.

3.11.1 Operational Modes

The DP83816 has two basic 10BASE-T operational modes:

— Half Duplex mode - functions as a standard IEEE 802.3

10BASE-T transceiver supporting the CSMA/CD protocol.

— Full Duplex mode - capable of simultaneously

transmitting and receiving without reporting a collision. The DP83816's 10 Mb/s ENDEC is designed to encode and decode simultaneously.

3.11.2 Smart Squelch

The smart squelch is responsible for determining when valid data is present on the differential receive inputs (RD±). The DP83816 implements an intelligent receive squelch to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. Smart squelch operation is independent of the 10BASE-T operational mode.

DP83816

The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10BASE-T standard) to determine the validity of data on the twisted pair inputs (refer to Figure 3-14).

The signal at the start of packet is checked by the smart squelch and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch level is overcome correctly, the opposite squelch level must then be exceeded within 150 ns. Finally the signal must again exceed the original squelch level within a 150 ns to ensure that the input waveform will not be rejected. This checking procedure results in the loss of typically three preamble bits at the beginning of each packet.

Only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder of the circuitry that valid data is present. At this time, the smart squelch circuitry is reset.

Valid data is considered to be present until the squelch level has not been generated for a time longer than 150 ns, indicating the End of Packet. Once good data has been detected the squelch levels are reduced to minimize the effect of noise causing premature End of Packet detection.

SQ+(reduced)

SQ-(reduced)

SQ+

<150 ns

SQ-

<150 ns

start of packet

Figure 3-14 10BASE-T Twisted Pair Smart Squelch Operation

3.11.3 Collision Detection

When in Half Duplex, a 10BASE-T collision is detected when the receive and transmit channels are active simultaneously. Collisions are reported to the MAC. Collisions are also reported when a jabber condition is detected.

If the ENDEC is receiving when a collision is detected it is reported immediately (through the COL signal).

When heartbeat is enabled, approximately 1 µs after the transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10 bit times is generated to indicate successful transmission.

The SQE test is inhibited when the physical layer is set in full duplex mode. SQE can also be inhibited by setting the HEARTBEAT_DIS bit in the TBTSCR register.

>150 ns

end of packet

3.11.4 Normal Link Pulse Detection/Generation

The link pulse generator produces pulses as defined in the IEEE 802.3 10BASE-T standard. Each link pulse is nominally 100 ns in duration and transmitted every 16 ms in the absence of transmit data.

Link pulses are used to check the integrity of the connection with the remote end. If valid link pulses are not received, the link detector disables the 10BASE-T twisted pair transmitter, receiver and collision detection functions.

When the link integrity function is disabled (FORCE_LINK_10 of the TBTSCR register), good link is forced and the 10BASE-T transceiver will operate regardless of the presence of link pulses.

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3.0 Functional Description (Continued)

3.11.5 Jabber Function

The jabber function monitors the DP83816's output and disables the transmitter if it attempts to transmit a packet of longer than legal size. A jabber timer monitors the transmitter and disables the transmission if the transmitter is active for approximately 20-30 ms.

Once disabled by the jabber function, the transmitter stays disabled for the entire time that the ENDEC module's internal transmit enable is asserted. This signal has to be de-asserted for approximately 400-600 ms (the “unjab” time) before the jabber function re-enables the transmit outputs.

The Jabber function is only meaningful in 10BASE-T mode.

3.11.6 Automatic Link Polarity Detection

The DP83816's 10BASE-T transceiver module incorporates an automatic link polarity detection circuit. When seven consecutive link pulses or three consecutive receive packets with inverted End-of-Packet pulses are received, bad polarity is reported.

A polarity reversal can be caused by a wiring error at either end of the cable, usually at the Main Distribution Frame (MDF) or patch panel in the wiring closet.

The bad polarity condition is latched. The DP83816's 10BASE-T transceiver module corrects for this error internally and will continue to decode received data correctly. This eliminates the need to correct the wiring error immediately.

3.11.7 10BASE-T Internal Loopback

When the LOOPBACK bit in the BMCR register is set, 10BASE-T transmit data is looped back in the ENDEC to the receive channel. The transmit drivers and receive input circuitry are disabled in transceiver loopback mode, isolating the transceiver from the network.

Loopback is used for diagnostic testing of the data path through the transceiver without transmitting on the network or being interrupted by receive traffic. This loopback function causes the data to loopback just prior to the 10BASE-T output driver buffers such that the entire transceiver path is tested.

3.11.8 Transmit and Receive Filtering

External 10BASE-T filters are not required when using the DP83816, as the required signal conditioning is integrated into the device.

Only isolation/step-up transformers and impedance matching resistors are required for the 10BASE-T transmit and receive interface. The internal transmit filtering ensures that all the harmonics in the transmit signal are attenuated by at least 30 dB.

3.11.9 Transmitter

The encoder begins operation when the transmit enable input to the physical layer is asserted and converts NRZ data to pre-emphasized Manchester data for the transceiver. For the duration of assertion, the serialized transmit data is encoded for the transmit-driver pair (TD±). The last transition is always positive; it occurs at the center of the bit cell if the last bit is a one, or at the end of the bit cell if the last bit is a zero.

3.11.10 Receiver

The decoder consists of a differential receiver and a PLL to separate a Manchester encoded data stream into internal

DP83816

clock signals and data. The differential input must be externally terminated with a differential 100Ω termination network to accommodate UTP cable. The internal impedance of RD± (typically 1.1KΩ) is in parallel with two

54.9Ω resistors to approximate the 100Ω termination. The decoder detects the end of a frame when no more mid-

bit transitions are detected.

3.11.11 Far End Fault Indication

Auto-Negotiation provides a mechanism for transferring information from the Local Station to the Link Partner that a remote fault has occurred for 100BASE-TX.

A remote fault is an error in the link that one station can detect while the other cannot. An example of this is a disconnected fiber at a station’s transmitter. This station will be receiving valid data and detect that the link is good via the Link Integrity Monitor, but will not be able to detect that its transmission is not propagating to the other station.

If three or more FEFI IDLE patterns are detected by the DP83816, then bit 4 of the Basic Mode Status register is set to one until read by management, additionally bit 7 of the PHY Status register is also set.

The first FEFI IDLE pattern may contain more than 84 ones as the pattern may have started during a normal IDLE transmission which is actually quite likely to occur. However, since FEFI is a repeating pattern, this will not cause a problem with the FEFI function. It should be noted that receipt of the FEFI IDLE pattern will not cause a Carrier Sense error to be reported.

If the FEFI function has been disabled via FEFI_EN (bit 3) of the PCSR Configuration register, then the DP83816 will not send the FEFI IDLE pattern.

3.12 802.3u MII

The DP83816 incorporates the Media Independent Interface (MII) as specified in Clause 22 of the IEEE 802.3u standard. This interface may be used to connect PHY devices. This section describes the MII configuration steps as well as the serial MII management interface and nibble wide MII data interface.

3.12.1 MII Access Configuration

The DP83816 must be specifically configured for accessing the MII. This is done by first connecting pin 133 (MD1/CFGDISN) to GND through a 1KΩ resistor. Then setting bit 12 (EXT_PHY) of the CFG register (offset 04h) to 1. See Section 4.2.2. When this bit is set, the internal Phy is automatically disabled, as reported by bit 9 (PHY_DIS) of the CFG register. The MII must then be initialized, as described in Section 3.12.4, before the external PHY can be detected.

If external MII is not selected through the register setting as described, then the internal Phy is used and the MII pins of the MacPhyter-II can be left unconnected.

3.12.2 MII Serial Management

The MII serial management interface allows for the configuration and control of PHY registers, gathering of status, error information, and the determination of the type and capabilities of the attached PHY(s).

The MII serial management specification defines a set of thirty-two 16-bit status and control registers that are accessible through the management interface pins MDC and MDIO. A description of the serial management interface access and access protocol follows.

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3.0 Functional Description (Continued)

3.12.3 MII Serial Management Access

Management access to the PHY(s) is done via Management Data Clock (MDC) and Management Data Input/Output (MDIO). MDC has a maximum clock rate of 25 MHz and no minimum rate. The MDIO line is bi-directional and may be shared by up to 32 devices. The internal PHY counts as one of these 32 devices.

The internal PHY has the advantage of having direct register access but can also be controlled exactly like a PHY, with a default address of 1Fh, connected to the MII.

Access and control of the MDC and MDIO pins is done via the MII/EEPROM Access Register (MEAR). The clock (MDC) is created by alternating writes of 0 then 1 to the MDC bit (bit 6). Control of data direction is done by the MDDIR bit (bit 5). Data is either recorded or written by the MDIO bit (bit 4). Setting the MDDIR bit to a 1 allows the DP83816 to drive the MDIO pin. Setting the MDDIR bit to a 0 allows the MDIO bit to reflect the value of the MDIO pin. See Section 4.2.3

This bit-bang access of the MDC and MDIO pins thus requires 64 accesses to the MEAR register to complete a single PHY register transaction. Since a PHY device is typically self configuring and adaptive this serial management access is usually only required at initialization time and therefore is not time critical.

DP83816

3.12.4 Serial Management Access Protocol

The serial control interface clock (MDC) has a maximum clock rate of 25 MHz and no minimum rate. The MDIO line is bi-directional and may be shared by up to 32 devices. The MDIO frame format is shown in Table 3-2.

If external PHY devices may be attached and removed from the MII there should be a 15 KΩ pull-down resistor on the MDIO signal. If the PHY will always be connected then there should be a 1.5 kΩ pull-up resistor which, during IDLE and turnaround, will pull MDIO high. In order to initialize the MDIO interface, the DP83816 sends a sequence of 32 contiguous logic ones on MDIO provides the PHY(s) with a sequence that can be used to establish synchronization. This preamble may be generated either by driving MDIO high for 32 consecutive MDC clock cycles, or by simply allowing the MDIO pull-up resistor to pull the MDIO pin high during which time 32 MDC clock cycles are provided. In addition 32 MDC clock cycles should be used to re-sync the device if an invalid start, opcode, or turnaround bit is detected.

Table 3-2 Typical MDIO Frame Format

MII Management

Serial Protocol

Read Operation <idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>

Write Operation <idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>

The Start code is indicated by a <01> pattern. This assures the MDIO line transitions from the default idle line state.

Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no device shall actively drive the MDIO signal during the first bit of

Turnaround. The addressed PHY drives the MDIO with a zero for the second bit of turnaround and follows this with the required data. Figure 3-15 shows the timing relationship between MDC and the MDIO as driven/received by the DP83816 and a PHY for a typical register read access.

MDC

MDIO

(STA)

MDIO

(PHY)

00011 110000 000

Idle Start

Opcode

(Read)

PHY Address

(PHYAD = 0Ch)

(00h = BMCR)

0 0 011000100000000

Figure 3-15 Typical MDC/MDIO Read Operation

Idle

For write transactions, the DP83816 writes data to the addressed PHY thus eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the DP83816 by inserting <10>. Figure 3-16 shows the timing relationship for a typical MII register write access.

3.12.5 Nibble-wide MII Data Interface

Clause 22 of the IEEE 802.3u specification defines the Media Independent Interface. This interface include separate dedicated receive and transmit busses. These two data buses, along with various control and indication signals, allow for the simultaneous exchange of data between the DP83816 and PHY(s).

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3.0 Functional Description (Continued)

MDC

DP83816

MDIO

(STA)

00011110000000

Idle Start

Opcode (Write)

PHY Address

(PHYAD = 0Ch)

(00h = BMCR)

Figure 3-16 Typical MDC/MDIO Write Operation

The receive interface consists of a nibble wide data bus RXD[3:0], a receive error signal RXER, a receive data valid flag RXDV, and a receive clock RXCLK for synchronous transfer of the data. The receive clock can operate at 2.5 MHz to support 10 Mb/s operation modes or at 25 MHz to support 100 Mb/s operational modes.

The transmit interface consists of a nibble wide data bus TXD[3:0], a transmit enable control signal TXEN, and a transmit clock TXCLK which runs at 2.5 MHz or 25 MHz.

Additionally, the MII includes the carrier sense signal CRS, as well as a collision detect signal COL. The CRS signal asserts to indicate the reception of data from the network or as a function of transmit data in Half Duplex mode. The COL signal asserts as an indication of a collision which can occur during half-duplex operation when both a transmit and receive operation occur simultaneously.

3.12.6 Collision Detection

For Half Duplex, a 10BASE-T or 100BASE-TX collision is detected when the receive and transmit channels are active simultaneously. Collisions are reported by the COL signal on the MII.

If the PHY is transmitting in 10 Mb/s mode when a collision is detected, the collision is not reported until seven bits

0 0 0 000 00000000

1000

have been received while in the collision state. This prevents a collision being reported incorrectly due to noise on the network. The COL signal remains set for the duration of the collision.

If a collision occurs during a receive operation, it is immediately reported by the COL signal.

When heartbeat is enabled (only applicable to 10 Mb/s operation), approximately 1µs after the transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10 bit times is generated (internally) to indicate successful transmission. SQE is reported as a pulse on the COL signal of the MII.

3.12.7 Carrier Sense

Carrier Sense (CRS) is asserted due to receive activity, once valid data is detected, during 10 Mb/s operation. During 100 Mb/s operation CRS is asserted when a valid link (SD) and two non-contiguous zeros are detected.

For 10 or 100 Mb/s Half Duplex operation, CRS is asserted during either packet transmission or reception.

For 10 or 100 Mb/s Full Duplex operation, CRS is asserted only due to receive activity.

CRS is de-asserted following an end of packet.

Idle

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4.0 Register Set

4.1 Configuration Registers

The DP83816 implements a PCI version 2.2 configuration register space. This allows a PCI BIOS to "soft" configure the DP83816. Software Reset has no effect on configuration registers. Hardware Reset returns all configuration registers to their hardware reset state. For all unused registers, writes are ignored, and reads return 0.

Table 4-1 Configuration Register Map

Offset Tag Description Access

00h CFGID Configuration Identification Register RO

04h CFGCS Configuration Command and Status Register R/W

08h CFGRID Configuration Revision ID Register RO

0Ch CFGLAT Configuration Latency Timer Register RO

10h CFGIOA Configuration IO Base Address Register R/W

14h CFGMA Configuration Memory Address Register R/W

18h-28h Reserved (reads return zero)

2Ch CFGSID Configuration Subsystem Identification Register RO

30h CFGROM Boot ROM configuration register R/W

34h CAPPTR Capabilities Pointer Register RO

38h Reserved (reads return zero)

3Ch CFGINT Configuration Interrupt Select Register R/W

40h PMCAP Power Management Capabilities Register RO

44h PMCSR Power Management Control and Status Register R/W

48-FFh Reserved (reads return zero)

DP83816

4.1.1 Configuration Identification Register

This register identifies the DP83816 Controller to PCI system software.

Tag: CFGID Size: 32 bits Hard Reset: 0020100Bh

Offset: 00h Access: Read Only Soft Reset: Unchanged

Bit Bit Name Description

31-16 DEVID Device ID

This field is read-only and is set to the device ID assigned by National Semiconductor to the DP83816, which is 0020h.

15-0 VENID Vendor ID

This field is read-only and is set to a value of 100Bh which is National Semiconductor's PCI Vendor ID.

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4.0 Register Set (Continued)

4.1.2 Configuration Command and Status Register

The CFGCS register has two parts. The upper 16-bits (31-16) are devoted to device status. A status bit is reset whenever the register is written, and the corresponding bit location is a 1. The lower 16-bits (15-0) are devoted to command and are used to configure and control the device.

Tag: CFGCS Size: 32 bits Hard Reset: 02900000h

Offset: 04h Access: Read Write Soft Reset: Unchanged

Bit Bit Name Description

31 DPERR Detected Parity Error

Refer to the description in the PCI V2.2 specification.

30 SSERR Signaled SERR

Refer to the description in the PCI V2.2 specification.

29 RMABT Received Master Abort

Refer to the description in the PCI V2.2 specification.

28 RTABT Received Target Abort

Refer to the description in the PCI V2.2 specification.

27 STABT Sent Target Abort

Refer to the description in the PCI V2.2 specification.

26-25 DSTIM DEVSELN Timing

This field will always be set to 01 indicating that DP83816 supports “medium” DEVSELN timing.

24 DPD Data Parity Detected

Refer to the description in the PCI V2.2 specification.

23 FBB Fast Back-to-Back Capable

DP83816 will set this bit to 1.

22-21 unused

(reads return 0)

20 NCPEN New Capabilities Enable

When set, this bit indicates that the Capabilities Pointer contains a valid value and new capabilities such as power management are supported. When clear, new capabilities (CAPPTR, PMCAP, PMCS) are disabled. This bit is loaded from a strap option, MD0 pin 132. A subsequent load of the configuration data from the EEPROM will overwrite any pre-existing value.

19-16 Unused

(reads return 0)

15-10 Unused

(reads return 0)

9 FBBEN Fast Back-to-Back Enable

Set to 1 by the PCI BIOS to enable the DP83816 to do Fast Back-to-Back transfers (FBB transfers as a master is not implemented in the current revision).

8 SERREN SERRN Enable

When SERREN and PERRSP are set, DP83816 will generate SERRN during target cycles when an address parity error is detected from the system. Also, when SERREN and PERRSP are set and CFG:PESEL is reset, master cycles detecting data parity errors will generate SERRN.

7 Unused

(reads return 0)

DP83816

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4.0 Register Set (Continued)

Bit Bit Name Description

6 PERRSP Parity Error Response

When set, DP83816 will assert PERRN on the detection of a data parity error when acting as the target, and will sample PERRN when acting as the initiator. Also, setting PERRSP allows SERREN to enable the assertion of SERRN. When reset, all address and data parity errors are ignored and neither SERRN nor PERRN are asserted.

5-3 Unused

(reads return 0)

2 BMEN Bus Master Enable

When set, DP83816 is allowed to act as a PCI bus master. When reset, DP83816 is prohibited from acting as a PCI bus master.

1 MSEN Memory Space Address

When set, DP83816 responds to memory space accesses. When reset, DP83816 ignores memory space accesses.

0 I/OSEN I/O Space Access

When set, DP83816 responds to I/O space accesses. When reset, DP83816 ignores I/O space accesses.

4.1.3 Configuration Revision ID Register

This register stores the silicon revision number, revision number of software interface specification and lets the configuration software know that it is an Ethernet controller in the class of network controllers.

DP83816

Tag: CFGRID Size: 32 bits Hard Reset: 02000000h

Offset: 08h Access: Read Only Soft Reset: Unchanged

Bit Bit Name Description

31-24 BASECL Base Class

Returns 02h which specifies a network controller.

23-16 SUBCL Sub Class

Returns 00h which specifies an Ethernet controller.

15-8 PROGIF Programming IF

Returns 00h which specifies the first release of the DP83816 Software Interface Specification.

7-0 REVID Silicon Revision

Returns 00h which specifies the silicon revision.

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4.0 Register Set (Continued)

4.1.4 Configuration Latency Timer Register

This register gives status and controls such miscellaneous functions as BIST, Latency timer and Cache line size.

Tag: CFGLAT Size: 32 bits Hard Reset: 00000000h

Offset: 0Ch Access: Read Write Soft Reset: Unchanged

Bit Bit Name Description

31 BISTCAP BIST Capable

Reads will always return 0.

30 BISTEN BIST Enable

Reads will return a 0, writes are ignored.

29-16 Reserved

Reads will return a 0, writes are ignored.

15-8 LAT Latency Timer

Set by software to the number of PCI clocks that DP83816 may hold the PCI bus.

7-0 CLS Cache Line Size

Ignored by DP83816.

DP83816

DP83816 Bus Master Operations: Independent of cache line size, the DP83816 will use the following PCI commands for bus mastered transfers:

0110 - Mem Read for all read cycles, 0111 - Mem Write for all write cycles.

4.1.5 Configuration I/O Base Address Register

This register specifies the Base I/O address which is required to build an address map during configuration. It also specifies the number of bytes required as well as an indication that it can be mapped into I/O space.

Tag: CFGIOA Size: 32 bits Hard Reset: 00000001h

Offset: 10h Access: Read Write Soft Reset: Unchanged

Bit Bit Name Description

31-8 IOBASE Base I/O Address

This is set by software to the base I/O address for the Operational Register Map.

7-2 IOSIZE Size indication

Read back as 0. This allows the PCI bridge to determine that the DP83816 requires 256 bytes of I/O space.

1 Unused

(reads return 0).

0 IOIND I/O Space Indicator

Set to 1 by DP83816 to indicate that DP83816 is capable of being mapped into I/O space. Read Only.

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4.0 Register Set (Continued)

4.1.6 Configuration Memory Address Register

This register specifies the Base Memory address which is required to build an address map during configuration. It also specifies the number of bytes required as well as an indication that it can be mapped into memory space.

Tag: CFGMA Size: 32 bits Hard Reset: 00000000h

Offset: 14h Access: Read Write Soft Reset: unchanged

Bit Bit Name Description

31-12 MEMBASE Memory Base Address

This is set by software to the base address for the Operational Register Map.

11- 4 MEMSIZE Memory Size

These bits return 0, which indicates that the DP83816 requires 4096 bytes of Memory Space (the minimum recommended allocation).

3 MEMPF Prefetchable

Set to 0 by DP83816. Read Only.

2-1 MEMLOC Location Selection

Set to 00 by DP83816. This indicates that the base register is 32-bits wide and can be placed anywhere in the 32-bit memory space. Read Only.

0 MEMIND Memory Space Indicator

Set to 0 by DP83816 to indicate that DP83816 is capable of being mapped into memory space. Read Only.

DP83816

4.1.7 Configuration Subsystem Identification Register

The CFGSID allows system software to distinguish between different subsystems based on the same PCI silicon. The values in this register can be loaded from the EEPROM if configuration is enabled.

Tag: CFGSID Size: 32 bits Hard Reset: 00000000h

Offset: 2Ch Access: Read Only Soft Reset: unchanged

Bit Bit Name Description

31-16 SDEVID Subsystem Device ID

Set to 0 by DP83816.

15-0 SVENID Subsystem Vendor ID

Set to 0 by DP83816.

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4.0 Register Set (Continued)

4.1.8 Boot ROM Configuration Register

Tag: CFGROM Size: 32 bits Hard Reset: 00000000h

Offset: 30h Access: Read Write Soft Reset: unchanged

Bit Bit Name Description

31-16 ROMBASE ROM Base Address

Set to the base address for the boot ROM.

15-11 ROMSIZE ROM Size

Set to 0 indicating a requirement for 64K bytes of Boot ROM space. Read only.

10-1 unused

(reads return 0)

0 ROMEN ROM Enable

This is used by the PCI BIOS to enable accesses to boot ROM. This allows the DP83816 to share the address decode logic between the boot ROM and itself. The BIOS will copy the contents of the boot ROM to system RAM before executing it. Set to 1 enables the address decode for boot ROM disabling access to operational target registers.

DP83816

4.1.9 Capabilities Pointer Register

This register stores the capabilities linked list offset into the PCI configuration space.

Tag: CAPPTR Size: 32 bits Hard Reset: 00000040h

Offset: 34h Access: Read Only Soft Reset: unchanged

Bit Bit Name Description

31-8 unused

(reads return 0)

7-0 CLOFS Capabilities List Offset

Offset into PCI configuration space for the location of the first item in the Capabilities Linked List, set to 40h to point to the PMCAP register.

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4.0 Register Set (Continued)

4.1.10 Configuration Interrupt Select Register

This register stores the interrupt line number as identified by the POST software that is connected to the interrupt controller as well as DP83816 desired settings for maximum latency and minimum grant. Max latency and Min latency can be loaded from the EEPROM.

Tag: CFGINT Size: 32 bits Hard Reset: 340b0100h

Offset: 3Ch Access: Read Write Soft Reset: unchanged

Bit Bit Name Description

31-24 MXLAT Maximum Latency

The DP83816 desired setting for Max Latency. The DP83816 will initialize this field to 52d (13 µsec). The value in this register can be loaded from the EEPROM.

23-16 MNGNT Minimum Grant

The DP83816 desired setting for Minimum Grant. The DP83816 will initialize this field to 11d (2.75 µsec). The value in this register can be loaded from the EEPROM.

15-8 IPIN Interrupt Pin

Read Only, always return 0000 0001 (INTA).

7-0 ILINE Interrupt Line

Set to which line on the interrupt controller that the DP83816's interrupt pin is connected to.

DP83816

4.1.11 Power Management Capabilities Register

This register provides information on the capabilities of the functions related to power management. This register also contains a pointer to the next item in the capabilities list and the capability ID for Power Management. This register is only visible if CFGCS[4] is set.

Tag: PMCAP Size: 32 bits Hard Reset: FF820001

Offset: 40h Access: Read Only Soft Reset: unchanged

Bit Bit Name Description

31-27 PMES PME Support

This 5 bit field indicates the power states in which DP83816 may assert PMEN. A 1 indicates PMEN is enabled for that state, a 0 indicates PMEN is inhibited in that state.

XXXX1 - PMEN can be asserted from state D0

XXX1X - PMEN can be asserted from state D1

XX1XX - PMEN can be asserted from state D2

X1XXX - PMEN can be asserted from state D3hot

1XXXX - PMEN can be asserted from state D3cold

The DP83816 will only report PME support for D3cold if auxiliary power is detected on the 3VAUX pin, in addition this value can be loaded from the EEPROM when in the D3cold state.

26 D2S D2 Support

This bit is set to a 1 when the DP83816 supports the D2 state.

25 D1S D1 Support

This bit is set to a 1 when the DP83816 supports the D1 state.

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4.0 Register Set (Continued)

Bit Bit Name Description

24-22 AUX_CURRENT Aux_Current

This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function.

If PMEN generation from D3cold is not supported by the function(PMCAP[31]), this field returns a value of "000b" when read.

Bit 3.3Vaux

24 23 22

1 1 0 320 mA

0 0 0 0 (self powered)

21 DSI Device Specific Initialization

This bit is set to 1 to indicate to the system that initialization of the DP83816 device is required (beyond the standard PCI configuration header) before the generic class device driver is able to use it. A 1 indicates that DP83816 requires a DSI sequence following transition to the D0 uninitialized state. This bit can be loaded from the EEPROM.

20 Reserved

(reads return 0)

19 PMEC PME Clock

Returns 0 to indicate PCI clock not needed for PMEN.

18-16 PMV Power Management Version

This bit field indicates compliance to a specific PM specification rev level. Currently set to 010b.

15-8 NLIPTR Next List Item Pointer

Offset into PCI configuration space for the location of the next item in the Capabilities Linked List. Returns 00h as no other capabilities are offered.

7-0 CAPID Capability ID

Always returns 01h for Power Management ID.

Max. Current Required

DP83816

4.1.12 Power Management Control and Status Register

This register contains PM control and status information.

Tag: PMCSR Size: 32 bits Hard Reset: 00000000h

Offset: 44h Access: Read Write Soft Reset: unchanged

Bit Bit Name Description

31-24 Reserved

(reads return 0)

23-16 BSE Bridge Support Extensions

unused (reads return 0)

15 PMESTS PME Status

Sticky bit which represents the state of the PME logic, regardless of the state of the PMEEN bit.

14-9 Reserved

(reads return 0)

8 PMEEN PME Enable

When set to 1, this bit enables the assertion of the PME function on the PMEN pin. When 0, the PMEN pin is forced to be inactive. This value can be loaded from the EEPROM.

7-2 Unused

(reads return 0)

1-0 PSTATE Power State

This 2 bit field is used to determine the current power state of DP83816, and to set a new power state.

00 - D0 10 - D2 01 - D1 11 - D3hot/cold

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4.0 Register Set (Continued)

4.2 Operational Registers

The DP83816 provides the following set of operational registers mapped into PCI memory space or I/O space. Writes to reserved register locations are ignored. Reads to reserved register locations return undefined values.

Table 4-2 Operational Register Map

Offset Tag Description Access

MAC/BIU Registers

00h CR Command Register R/W

04h CFG Configuration Register R/W

08h MEAR EEPROM Access Register R/W

0Ch PTSCR PCI Test Control Register R/W

10h ISR Interrupt Status Register RO

14h IMR Interrupt Mask Register R/W

18h IER Interrupt Enable Register R/W

1Ch IHR Interrupt Holdoff Register R/W

20h TXDP Transmit Descriptor Pointer Register R/W

24h TXCFG Transmit Configuration Register R/W

28-2Ch Reserved Reserved

30h RXDP Receive Descriptor Pointer Register R/W

34h RXCFG Receive Configuration Register R/W

38 Reserved Reserved

3Ch CCSR CLKRUN Control/Status Register R/W

40h WCSR Wake on LAN Control/Status Register R/W

44h PCR Pause Control/Status Register R/W

48h RFCR Receive Filter/Match Control Register R/W

4Ch RFDR Receive Filter/Match Data Register R/W

50h BRAR Boot ROM Address R/W

54h BRDR Boot ROM Data R/W

58h SRR Silicon Revision Register RO

5Ch MIBC Management Information Base Control Register R/W

60-78h MIB Management Information Base Data Registers RO

7Ch Reserved Reserved

Internal Phy Registers

80h BMCR Basic Mode Control Register R/W

84h BMSR Basic Mode Status Register RO

88h PHYIDR1 PHY Identifier Register #1 RO

8Ch PHYIDR2 PHY Identifier Register #2 RO

90h ANAR Auto-Negotiation Advertisement Register R/W

94h ANLPAR Auto-Negotiation Link Partner Ability Register R/W

98h ANER Auto-Negotiation Expansion Register R/W

9Ch ANNPTR Auto-Negotiation Next Page TX R/W

A0-BCh Reserved Reserved

C0h PHYSTS PHY Status Register RO

C4h MICR MII Interrupt Control Register R/W

C8h MISR MII Interrupt Status Register R/W

CCh Reserved Reserved

D0h FCSCR False Carrier Sense Counter Register R/W

D4h RECR Receive Error Counter Register R/W

D8h PCSR 100 Mb/s PCS Configuration and Status Register R/W

DCh-E0h Reserved Reserved

E4h PHYCR PHY Control Register R/W

E8h TBTSCR 10Base-T Status/Control Register R/W

ECh-FCh Reserved Reserved

DP83816

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4.0 Register Set (Continued)

4.2.1 Command Register

This register is used for issuing commands to DP83816. These commands are issued by setting the corresponding bits for the function. A global software reset along with individual reset and enable/disable for transmitter and receiver are provided here.

Tag: CR Size: 32 bits Hard Reset: 00000000h

Offset: 0000h Access: Read Write Soft Reset: 00000000h

Bit Bit Name Description

31-9 unused

8 RST Reset

Set to 1 to force the DP83816 to a soft reset state which disables the transmitter and receiver, reinitializes the FIFOs, and resets all affected registers to their soft reset state. This operation implies both a TXR and a RXR. This bit will read back a 1 during the reset operation, and be cleared to 0 by the hardware when the reset operation is complete. EEPROM configuration information is not loaded here.

7 SWI Software Interrupt

Setting this bit to a 1 forces the DP83816 to generate a hardware interrupt. This interrupt is mask-able via the IMR.

6 unused

5 RXR Receiver Reset

When set to a 1, this bit causes the current packet reception to be aborted, the receive data and status FIFOs to be flushed, and the receive state machine to enter the idle state (RXE goes to 0). This is a write-only bit and is always read back as 0.

4 TXR Transmit Reset

When set to a 1, this bit causes the current transmission to be aborted, the transmit data and status FIFOs to be flushed, and the transmit state machine to enter the idle state (TXE goes to 0). This is a write-only bit and is always read back as 0.

3 RXD Receiver Disable

Disable the receive state machine after any current packets in progress. When this operation has been completed the RXE bit will be cleared to 0. This is a write-only bit and is always read back as 0. The driver should not set both RXD and RXE in the same write, the RXE will be ignored, and RXD will have precedence.

2 RXE Receiver Enable

When set to a 1, and the receive state machine is idle, then the receive machine becomes active. This bit will read back as a 1 whenever the receive state machine is active. After initial power-up, software must insure that the receiver has completely reset before setting this bit (See ISR:RXRCMP).

1 TXD Transmit Disable

When set to a 1, halts the transmitter after the completion of the current packet. This is a write-only bit and is always read back as 0. The driver should not set both TXD and TXE in the same write, the TXE will be ignored, and TXD will have precedence.

0 TXE Transmit Enable

When set to a 1, and the transmit state machine is idle, then the transmit state machine becomes active. This bit will read back as a 1 whenever the transmit state machine is active. After initial power-up, software must insure that the transmitter has completely reset before setting this bit (See ISR:TXRCMP).

DP83816

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4.0 Register Set (Continued)

4.2.2 Configuration and Media Status Register

This register allows configuration of a variety of device and phy options, and provides phy status information.

Tag: CFG Size: 32 bits Hard Reset: 00000000h

Offset: 0004h Access: Read Write Soft Reset: 00000000h

Bit Bit Name Description

31 LNKSTS Link Status

Link status of the internal phy. Asserted when link is good. RO

30 SPEED100 Speed 100 Mb/s

Speed 100 Mb/s indicator for internal phy. Asserted when speed is set or has negotiated to 100 Mb/s. De-asserted when speed has been set or negotiated to 10 Mb/s. RO

29 FDUP Full Duplex

Full Duplex indicator for internal phy. Asserted when duplex mode is set or has negotiated to FULL. Deasserted when duplex mode has been set or negotiated to HALF. RO

28 POL 10 Mb/s Polarity Indication

Twisted pair polarity indicator for internal phy. Asserted when operating and 10 Mb/s and the polarity has been detected as reversed. De-asserted when polarity is normal or phy is operating at 100 Mb/s. RO

27 ANEG_DN Auto-negotiation Done

Auto-negotiation done indicator from internal phy. Asserted when auto-negotiation process has completed or is not active. RO

26-24 unused

23-18 PHY_CFG Phy Configuration

Miscellaneous internal phy Power-On-Reset configuration control bits.

17 PINT_ACEN Phy Interrupt Auto Clear Enable

When set to a 1, this bit allows the phy interrupt source to be automatically cleared whenever the ISR is read. When this bit is 0, the phy interrupt source must be manually cleared via access of the phy registers. R/W

16 PAUSE_ADV Pause Advertise

This bit is loaded from EEPROM at power-up and is used to configure the internal phy to advertise the capability of 802.3x pause during auto-negotiation. Setting this bit to 1 will cause the pause function to be advertised if the phy has also been configured to advertise full duplex capability (See ANEG_SEL). R/W

15-13 ANEG_SEL Auto-negotiation Select

These bits are loaded from EEPROM at power-up and are used to define the default state of the internal phy auto-negotiation logic. R/W These bits are encoded as follows:

000 Auto-negotiation disabled, force 10 Mb/s half duplex

010 Auto-negotiation disabled, force 100 Mb/s half duplex

100 Auto-negotiation disabled, force 10 Mb/s full duplex

110 Auto-negotiation disabled, force 100 Mb/s full duplex

001 Auto-negotiation enabled, advertise 10 Mb/s half & full duplex

011 Auto-negotiation enabled, advertise 10/100 Mb/s half duplex

101 Auto-negotiation enabled, advertise 100 Mb/s half & full duplex

111 Auto-negotiation enabled, advertise 10/100 Mb/s half & full duplex

12 EXT_PHY External Phy Support

Act as a stand-alone MAC. When set, this bit enables the MII and disables the internal Phy (sets bit 9). R/W

11 Reserved

DP83816

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4.0 Register Set (Continued)

Bit Bit Name Description

10 PHY_RST Reset internal Phy

Asserts reset to internal phy. Can be used to cause phy to reload options from the CFG register. This bit does not self clear when set. R/W

9 PHY_DIS Disable internal Phy

When set to a 1, this bit forces the internal phy to its low-power state. R/W

8 EUPHCOMP DP83810 Descriptor Compatibility

When set, DP83816 will use DP83810 compatible (but single fragment) descriptor format. Descriptors are four 32-bit words in length, but the fragment count field is ignored. When clear, DP83816 will only fetch 3 32-bit words in descriptor fetches with the third word being the fragment pointer. R/W

7 REQALG PCI Bus Request Algorithm

Selects mode for making requests for the PCI bus. When set to 0 (default), DP83816 will use an aggressive Request scheme. When set to a 1, DP83816 will use a more conservative scheme. R/W

6 SB Single Back-off

Setting this bit to 1 forces the transmitter back-off state machine to always back-off for a single 802.3 slot time instead of following the 802.3 random back-off algorithm. A 0 (default) allows normal transmitter back-off operation. R/W

5 POW Program Out of Window Timer

This bit controls when the Out of Window collision timer begins counting its 512 bit slot time. A 0 causes the timer to start after the SFD is received. A 1 causes the timer to start after the first bit of the preamble is received. R/W

4 EXD Excessive Deferral Timer disable

Setting this bit to 1 will inhibit transmit errors due to excessive deferral. This will inhibit the setting of the ED status, and the logging of the TxExcessiveDeferral MIB counter. R/W

3 PESEL Parity Error Detection Action

This bit controls the assertion of SERR when a data parity error is detected while the DP83816 is acting as the bus master. When set, parity errors will not result in the assertion of SERR. When reset, parity errors will result in the assertion of SERR, indicating a system error. This bit should be set to a one by software if the driver can handle recovery from and reporting of data parity errors. R/W

2 BROM_DIS Disable Boot ROM interface

When set to 1, this bit inhibits the operation of the Boot ROM interface logic. R/W

1 Reserved

(reads return 0)

0 BEM Big Endian Mode

When set, DP83816 will perform bus-mastered data transfers in “big endian” mode. Note that access to register space is unaffected by the setting of this bit. R/W

DP83816

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4.0 Register Set (Continued)

4.2.3 EEPROM Access Register

The EEPROM Access Register provides an interface for software access to the NMC9306 style EEPROM The default values given assume that the EEDO line has a pullup resistor to VDD.

Tag: MEAR Size: 32 bits Hard Reset: 00000002h

Offset: 0008h Access: Read Write Soft Reset: 00000002h

Bit Bit Name Description

31-7 unused

6 MDC MII Management Clock

Controls the value of the MDC pin. When set, the MDC pin is 1; when clear the MDC pin is 0. R/W

5 MDDIR MII Management Direction

Controls the direction of the MDIO pin. When set, DP83816 drives the MDIO pin. When clear MDIO bit reflects the current state of the MDIO pin. R/W

4 MDIO MII Management Data

Software access to the MDIO pin (see MDDIR above). R/W

3 EESEL EEPROM Chip Select

Controls the value of the EESEL pin. When set, the EESEL pin is 1; when clear the EESEL pin is 0. R/W

2 EECLK EEPROM Serial Clock

Controls the value of the EECLK pin. When set, the EECLK pin is 1; when clear the EECLK pin is 0. R/W

1 EEDO EEPROM Data Out

Returns the current state of the EEDO pin. When set, the EEDO pin is 1; when clear the EEDO pin is 0. RO

0 EEDI EEPROM Data In

Controls the value of the EEDI pin. R/W

DP83816

4.2.4 EEPROM Map

EEPROM

Address

0000h CFGSID[0:15] D008h

0001h CFGSID[16:31] 0400h

0002h CFGINT[24:31],CFGINT[16:23] 2CD0h

0003h CFGCS[20],PMCAP[31],PMCAP[21],PMCSR[8],

0004h SOPAS[1:16] 0000h

0005h SOPAS[17:32] 0000h

0006h SOPAS[33:47],PMATCH[0] 000Nh

0007h PMATCH[1:16] NNNNh

0008h PMATCH[17:32] NNNNh

0009h PMATCH[33:47],WCSR[0] NNNNh

000Ah WCSR[1:4],WCSR[9:10],RFCR[20],RFCR[22],

000Bh checksum value XX55

Configuration/Operation Register Bits

CFG[13:16],CFG[18:23],CR[2], SOPAS[0]

RFCR[27:31],000b (3 bits)

In the above table: N denotes the value is dependent on the ethernet MAC ID Number. X denotes the value is dependent on the checksum value.

Default Value

(16 bits)

CF82h

A098h

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4.0 Register Set (Continued)

PMATCH[47:0] can be accessed via the combination of the RFCR (offset 0048h) and RFDR (offset 004Ch) registers. PMATCH holds the Ethernet address info. See Section 3.3.3.

The lower 8 bits of the checksum value should be 55h. For the upper 8 bits, add the top 8 data bits to the lower 8 data bits for each address. Sum the resultant 8 bit values for all addresses and then add 55h. Take the 2’s complement of the final sum. This 2’s complement number should be the upper 8 bits of the checksum value in the last address.

As an example, consider an EEPROM with two addresses. EEPROM address 0000h contains the data 1234h. EEPROM address 0001h contains the data 5678h.

12h + 34h = 46h 56h + 78h = CEh 46h + CEh + 55h = 69h The 2’s complement of 69h is 97h so the checksum value entered into EEPROM address 0002h would be 9755h.

4.2.5 PCI Test Control Register

Tag: PTSCR Size: 32 bits Hard Reset: 00000000h

Offset: 000Ch Access: Read Write Soft Reset: 00000000h

DP83816

Bit Bit Name Description

31-13 unused

12 Reserved for NSC internal use only.

Must be written as a 0 otherwise. R/W

11 Reserved

10 RBIST_RST SRAM BIST Reset

Setting this bit to 1 allows the SRAM BIST engine to be reset. R/W

9-8 Reserved for NSC internal use only.

Must be written as a 00 otherwise. R/W

7 RBIST_EN SRAM BIST Enable

Setting this bit to 1 starts the SRAM BIST engine. R/W

6 RBIST_DONE SRAM BIST Done

This bit is set to one when the BIST has completed its current test. It is cleared when either the BIST is active or disabled. RO

5 RBIST_RXFAIL RX FIFO BIST Fail

This bit is set to 1 if the SRAM BIST detects a failure in the RX FIFO SRAM. RO

4 RBIST_TXFAIL TX FIFO Fail

This bit is set to 1 if the SRAM BIST detects a failure in the TX FIFO SRAM. RO

3 RBIST_RXFFAIL RX Filter RAM BIST Fail

This bit is set to 1 if the SRAM BIST detects a failure in the RX Filter SRAM. RO

2 EELOAD_EN Enable EEPROM Load

This bit is set to a 1 to manually initiate a load of configuration information from EEPROM. A 1 is returned while the configuration load from EEPROM is active (approx. 1500 us). R/W

1 EEBIST_EN Enable EEPROM BIST

This bit is set to a 1 to initiate EEPROM BIST, which verifies the EEPROM data and checksum without reloading configuration values to the device. A 1 is returned while the EEPROM BIST is active. R/W

0 EEBIST_FAIL EE BIST Fail indication

This bit is set to a 1 upon completion of the EEPROM BIST (EEBIST_EN returns 0) if the BIST logic encountered an invalid checksum. RO

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4.0 Register Set (Continued)

4.2.6 Interrupt Status Register

This register indicates the source of an interrupt when the INTA pin goes active. Enabling the corresponding bits in the Interrupt Mask Register (IMR) allows bits in this register to produce an interrupt. When an interrupt is active, one or more bits in this register are set to a “1”. The Interrupt Status Register reflects all current pending interrupts, regardless of the state of the corresponding mask bit in the IMR. Reading the ISR clears all interrupts. Writing to the ISR has no effect.

Tag: ISR Size: 32 bits Hard Reset: 03008000h

Offset: 0010h Access: Read Only Soft Reset: 03008000h

Bit Bit Name Description

31-26 Reserved

25 TXRCMP Transmit Reset Complete

Indicates that a requested transmit reset operation is complete.

24 RXRCMP Receive Reset Complete

Indicates that a requested receive reset operation is complete.

23 DPERR Detected Parity Error

This bit is set whenever CFGCS:DPERR is set, but cleared (like all other ISR bits) when the ISR register is read.

22 SSERR Signaled System Error

The DP83816 signaled a system error on the PCI bus.

21 RMABT Received Master Abort

The DP83816 received a master abort generated as a result of target not responding.

20 RTABT Received Target Abort

The DP83816 received a target abort on the PCI bus.

19-17 unused

16 RXSOVR Rx Status FIFO Overrun

Set when an overrun condition occurs on the Rx Status FIFO.

15 HIBERR High Bits Error Set

A logical OR of bits 25-16.

14 PHY Phy interrupt

Set to 1 when internal phy generates an interrupt.

13 PME Power Management Event

Set when WOL conditioned detected.

12 SWI Software Interrupt

Set whenever the SWI bit in the CR register is set.

11 MIB MIB Service

Set when one of the enabled management statistics has reached its interrupt threshold. (See Section 4.2.24)

10 TXURN Tx Underrun

Set when a transmit data FIFO underrun condition occurs.

9 TXIDLE Tx Idle

This event is signaled when the transmit state machine enters the idle state from a non-idle state. This will happen whenever the state machine encounters an "end-of-list" condition (NULL link field or a descriptor with OWN clear).

8 TXERR Tx Packet Error

This event is signaled after the last transmit descriptor in a failed transmission attempt has been updated with valid status.

DP83816

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4.0 Register Set (Continued)

Bit Bit Name Description

7 TXDESC Tx Descriptor

This event is signaled after a transmit descriptor when the INTR bit in the CMDSTS field has been updated.

6 TXOK Tx Packet OK

This event is signaled after the last transmit descriptor in a successful transmission attempt has been updated with valid status.

5 RXORN Rx Overrun

Set when a receive data FIFO overrun condition occurs.

4 RXIDLE Rx Idle

This event is signaled when the receive state machine enters the idle state from a running state. This will happen whenever the state machine encounters an "end-of-list" condition (NULL link field or a descriptor with OWN set).

3 RXEARLY Rx Early Threshold

Indicates that the initial Rx Drain Threshold has been met by the incoming packet, and the transfer of the number of bytes specified by the DRTH field in the RXCFG register has been completed by the receive DMA engine. This interrupt condition will occur only once per packet.

2 RXERR Rx Packet Error

This event is signaled after the last receive descriptor in a failed packet reception has been updated with valid status.

1 RXDESC Rx Descriptor

This event is signaled after a receive descriptor with the INTR bit set in the CMDSTS field has been updated.

0 RXOK Rx OK

Set by the receive state machine following the update of the last receive descriptor in a good packet.

DP83816

4.2.7 Interrupt Mask Register

This register masks the interrupts that can be generated from the ISR. Writing a “1” to the bit enables the corresponding interrupt. During a hardware reset, all mask bits are cleared. Setting a mask bit allows the corresponding bit in the ISR to cause an interrupt. ISR bits are always set to 1, however, if the condition is present, regardless of the state of the corresponding mask bit.

Tag: IMR Size: 32 bits Hard Reset: 00000000h

Offset: 0014h Access: Read Write Soft Reset: 00000000h

Bit Bit Name Description

31-26 unused

25 TXRCMP Transmit Reset Complete