National Semiconductor DAC121C081, DAC121C085 Technical data

March 13, 2008

DAC121C081/ DAC121C085 12-Bit Micro Power Digital-to-Analog Converter with an I2C-Compatible Interface

DAC121C081/ DAC121C085 12-Bit Micro Power Digital-to-Analog Converter

General Description

The DAC121C081 is a 12-bit, single channel, voltage-output digital-to-analog converter (DAC) that operates from a +2.7V to 5.5V supply. The output amplifier allows rail-to-rail output swing and has an 8.5µsec settling time. The DAC121C081 uses the supply voltage as the reference to provide the widest dynamic output range and typically consumes 132µA while operating at 5.0V. It is available in 6-lead TSOT and LLP packages and provides three address options (pin selectable).

As an alternative, the DAC121C085 provides nine I2C addressing options and uses an external reference. It has the same performance and settling time as the DAC121C081. It is available in an 8-lead MSOP.

The DAC121C081 and DAC121C085 use a 2-wire, I2C-compatible serial interface that operates in all three speed modes, including high speed mode (3.4MHz). An external address selection pin allows up to three DAC121C081 or nine DAC121C085 devices per 2-wire bus. Pin compatible alternatives to the DAC121C081 are available that provide additional address options.

The DAC121C081 and DAC121C085 each have a 16-bit register that controls the mode of operation, the power-down condition, and the output voltage. A power-on reset circuit ensures that the DAC output powers up to zero volts. A powerdown feature reduces power consumption to less than a microWatt. Their low power consumption and small packages make these DACs an excellent choice for use in battery operated equipment. Each DAC operates over the extended industrial temperature range of −40°C to +125°C.

The DAC121C081 and DAC121C085 are each part of a family of pin compatible DACs that also provide 8 and 10 bit resolution. For 8-bit DACs see the DAC081C081 and DAC081C085. For 10-bit DACs see the DAC101C081 and DAC101C085.

Features

Guaranteed Monotonicity to 12-bits

■

Low Power Operation: 156 µA max @ 3.3V

■

Extended power supply range (+2.7V to +5.5V)

■

I2C-Compatible 2-wire Interface which supports standard

■

(100kHz), fast (400kHz), and high speed (3.4MHz) modes Rail-to-Rail Voltage Output

■

Very Small Package

■

Key Specifications

Resolution 12 bits

■

INL ±8 LSB (max)

■

DNL +0.6 / -0.5 LSB (max)

■

Settling Time 8.5 µs (max)

■

Zero Code Error +10 mV (max)

■

Full-Scale Error −0.7 %FS (max)

■

Supply Power

■

Normal 380 µW (3V) / 730 µW (5V) typ

—

Power Down 0.5 µW (3V) / 0.9 µW (5V) typ

—

Applications

Industrial Process Control

■

Portable Instruments

■

Digital Gain and Offset Adjustment

■

Programmable Voltage & Current Sources

■

Test Equipment

■

Pin-Compatible Alternatives

All devices are fully pin and function compatible.

Resolution TSOT-6 and LLP-6

Packages

12-bit DAC121C081 DAC121C085

10-bit DAC101C081 DAC101C085

8-bit DAC081C081 DAC081C085

MSOP-8 Package w/

External Reference

Connection Diagrams

30004901 30004902

I2C® is a registered trademark of Phillips Corporation.

30004910

Ordering Information

Order Code Temperature Range Package Top Mark

DAC121C081CIMK

DAC121C081CIMKX

DAC121C081CISD

DAC121C081CISDX

DAC121C085CIMM

DAC121C081/ DAC121C085

DAC121C085CIMMX

DAC121C08XEB Evaluation Board

Block Diagram

−40°C ≤ TA ≤ +125°C

TSOT X84C

TSOT Tape-and-Reel X84C

LLP X87

LLP Tape-and-Reel X87

MSOP X90C

MSOP Tape-and-Reel X90C

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30004903

Pin Descriptions

Symbol Type Equivalent Circuit Description

V

OUT

V

A

GND Ground Ground for all on-chip circuitry.

SDA

SCL Digital Input

ADR0

Analog Output Analog Output Voltage.

Power supply input. For the TSOT and LLP versions, this

Supply

supply is used as the reference. Must be decoupled to GND.

Serial Data bi-directional connection. Data is clocked into

Digital

Input/Output

or out of the internal 16-bit register relative to the clock edges of SCL. This is an open drain data line that must be pulled to the supply (VA) by an external pull-up resistor.

Serial Clock Input. SCL is used together with SDA to control the transfer of data in and out of the device.

Digital Input,

three levels

Tri-state Address Selection Input. Sets the two Least Significant Bits (A1 & A0) of the 7-bit slave address. (see Table 1)

DAC121C081/ DAC121C085

ADR1

Digital Input,

three levels

Tri-state Address Selection Input. Sets Bits A6 & A3 of the 7-bit slave address. (see Table 1)

Unbufferred reference voltage. For the MSOP-8, this

V

REF

Supply

supply is used as the reference. V

must be free of noise

REF

and decoupled to GND.

Exposed die attach pad can be connected to ground or left

PAD

(LLP only)

Ground

floating. Soldering the pad to the PCB offers optimal thermal performance and enhances package selfalignment during reflow.

Package Pinouts

V

OUT

TSOT 1 2 3 4 5 6 N/A N/A N/A

LLP 6 5 4 3 2 1 N/A N/A 7

MSOP-8 8 6 5 4 3 1 2 7 N/A

V

A

GND SDA SCL ADR0 ADR1

V

REF

PAD (LLP only)

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Absolute Maximum Ratings

(Notes 1, 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage, V

A

−0.3V to +6.5V

Operating Ratings (Notes 1, 2)

Operating Temperature Range

Supply Voltage, V

Reference Voltage, V

A

REFIN

Digital Input Voltage (Note 7) 0.0V to 5.5V Output Load 0 to 1500 pF

−40°C ≤ TA ≤ +125°C

Voltage on any Input Pin −0.3V to +6.5V Input Current at Any Pin (Note 3) ±10 mA Package Input Current (Note 3) ±20 mA Power Consumption at TA = 25°C

DAC121C081/ DAC121C085

ESD Susceptibility (Note 5) VA, GND, V

REF

, V

OUT

, ADR0, ADR1 pins: Human Body Model Machine Model Charged Device Model (CDM) SDA, SCL pins: Human Body Model Machine Model Charged Device Model (CDM)

See (Note 4)

2500V

250V

1000V

5000V

350V

1000V

Package Thermal Resistances

Package

6-Lead TSOT 250°C/W

6-Lead LLP 190°C/W

8-Lead MSOP 240°C/W

Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6)

θ

JA

Junction Temperature +150°C Storage Temperature −65°C to +150°C

Electrical Characteristics

Values shown in this table are design targets and are subject to change before product release.

The following specifications apply for VA = +2.7V to +5.5V, V

limits apply for T

≤ TA ≤ T

MIN

and all other limits are at TA = 25°C, unless otherwise specified.

MAX

Symbol Parameter Conditions

STATIC PERFORMANCE

Resolution 12 Bits (min)

Monotonicity 12 Bits (min)

INL Integral Non-Linearity

DNL Differential Non-Linearity

I

OUT

= 0

ZE Zero Code Error

FSE Full-Scale Error

GE Gain Error All ones Loaded to DAC register −0.2 −0.7 %FSR (max)

ZCED Zero Code Error Drift −20 µV/°C

OUT

VA = 3V

VA = 5V

)

TC GE Gain Error Tempco

ANALOG OUTPUT CHARACTERISTICS (V

DAC121C085

Output Voltage Range(Note 10)

DAC121C081

ZCO Zero Code Output

FSO Full Scale Output

I

Output Short Circuit Current

OS

(I

SOURCE

)

VA = 3V, I

VA = 5V, I

VA = 3V, I

VA = 5V, I

VA = 3V, V

VA = 5V, V

= VA, CL = 200 pF to GND, input code range 48 to 4047. Boldface

REF

Typical

(Note 9)

Limits

(Note 9)

+2.2 +8 LSB (max)

−1.5 −8 LSB (min)

+0.18 +0.6 LSB (max)

−0.12 −0.5 LSB (min)

+1.1 +10 mV (max)

−0.1 −0.7 %FSR (max)

−0.7 ppm FSR/°C

−1.0 ppm FSR/°C

0

V

REF

0

V

A

= 200 µA

OUT

= 200 µA

OUT

= 200 µA

OUT

= 200 µA

OUT

= 0V, Input Code = FFFh.

OUT

= 0V, Input Code = FFFh.

OUT

1.3 mV

7.0 mV

2.984 V

4.989 V

56 mA

69 mA

+2.7V to 5.5V

+1.0V to V

Units

(Limits)

V (min)

V (max)

V (min)

V (max)

A

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DAC121C081/ DAC121C085

Symbol Parameter Conditions

I

C

Z

Output Short Circuit Current

OS

(I

)

SINK

Continuous Output

I

O

Current (Note 10)

Maximum Load Capacitance

L

DC Output Impedance 7.5

OUT

VA = 3V, V

VA = 5V, V

Available on the DAC output 11 mA (max)

RL = ∞

RL = 2kΩ

= 3V, Input Code = 000h.

OUT

= 5V, Input Code = 000h.

OUT

REFERENCE INPUT CHARACTERISTICS- (DAC121C085 only)

Input Range Minimum 0.2 1.0 V (min)

V

Input Range Maximum

REF

Input Impedance 120

LOGIC INPUT CHARACTERISTICS (SCL, SDA)

V

I

C

HYST

Input High Voltage

IH

Input Low Voltage

IL

Input Current ±1 µA (max)

IN

Input Pin Capacitance (Note 10) 3 pF (max)

IN

Input Hysteresis

LOGIC INPUT CHARACTERISTICS (ADR0, ADR1)

V

I

Input High Voltage

IH

Input Low Voltage 0.5 V (max)

IL

Input Current ±1 µA (max)

IN

LOGIC OUTPUT CHARACTERISTICS (SDA)

I

= 3 mA

V

I

Output Low Voltage

OL

High-Impedence Output

OZ

Leakage Current

SINK

I

= 6 mA

SINK

±1 µA (max)

Typical

(Note 9)

Limits

(Note 9)

(Limits)

−52 mA

−75 mA

1500 pF

V

A

0.7 x V

0.3 x V

0.1 x V

A

V (max)

VA- 0.5V

0.4 V (max)

0.6 V (max)

Units

Ω

kΩ

V (min)

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Symbol Parameter Conditions

Typical

(Note 9)

Limits

(Note 9)

POWER REQUIREMENTS

V

Normal -- V

I

ST_VA-1VA

I

ST_VA-5VA

DAC121C081/ DAC121C085

I

ST_VREF

P

Supply Voltage Minimum 2.7 V (min)

A

Supply Voltage Maximum 5.5 V (max)

set to midscale. 2-wire interface quiet (SCL = SDA = VA). (output unloaded)

OUT

DAC121C081 Supply Current

DAC121C085 Supply Current

V

REF

(DAC121C085 only)

Power Consumption

ST

(VA & V

Supply Current

for DAC121C085)

REF

VA = 2.7V to 3.6V

VA = 4.5V to 5.5V

VA = 2.7V to 3.6V

VA = 4.5V to 5.5V

VA = 2.7V to 3.6V

VA = 4.5V to 5.5V

VA = 3.0V

VA = 5.0V

105 156 µA (max)

132 214 µA (max)

86 118 µA (max)

98 152 µA (max)

37 43 µA (max)

53 61 µA (max)

380 µW

730 µW

Continuous Operation -- 2-wire interface actively addressing the DAC and writing to the DAC register. (output unloaded)

I

CO_VA-1VA

I

CO_VA-5VA

I

CO_VREF

P

CO

DAC121C081 Supply Current

DAC121C085 Supply Current

V

Supply Current

REF

(DAC121C085 only)

Power Consumption (VA & V

for DAC121C085)

REF

f

SCL

=400kHz

=3.4MHz

=400kHz

=3.4MHz

=400kHz

=3.4MHz

VA = 2.7V to 3.6V

VA = 4.5V to 5.5V

VA = 2.7V to 3.6V

VA = 4.5V to 5.5V

VA = 2.7V to 3.6V

VA = 4.5V to 5.5V

VA = 2.7V to 3.6V

VA = 4.5V to 5.5V

VA = 2.7V to 3.6V

VA = 4.5V to 5.5V

VA = 3.0V

VA = 5.0V

VA = 3.0V

VA = 5.0V

134 220 µA (max)

192 300 µA (max)

225 320 µA (max)

374 500 µA (max)

101 155 µA (max)

142 220 µA (max)

193 235 µA (max)

325 410 µA (max)

33.5 55 µA (max)

49.5 71.4 µA (max)

480 µW

1.06 mW

810 µW

2.06 mW

Power Down -- 2-wire interface quiet (SCL = SDA = VA) after PD mode written to DAC register. (output unloaded)

I

P

Supply Current

PD

(VA & V

Power Consumption

PD

(VA & V

for DAC121C085)

REF

for DAC121C085)

REF

All Power Down Modes

VA = 2.7V to 3.6V

VA = 4.5V to 5.5V

VA = 3.0V

VA = 5.0V

0.13 1.52 µA (max)

0.15 3.25 µA (max)

0.5 µW

0.9 µW

Units

(Limits)

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A.C. and Timing Characteristics

Values shown in this table are design targets and are subject to change before product release.

The following specifications apply for VA = +2.7V to +5.5V, V

for T

≤ TA ≤ T

MIN

and all other limits are at TA = 25°C, unless otherwise specified.

MAX

Symbol Parameter

t

s

Output Voltage Settling Time (Note 10)

400h to C00h code change

RL = 2kΩ, CL = 200 pF

SR Output Slew Rate 1 V/µs

Glitch Impulse Code change from 800h to 7FFh 12 nV-sec

Digital Feedthrough 0.5 nV-sec

V

Multiplying Bandwidth(Note 12)

Total Harmonic Distortion(Note 12)

t

WU

Wake-Up Time

= 2.5V ± 0.1Vpp

REF

V

= 2.5V ± 0.1Vpp

REF

input frequency = 10kHz

VA = 3V

VA = 5V

DIGITAL TIMING SPECS (SCL, SDA)

Standard Mode

f

SCL

Serial Clock Frequency

Fast Mode High Speed Mode, Cb = 100pF High Speed Mode, Cb = 400pF

Standard Mode

t

LOW

SCL Low Time

Fast Mode High Speed Mode, Cb = 100pF High Speed Mode, Cb = 400pF

Standard Mode

t

HIGH

SCL High Time

Fast Mode High Speed Mode, Cb = 100pF High Speed Mode, Cb = 400pF

Standard Mode

t

SU;DAT

Data Setup Time

Fast Mode High Speed Mode

Standard Mode

Fast Mode

t

HD;DAT

Data Hold Time

High Speed Mode, Cb = 100pF

High Speed Mode, Cb = 400pF

Standard Mode Fast Mode High Speed Mode

Standard Mode Fast Mode

t

SU;STA

t

HD;STA

t

BUF

Setup time for a start or a repeated start condition

Hold time for a start or a repeated start condition

Bus free time between a stop and start condition

Standard Mode

t

SU;STO

Setup time for a stop condition

Fast Mode High Speed Mode

= VA, RL = Infinity, CL = 200 pF to GND. Boldface limits apply

REF

Limits

(Notes 9,

13)

Conditions (Note 13)

Typical

(Note 9)

6 8.5 µs (max)

160 kHz

70 dB

0.8 µsec

0.5 µsec

100 400

3.4

1.7

4.7

1.3 160 320

4.0

0.6

60

120

250 100

10

0

3.45

0

0.9

0

70

0

150

4.7

0.6 160

4.0

0.6 160

4.7

1.3

4.0

0.6 160

Units

(Limits)

kHz (max)

kHz (max) MHz (max) MHz (max)

µs (min) µs (min) ns (min) ns (min)

ns (min) ns (min) ns (min)

µs (min)

µs (max)

µs (min)

µs (max)

ns (min)

ns (max)

ns (min)

ns (max)

µs (min) µs (min) ns (min)

µs (min) µs (min)

µs (min) µs (min) ns (min)

DAC121C081/ DAC121C085

7 www.national.com

Symbol Parameter

t

rDA

Rise time of SDA signal

DAC121C081/ DAC121C085

t

C

t

fDA

rCL

rCL1

fCL

b

SP

outz

Fall time of SDA signal

Rise time of SCL signal

Rise time of SCL signal after a repeated start condition and after an acknowledge bit.

Fall time of a SCL signal

Capacitive load for each bus line (SCL and SDA)

Pulse Width of spike suppressed (Notes 11, 10)

SDA output delay (see Section 1.9)

Limits

(Notes 9,

13)

Units

(Limits)

Conditions (Note 13)

Typical

(Note 9)

Standard Mode 1000 ns (max)

Fast Mode

High Speed Mode, Cb = 100pF

High Speed Mode, Cb = 400pF

20+0.1C

300

10 80

20

160

b

ns (min)

ns (max)

ns (min)

ns (max)

ns (min)

ns (max)

Standard Mode 250 ns (max)

Fast Mode

High Speed Mode, Cb = 100pF

High Speed Mode, Cb = 400pF

20+0.1C

250

10 80

20

160

b

ns (min)

ns (max)

ns (min)

ns (max)

ns (min)

ns (max)

Standard Mode 1000 ns (max)

Fast Mode

High Speed Mode, Cb = 100pF

High Speed Mode, Cb = 400pF

20+0.1C

300

10 40

20 80

b

ns (min)

ns (max)

ns (min)

ns (max)

ns (min)

ns (max)

Standard Mode 1000 ns (max)

Fast Mode

High Speed Mode, Cb = 100pF

High Speed Mode, Cb = 400pF

20+0.1C

300

10 80

20

160

b

ns (min)

ns (max)

ns (min)

ns (max)

ns (min)

ns (max)

Standard Mode 300 ns (max)

Fast Mode

High Speed Mode, Cb = 100pF

High Speed Mode, Cb = 400pF

20+0.1C

300

10 40

20 80

b

ns (min)

ns (max)

ns (min)

ns (max)

ns (min)

ns (max)

400 pF (max)

Fast Mode High Speed Mode

87 38

50 10

270

60

ns (max) ns (max)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.

Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited to 10 mA. The 20 mA maximum package

input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.

Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).

Note 5: Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged through 0 Ω. Charge device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.

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