National Semiconductor DAC1218, DAC1219 Technical data

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DAC1218/DAC1219 12-Bit Binary Multiplying D/A Converter

General Description

The DAC1218 and the DAC1219 are 12-bit binary, 4-quadrant multiplying D to A converters. The linearity, differential non-linearity and monotonicity specifications for these converters are all guaranteed over temperature. In addition, these parameters are specified with standard zero and fullscale adjustment procedures as opposed to the impractical best fit straight line guarantee.

This level of precision is achieved though the use of an advanced silicon-chromium (SiCr) R-2R resistor ladder network. This type of thin-film resistor eliminates the parasitic diode problems associated with diffused resistors and allows the applied reference voltage to range from 25V, independent of the logic supply voltage.

CMOS current switches and drive circuitry are used to achieve low power consumption (20 mW typical) and minimize output leakage current errors (10 nA maximum). Unique digital input circuitry maintains TTL compatible input threshold voltages over the full operating supply voltage range.

The DAC1218 and DAC1219 are direct replacements for the AD7541 series, AD7521 series, and AD7531 series with a significant improvement in the linearity specification. In applications where direct interface of the D to A converter to

25V to

December 1994

a microprocessor bus is desirable, the DAC1208 and DAC1230 series eliminate the need for additional interface logic.

Features

Linearity specified with zero and full-scale adjust only

Logic inputs which meet TTL voltage level specs (1.4V logic threshold)

Works withg10V referenceÐfull 4-quadrant multiplication

All parts guaranteed 12-bit monotonic

Key Specifications

Current Settling Time 1 ms

Resolution 12 Bits

Linearity (Guaranteed 12 Bits (DAC1218) over temperature) 11 Bits (DAC1219)

Gain Tempco 1.5 ppm/§C

Low Power Dissipation 20 mW

Single Power Supply 5 VDCto 15 V

DAC1218/DAC1219 12-Bit Binary Multiplying D/A Converter

Typical Application

Connection Diagram

Dual-In-Line Package

OUT

REF

where: ANe1 if digital input is high

0 if digital input is low

A12

...

4096

TL/H/5691– 1

TL/H/5691– 15

Top View

Ordering Information

Temperature Range 0§Ctoa70§C

Non 0.012% DAC1218LCJ-1 DAC1218LCJ J18A Cerdip

Linearity

BI-FETTMis a trademark of National Semiconductor Corp.

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

0.024% DAC1219LCJ J18A Cerdip

TL/H/5691

40§Ctoa85§C Package Outline

Absolute Maximum Ratings (Notes 1 and 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Supply Voltage (V

Voltage at Any Digital Input VCCto GND

Voltage at V

Storage Temperature Range

Package Dissipation at T

DC Voltage Applied to I

)17V

REF

Input

25§C (Note 3) 500 mW

or I

OUT1

OUT2

65§Ctoa150§C

100 mV to V

25V

Operating Conditions

Temperature Range T

DAC1218LCJ, DAC1219LCJ

40§CsT

MIN

DAC1218LCJ-1 0

Range of V

Voltage at Any Digital Input VCCto GND

CsT

5VDCto 16 V

(Note 4)

Lead Temp. (Soldering, 10 seconds) 300§C

ESD Susceptibility (Note 11) 800V

Electrical Characteristics

10.000 VDC,V

REF

Note 9); all other limits T

Parameter Conditions Notes

Resolution 12 12 12 Bits

Linearity Error Zero and Full-Scale 4, 5, 9 (End Point Linearity) Adjusted

Differential Non-Linearity Zero and Full-Scale 4, 5, 9

Monotonicity 4 12 12 12 Bits

Gain Error (Min) Using Internal RFb,5

Gain Error (Max)

Gain Error Tempco 5

Power Supply Rejection All Digital Inputs High 5

Reference Input Resistance (Min) 9 15 10 10 kX

Output Feedthrough Error V

Output Capacitance All Data Inputs I

Supply Current Drain 9 2.0 2.5 mA

Output Leakage Current 7, 9

OUT1

OUT2

Digital Input Threshold Low Threshold 9 0.8 0.8 V

Digital Input Currents Digital Inputsk0.8V 9

tsCurrent Settling Time R

11.4 VDCto 15.75 VDCunless otherwise noted. Boldface limits apply from T

25§C.

DAC1218 DAC1219

Typ

(Note 10)

Tested Design

Limit Limit Units

(Note 11) (Note 12)

0.018g0.018 %ofFSR

0.024g0.024 %ofFSR

Adjusted

DAC1218 DAC1219

REF

10V,g1V

0.1 0.0 % of FSR

0.1

1.3

3.0

0.018g0.018 %ofFSR

0.024g0.024 %ofFSR

0.2 % of FSR

6.0 ppm of FS/§C

30 ppm of FSR/V

(Max) 9 15 20 20 kX

120 Vp-p, fe100 kHz 6 3.0 mVp-p

REF

All Data Inputs Low

High I All Data Inputs I Low I

OUT1

OUT2

OUT1

OUT2

200 pF

70 pF 70 pF

200 pF

All Data Inputs Low 10 10 nA All Data Inputs High 10 10 nA

High Threshold 2.2 2.2 V

200

200 mA

Digital Inputsl2.2V 10 10 mA

100X, Output Settled

to 0.01%, All Digital Inputs 1 ms Switched Simultaneously

MIN

to T

MAX

85§C 70§C

(see

MAX

Electrical Characteristics Notes

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating

the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified.

Note 3: This 500 mW specification applies for all packages. The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify

the power dissipation) removes concern for heat sinking.

Note 4: Both I example, if V

Note 5: The unit FSR stands for full-scale range. Linearity Error and Power Supply Rejection specs are based on this unit to eliminate dependence on a particular V

value to indicate the true performance of the part. The Linearity Error specification of the DAC1218 is 0.012% of FSR. This guarantees that after performing a

REF

zero and full-scale adjustment, the plot of the 4096 analog voltage outputs will each be within 0.012% scale. The unit ppm of FSR (parts per million of full-scale range) and ppm of FS (parts per million of full-scale) are used for convenience to define specs of very small percentage values, typical of higher accuracy converters. 1 ppm of FSR example, the gain error tempco spec of

(6)(V

REF

Note 6: To achieve this low feedthrough in the D package, the user must ground the metal lid. If the lid is left floating the feedthrough is typically 6 mV.

Note 7: A 10 nA leakage current with R

Note 8: Human body model, 100 pF discharged through 1.5 kX resistor.

Note 9: Tested limit for

Note 10: Typicals are at 25

Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 12: Design limits are guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels.

and I

OUT1

REF

/106)(125§C) org0.75 (10

must go to ground or the virtual ground of an operational amplifier. The linearity error is degraded by approximately V

OUT2

10Vthena1mVoffset, VOS,onI

1 suffix parts applies only at 25§C.

C and represent the most likely parametric norm.

or I

OUT1

6 ppm of FS/§C represents a worst-case full-scale gain error change with temperature fromb40§Ctoa85§Cof

which isg0.075% of V

REF

20k and V

REF

will introduce an additional 0.01% linearity error.

OUT2

/106is the conversion factor to provide an actual output voltage quantity. For

REF

10V corresponds to a zero error of (10c10

of a straight line which passes through zero and full-

REF

20c103)c100% 10V or 0.002% of FS.

. For

REF

Typical Performance Characteristics

Digital Input Threshold vs V

Gain and Linearity Error Variation vs Temperature

Digital Input Threshold vs Temperature

Gain and Linearity Error Variation vs Supply Voltage

TL/H/5691– 2

Definition of Package Pinouts

(A1–A12): Digital Inputs. A12 is the least significant digital

input (LSB) and A1 is the most significant digital input (MSB).

: DAC Current Output 1. I

OUT1

digital input of all 1s, and is zero for a digital input of all 0s.

: DAC Current Output 2. I

OUT2

,orI

OUT1

voltage).

: Feedback Resistor. The feedback resistor is provided

on the IC chip for use as the shunt feedback resistor for the

OUT1

constant (for a fixed reference

OUT2

is a maximum for a

OUT1

is a constant minus

OUT2

external op amp which is used to provide an output voltage for the DAC. This on-chip resistor should always be used (not an external resistor) since it matches the resistors in the on-chip R-2R ladder and tracks these resistors over temperature.

: Reference Voltage Input. This input connects to an

REF

external precision voltage source to the internal R-2R ladder. V This is also the analog voltage input for a 4-quadrant multi-

can be selected over the range of 10V tob10V.

REF

plying DAC application.

: Digital Supply Voltage. This is the power supply pin for

the part. V optimum for 15 V

can be from 5 VDCto 15 VDC. Operation is

GND: Ground. This is the ground for the circuit.

Definition of Terms

Resolution: Resolution is defined as the reciprocal of the

number of discrete steps in the DAC output. It is directly related to the number of switches or bits within the DAC. For example, the DAC1218 has 2 has 12-bit resolution.

Linearity Error: Linearity error in the maximum deviation from a

straight line passing through the endpoints of the

or 4096 steps and therefore

DAC transfer characteristic.

It is measured after adjusting for zero and full scale. Linearity error is a parameter intrinsic to the device and cannot be externally adjusted.

National’s linearity test (a) and the best straight line test (b) used by other suppliers are illustrated below. The best straight line (b) requires a special zero and FS adjustment for each part, which is almost impossible for the user to determine. The end point test uses a standard zero FS adjustment procedure and is a much more stringent test for DAC linearity.

Power Supply Sensitivity: Power supply sensitivity is a measure of the effect of power supply changes on the DAC full-scale output.

Settling Time: Full-scale current settling time requires zero to full-scale or full-scale to zero output change. Settling time is the time required from a code transition until the DAC output reaches within

1/2 LSB of the final output value.

Full-scale Error: Full-scale error is a measure of the output error between an ideal DAC and the actual device output. Ideally, for the DAC1218 full-scale is V

10V and unipolar operation, V

REF

10.0000Vb2.44 mVe9.9976V. Full-scale error is

SCALE

adjustable to zero.

REF

1 LSB. For

FULL-

Differential Non-Linearity: The difference between any two consecutive codes in the transfer curve from the theoretical 1 LSB is differential non-linearity.

Monotonic: If the output of a DAC increases for increasing digital input code, then the DAC is monotonic. A 12-bit DAC which is monotonic to 12 bits simply means that input increasing digital input codes will produce an increasing analog output.

a) End point test after zero and FS adjust b) Shifting FS adjust to pass best straight line test

TL/H/5691– 3

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