National Semiconductor DAC101S101 Technical data

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DAC101S101 10-Bit Micro Power Digital-to-Analog Converter with Rail-to-Rail Output

June 2005

General Description

The DAC101S101 is a full-featured, general purpose 10-bit voltage-output digital-to-analog converter (DAC) that can operate from a single +2.7V to 5.5V supply and consumes just 175 µA of current at 3.6 Volts. The on-chip output amplifier allows rail-to-rail output swing and the three wire serial interface operates at clock rates up to 30 MHz over the specified supply voltage range and is compatible with standard SPI petitive devices are limited to 20 MHz clock rates at supply voltages in the 2.7V to 3.6V range.

The supply voltage for the DAC101S101 serves as its voltage reference, providing the widest possible output dynamic range. A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a microWatt.

The low power consumption and small packages of the DAC101S101 make it an excellent choice for use in battery operated equipment.

The DAC101S101 is a direct replacement for the AD5310 and is one of a family of pin compatible DACs, including the 8-bit DAC081S101 and the 12-bit DAC121S101. The DAC101S101 operates over the extended industrial temperature range of −40˚C to +105˚C.

™

, QSPI, MICROWIRE and DSP interfaces. Com-

Features

n Guaranteed Monotonicity n Low Power Operation n Rail-to-Rail Voltage Output n Power-on Reset to Zero Volts Output n SYNC Interrupt Facility n Wide power supply range (+2.7V to +5.5V) n Small Packages n Power Down Feature

Key Specifications

n Resolution 10 bits n DNL +0.15, -0.05 LSB (typ) n Output Settling Time 8 µs (typ) n Zero Code Error 3.3 mV (typ) n Full-Scale Error −0.06 %FS (typ) n Power Consumption

— Normal Mode 0.63 mW (3.6V) / 1.41 mW (5.5V) typ — Pwr Down Mode 0.14 µW (3.6V) / 0.33 µW (5.5V) typ

Applications

n Battery-Powered Instruments n Digital Gain and Offset Adjustment n Programmable Voltage & Current Sources n Programmable Attenuators

Pin Configuration

20154101

20154102

Ordering Information

Order Numbers Temperature Range Package Top Mark

DAC101S101CIMM −40˚C ≤ T

DAC101S101CIMMX −40˚C ≤ T

DAC101S101CIMK −40˚C ≤ T

DAC101S101CIMKX −40˚C ≤ T

DAC101S101EVAL Evaluation Board

SPI™is a trademark of Motorola, Inc.

≤ +105˚C MSOP X62C

≤ +105˚C MSOP Tape-and-Reel X62C

≤ +105˚C TSOT X63C

≤ +105˚C TSOT Tape-and-Reel X63C

Block Diagram

DAC101S101

20154103

Pin Descriptions

TSOT

(SOT-23)

Pin No.

14V

2 8 GND Ground reference for all on-chip circuitry.

31V

47D

5 6 SCLK

6 5 SYNC

MSOP

Pin No.

2, 3 NC

Symbol Description

OUT

DAC Analog Output Voltage.

Power supply and Reference input. Should be decoupled to GND.

Serial Data Input. Data is clocked into the 16-bit shift

Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin.

Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.

No Connect. There is no internal connection to these pins.

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DAC101S101

Absolute Maximum Ratings

Storage Temperature −65˚C to +150˚C

(Notes 1, 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

+ 0.3V)

6.5V

Supply Voltage, V

Voltage on any Input Pin −0.3V to (V

Input Current at Any Pin (Note 3) 10 mA

Package Input Current (Note 3) 20 mA

Power Consumption at T

= 25˚C See (Note 4)

ESD Susceptibility (Note 5) Human Body Model Machine Model

2500V

250V

Soldering Temperature, Infrared,

Operating Ratings (Notes 1, 2)

Operating Temperature Range −40˚C ≤ T

Supply Voltage, V

Any Input Voltage (Note 7) −0.1 V to (V

Output Load 0 to 1500 pF

SCLK Frequency Up to 30 MHz

≤ +105˚C

+2.7V to 5.5V

+ 0.1 V)

Package Thermal Resistances

Package θ

8-Lead MSOP 240˚C/W

6-Lead TSOT 250˚C/W

10 Seconds (Note 6) 235˚C

Electrical Characteristics

Values shown in this table are design targets and are subject to change before product release. The following specifica-

tions apply for V

Boldface limits apply for T

= +2.7V to +5.5V, RL=2kΩ to GND, CL= 200 pF to GND, f

MIN

≤ TA≤ T

: all other limits TA= 25˚C, unless otherwise specified.

MAX

Symbol Parameter Conditions

STATIC PERFORMANCE

Resolution 10 Bits (min)

Monotonicity 10 Bits (min)

INL Integral Non-Linearity Over Decimal codes 12 to 1011

= 2.7V to 5.5V +0.15 +0.35 LSB (max)

DNL Differential Non-Linearity

ZE Zero Code Error I

FSE Full-Scale Error I

= 0 +3.3 +15 mV (max)

OUT

= 0 −0.06 −1.0

OUT

GE Gain Error All ones Loaded to DAC register −0.10

ZCED Zero Code Error Drift −20 µV/˚C

= 3V −0.7 ppm/˚C

TC GE Gain Error Tempco

= 5V −1.0 ppm/˚C

OUTPUT CHARACTERISTICS

Output Voltage Range (Note 10)

ZCO Zero Code Output

FSO Full Scale Output

Maximum Load Capacitance

= 3V, I

= 5V, I

= 3V, I

= 5V, I

∞

=2kΩ 1500 pF

= 10 µA 1.8 mV

OUT

= 100 µA 5.0 mV

OUT

= 10 µA 3.7 mV

OUT

= 100 µA 5.4 mV

OUT

= 10 µA 2.997 V

OUT

= 100 µA 2.990 V

OUT

= 10 µA 4.995 V

OUT

= 100 µA 4.992 V

OUT

DC Output Impedance 1.3 Ohm

= 30 MHz, input code range 12 to 1011.

SCLK

Typical

(Note 9)

0.6

Limits

(Note 9)

2.8 LSB (max)

−0.05 −0.2 LSB (min)

1.0

1500 pF

Units

(Limits)

%FSR

(max)

%FSR

(max)

V (min)

V (max)

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Electrical Characteristics (Continued)

Values shown in this table are design targets and are subject to change before product release. The following specifica-

tions apply for V

Boldface limits apply for T

= +2.7V to +5.5V, RL=2kΩ to GND, CL= 200 pF to GND, f

MIN

≤ TA≤ T

: all other limits TA= 25˚C, unless otherwise specified.

MAX

DAC101S101

Symbol Parameter Conditions

= 5V, V

Input code = 3FFh

VA= 3V, V

Output Short Circuit Current

LOGIC INPUT

Input Current (Note 10)

Input Low Voltage (Note 10)

Input High Voltage (Note 10)

Input Capacitance (Note 10) 3 pF (max)

POWER REQUIREMENTS

OUT/IA

Supply Current (output unloaded)

Power Consumption (output unloaded)

Power Efficiency I

Input code = 3FFh

VA= 5V, V Input code = 000h

= 3V, V

Input code = 000h

=5V 0.8 V (max)

=3V 0.5 V (max)

=5V 2.4 V (min)

=3V 2.1 V (min)

Normal Mode

=30MHz

SCLK

Normal Mode

=20MHz

SCLK

Normal Mode

SCLK

All PD Modes,

=30MHz

SCLK

All PD Modes,

=20MHz

SCLK

All PD Modes,

= 0 (Note 10)

SCLK

Normal Mode

=30MHz

SCLK

Normal Mode

=20MHz

SCLK

Normal Mode

SCLK

All PD Modes,

=30MHz

SCLK

All PD Modes,

=20MHz

SCLK

All PD Modes,

= 0 (Note 10)

SCLK

= 2mA

LOAD

OUT

= 0V,

= 5V,

= 3V,

= 5.5V 256 332 µA (max)

= 3.6V 174 226 µA (max)

= 5.5V 221 297 µA (max)

= 3.6V 154 207 µA (max)

= 5.5V 145 µA (max)

= 3.6V 113 µA (max)

= 5.0V 83 µA (max)

= 3.0V 42 µA (max)

= 5.0V 56 µA (max)

= 3.0V 28 µA (max)

= 5.5V 0.06 1.0 µA (max)

= 3.6V 0.04 1.0 µA (max)

= 5.5V 1.41 1.83 mW (max)

= 3.6V 0.63 0.81 mW (max)

= 5.5V 1.22 1.63 mW (max)

= 3.6V 0.55 0.74 mW (max)

= 5.5V 0.80 µW (max)

= 3.6V 0.41 µW (max)

= 5.0V 0.42 µW (max)

= 3.0V 0.13 µW (max)

= 5.0V 0.28 µW (max)

= 3.0V 0.08 µW (max)

= 5.5V 0.33 5.5 µW (max)

= 3.6V 0.14 3.6 µW (max)

=5V 91 %

=3V 94 %

= 30 MHz, input code range 12 to 1011.

SCLK

Typical

(Note 9)

Limits

(Note 9)

−63 mA

−50 mA

74 mA

53 mA

1 µA (max)

Units

(Limits)

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A.C. and Timing Characteristics

Values shown in this table are design targets and are subject to change before product release. The following specifica-

tions apply for V

Boldface limits apply for T

= +2.7V to +5.5V, RL=2kΩ to GND, CL= 200 pF to GND, f

MIN

≤ TA≤ T

: all other limits TA= 25˚C, unless otherwise specified.

MAX

Symbol Parameter Conductions Typical Limits

SCLK

SCLK Frequency 30 MHz (max)

Output Voltage Settling Time (Note 10)

100h to 300h code change, R

=2kΩ

≤ 200 pF 5 7.5 µs (max)

SR Output Slew Rate 1 V/µs

Glitch Impulse Code change from 200h to 1FFh 12 nV-sec

Digital Feedthrough 0.5 nV-sec

= 5V 1.6 µs

1/f

SCLK

SUCL

SUD

DHD

SYNC

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified

Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than V

mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.

Note 4: The absolute maximum junction temperature (T junction-to-ambient thermal resistance (θ for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.

Note 6: See the section entitled "Surface Mount" found in any post 1986 National Semiconductor Linear Data Book for methods of soldering surface mount devices.

Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to V

However, errors in the conversion result can occur if any input goes above V ≤ input voltages ≤2.8V

Wake-Up Time

SCLK Cycle Time 33 ns (min)

SCLK High time 5 13 ns (min)

SCLK Low Time 5 13 ns (min)

Set-up Time SYNC to SCLK Rising Edge

Data Set-Up Time 2.5 5 ns (min)

Data Hold Time 2.5 4.5 ns (min)

SCLK fall to rise of SYNC

SYNC High Time

), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values

to ensure accurate conversions.

= 3V 1.9 µs

VA=5V 0 3 ns (min)

=3V −2 1 ns (min)

2.7 ≤ VA≤ 3.6 9 20 ns (min)

3.6 ≤ V

max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the

≤ 5.5 5 10 ns (min)

+ 300 mV or to 300 mV below GND will not damage this device.

or below GND by more than 100 mV. For example, if VAis 2.7VDC, ensure that −100mV

= 30 MHz, input code range 12 to 1011.

SCLK

−15 0 ns (min)

), the current at that pin should be limited to 10

Units

(Limits)

DAC101S101

20154104

Note 8: To guarantee accuracy, it is required that VAbe well bypassed.

Note 9: Typical figures are at T

Level).

Note 10: This parameter is guaranteed by design and/or characterization and is not tested in production.

= 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality

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Specification Definitions

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB, which is V

DAC101S101

DIGITAL FEEDTHROUGH is a measure of the energy in-

jected into the analog output of the DAC from the digital inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus.

FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (3FFh) loaded into the DAC and the value of V

GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and FullScale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error.

GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register changes. It is specified as the area of the glitch in nanovolt-seconds.

INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line through the input to output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The end point method is used. INL for this product is specified over a limited range, per the Electrical Tables.

LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is

/1024=VA/ 1024.

REF

x 1023 / 1024.

REF

where V

LSB=V

is the supply voltage for this product, and "n" is

REF

the DAC resolution in bits, which is 10 for the DAC101S101. MAXIMUM LOAD CAPACITANCE is the maximum capaci-

tance that can be driven by the DAC with output stability maintained.

MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when the input code increases.

MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is 1/2 of

POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from the power supply. The difference between the supply and output currents, is the power consumed by the device without a load.

SETTLING TIME is the time for the output to settle within 1/2 LSB of the final value after the input code is updated.

WAKE-UP TIME is the time for the output to settle to within 1/2 LSB of the final value after the device is commanded to the active mode from any of the power down modes.

ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been entered.

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