National Semiconductor DAC0830, DAC0832 Technical data

May 1999

DAC0830/DAC0832 8-Bit µP Compatible, Double-Buffered D to A Converters

General Description

The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying DAC designed to interface directly with the 8080, 8048, 8085, Z80 silicon-chromium R-2R resistor ladder network divides the reference current and provides the circuit with excellent temperature tracking characteristics (0.05%of Full Scale Range maximum linearity error over temperature). The circuit uses CMOS current switches and control logic to achieve low power consumption and low output leakage current errors. Special circuitry provides TTL logic input voltage level compatibility.

Double buffering allows these DACs to output a voltage corresponding to one digital word while holding the next digital word. This permits the simultaneous updating of any number of DACs.

The DAC0830 series are the 8-bit members of a family of microprocessor-compatible DACs (MICRO-DAC

, andother popular microprocessors.Adeposited

™

Typical Application

Features

n Double-buffered, single-buffered or flow-through digital

data inputs

n Easy interchange and pin-compatible with 12-bit

DAC1230 series

n Direct interface to all popular microprocessors n Linearity specified with zero and full scale adjust

only—NOT BEST STRAIGHT LINE FIT.

n Works with n Can be used in the voltage switching mode n Logic inputs which meet TTL voltage level specs (1.4V

logic threshold)

n Operates “STAND ALONE” (without µP) if desired n Available in 20-pin small-outline or molded chip carrier

package

10V reference-full 4-quadrant multiplication

Key Specifications

n Current settling time: 1 µs n Resolution: 8 bits n Linearity: 8, 9, or 10 bits (guaranteed over temp.) n Gain Tempco: 0.0002%FS/˚C n Low power dissipation: 20 mW n Single power supply: 5 to 15 V

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BI-FET™and MICRO-DAC™are trademarks of National Semiconductor Corporation.

Z80

is a registered trademark of Zilog Corporation.

Connection Diagrams (Top Views)

Dual-In-Line and

Small-Outline Packages

Molded Chip Carrier Package

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Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage (V Voltage at Any Digital Input VCCto GND Voltage at V Storage Temperature Range −65˚C to +150˚C Package Dissipation

25˚C (Note 3) 500 mW

at T

DC Voltage Applied to

or I

OUT1

ESD Susceptability (Note 4) 800V

)17V

Input

REF

(Note 4) −100 mV to V

OUT2

25V

Lead Temperature (Soldering, 10 sec.)

Dual-In-Line Package (plastic) 260˚C Dual-In-Line Package (ceramic) 300˚C Surface Mount Package

Vapor Phase (60 sec.) 215˚C Infrared (15 sec.) 220˚C

Operating Conditions

Temperature Range T

Part numbers with “LCN” suffix 0˚C to +70˚C Part numbers with “LCWM” suffix 0˚C to +70˚C

Part numbers with “LCV” suffix 0˚C to +70˚C Part numbers with “LCJ” suffix −40˚C to +85˚C

MIN≤TA≤TMAX

Part numbers with “LJ” suffix −55˚C to +125˚C

Voltage at Any Digital Input V

to GND

Electrical Characteristics

10.000 V

REF

25˚C.

Parameter Conditions

CONVERTER CHARACTERISTICS

Resolution 88 8 bits Linearity Error Max Zero and full scale adjusted 4, 8

DAC0830LJ & LCJ 0.05 0.05 DAC0832LJ & LCJ 0.2 0.2 DAC0830LCN, LCWM &

LCV DAC0831LCN 0.1 0.1 DAC0832LCN, LCWM &

LCV Differential Nonlinearity Zero and full scale adjusted 4, 8

Max −10V≤V DAC0830LJ & LCJ 0.1 0.1 DAC0832LJ & LCJ 0.4 0.4 DAC0830LCN, LCWM &

LCV DAC0831LCN 0.2 0.2 DAC0832LCN, LCWM &

LCV Monotonicity −10V≤V

Gain Error Max Using Internal R

Gain Error Tempco Max Using internal R

Power Supply Rejection All digital inputs latched high

Reference Max 15 20 20 kΩ Input Min 15 10 10 kΩ Output Feedthrough Error V

unless otherwise noted. Boldface limits apply over temperature, T

See

Note

−10V≤V

All data inputs latched low

≤+10V

REF

≤+10V

REF

LJ & LCJ 4 88bits

REF

≤+10V LCN, LCWM & LCV 8 8 bits

≤+10V

REF

14.5V to 15.5V 0.0002 0.0025

11.5V to 12.5V 0.0006 FSR/V

4.5V to 5.5V 0.013 0.015

20 Vp-p, f=100 kHz

REF

Typ

(Note 12)

0.2

0.0002 0.0006

3 mVp-p

MIN≤TA≤TMAX

4.75 V

15.75 V

Tested

Limit

(Note 5)

0.05 0.05

0.2 0.2

0.1 0.1

0.4 0.4

. For all other limits

12 V

Design

Limit

Units

% % %

% %

% % %

% %

FS/˚C

to 15 V

(Note 6)

FSR FSR FSR

FSR FSR

FSR FSR FSR

FSR FSR

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Electrical Characteristics (Continued)

10.000 V

REF

25˚C.

Parameter Conditions

CONVERTER CHARACTERISTICS

Output Leakage Current Max

Output I Capacitance I

DIGITAL AND DC CHARACTERISTICS

Digital Input Max Logic Low LJ: 4.75V 0.6 Voltages LJ: 15.75V 0.8

Digital Input Max Digital inputs

Currents LJ & LCJ −50 −200 −200 µA

Supply Current Max LJ & LCJ 1.2 3.5 3.5 mA

Drain LCN, LCWM, LCV 1.7 2.0

unless otherwise noted. Boldface limits apply over temperature, T

Typ

(Note 12)

See

Note

All data inputs LJ & LCJ 10 100 100 nA

OUT1

15.75 V

4.75 V

(Note 5)

MIN≤TA≤TMAX

Tested

Limit

. For all other limits

12 V

Design

Limit

(Note 6)

to 15 V

latched low LCN, LCWM & LCV 50 100

All data inputs LJ & LCJ 100 100 nA

OUT2

latched high LCN, LCWM & LCV 50 100 All data inputs 45 pF

I I

OUT1 OUT2 OUT1 OUT2

latched low 115

All data inputs 130 pF

latched high 30

LCJ: 4.75V 0.7 V LCJ: 15.75V 0.8 LCN, LCWM, LCV 0.95 0.8

Min Logic High LJ & LCJ 2.0 2.0 V

LCN, LCWM, LCV 1.9 2.0

0.8V

LCN, LCWM, LCV −160 −200 µA

Digital inputs

2.0V LJ & LCJ 0.1 +10 +10 µA LCN, LCWM, LCV +8 +10

Limit Units

Electrical Characteristics

10.000 V

REF

25˚C.

Symbol Parameter Conditions

AC CHARACTERISTICS

Current Setting V

Time Write and XFER V

Pulse Width Min 9 320 320 900 900 Data Setup Time V

Min 320 320 900 900 Data Hold Time V

Min 30 50 Control Setup Time V

Min 320 320 1100 1100 Control Hold Time V

Min 00

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified.

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unless otherwise noted. Boldface limits apply over temperature, T

12 V

15.75 V

See

Note

0V, V

5V 1.0 1.0 µs

0V, V

5V 11 100 250 375 600

0V, V

5V 9 100 250 375 600

0V, V

5V 9 30 50 ns

0V, V

5V 9 110 250 600 900

0V, V

5V 9 0 0 10 00

Typ

(Note 12)

Tested

Limit

(Note 5)

to 15 V

Design Limit

(Note 6)

MIN≤TA≤TMAX

Typ

(Note 12)

. For all other limits

4.75 V

Tested

Limit

(Note 5)

Design

Limit

(Note 6)

Limit

Units

Electrical Characteristics (Continued)

Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

allowable power dissipation at any temperature is P

125˚C (plastic) or 150˚C (ceramic), and the typical junction-to-ambient thermal resistance of the J package when board mounted is 80˚C/W.For the N pack-

JMAX

age, this number increases to 100˚C/W and for the V package this number is 120˚C/W. Note 4: For current switching applications, both I

by approximately V Note 5: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

. For example, if V

REF

JMAX−TA

and I

OUT1 REF

must go to ground or the “Virtual Ground” of an operational amplifier. The linearity error is degraded

OUT2

10Vthena1mVoffset, V

)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this device,

,onI

OUT1

or I

Note 6: Guaranteed, but not 100%production tested. These limits are not used to calculate outgoing quality levels.

Note 7: Guaranteed at V Note 8: The unit “FSR” stands for “Full Scale Range.” “Linearity Error” and “Power Supply Rejection” specs are based on this unit to eliminate dependence on a par-

ticular V after performing a zero and full scale adjustment (see Sections 2.5 and 2.6), the plot of the 256 analog voltage outputs will each be within 0.05%xV line which passes through zero and full scale.

value and to indicate the true performance of the part. The “Linearity Error” specification of the DAC0830 is “0.05%of FSR (MAX)”. This guarantees that

REF

10 VDCand V

REF

1VDC.

Note 9: Boldface tested limits apply to the LJ and LCJ suffix parts only. Note 10: A 100nA leakage current with R Note 11: The entire write pulse must occur within the valid data interval for the specified t

20k and V

Note 12: Typicals are at 25˚C and represent most likely parametric norm.

10V corresponds to a zero error of (100x10

REF

W,tDS,tDH

Note 13: Human body model, 100 pF discharged through a 1.5 kΩ resistor.

, θJA, and the ambient temperature, TA. The maximum

JMAX

will introduce an additional 0.01%linearity error.

OUT2

−9

x20x103)x100/10 which is 0.02%of FS.

, and tSto apply.

REF

of a straight

Switching Waveform

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Definition of Package Pinouts

Control Signals (All control signals level actuated)

Chip Select (active low). The CS in combination

CS:

with ILE will enable WR1.

ILE: Input Latch Enable (active high). The ILE in combi-

nation with CS enables WR

WR1: Write1. The active low WR1is used to load the digi-

tal input data bits (DI) into the input latch. The data in the input latch is latched when WR update the input latch–CS and WR1must be low

is high. To

while ILE is high.

: Write2 (active low). This signal, in combination with

XFER, causes the 8-bit data which is available in the input latch to transfer to the DAC register.

Transfercontrol signal (active low). The XFER will

XFER:

enable WR2.

Other Pin Functions

-DI7: Digital Inputs. DI0is the least significant bit (LSB)

and DI

is the most significant bit (MSB).

: DAC Current Output 1. I

OUT1

digital code of all 1’s in the DAC register, and is

is a maximum for a

OUT1

zero for all 0’s in DAC register.

: DAC Current Output 2. I

OUT2

,orI

OUT1

a fixed reference voltage).

: Feedback Resistor. The feedback resistor is pro-

OUT1+IOUT2

is a constant minus

OUT2

constant (I full scale for

Linearity Error

vided on the IC chip for use as the shunt feedback resistor for the external op amp which is used to provide an output voltage for the DAC. This onchip resistor should always be used (not an external resistor) since it matches the resistors which are used in the on-chip R-2R ladder and tracks these resistors over temperature.

: Reference Voltage Input. This input connects an

REF

external precision voltage source to the internal R-2R ladder. V of +10 to −10V. This is also the analog voltage in-

can be selected over the range

REF

put for a 4-quadrant multiplying DAC application.

: Digital Supply Voltage. This is the power supply

pin for the part. V Operation is optimum for +15V

can be from +5 to +15VDC.

GND: The pin 10 voltage must be at the same ground

potential as I applications. Any difference of potential (V

10) will result in a linearity change of

For example, if V I

and I

OUT1

OUT2

Pin 3 can be offset

REF

the linearity change will be 0.03%.

OUT1

and I

for current switching

OUT2

= 10V and pin 10 is 9mV offset from

100mV with no linearity change, but the

logic input threshold will shift.

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a) End point test after

zero and fs adj.

b) Best straight line

Definition of Terms

Resolution: Resolution is directly related to the number of

switches or bits within the DAC. For example, the DAC0830

has 2

or 256 steps and therefore has 8-bit resolution.

Linearity Error: Linearity Error is the maximum deviation from a

straight line passing through the endpoints of the

DAC transfer characteristic

zero and full-scale. Linearity error is a parameter intrinsic to the device and cannot be externally adjusted.

National’s linearity “end point test” (a) and the “best straight line” test (b,c) used by other suppliers are illustrated above. The “end point test’’ greatly simplifies the adjustment procedure by eliminating the need for multiple iterations of checking the linearity and then adjusting full scale until the linearity is met. The “end point test’’ guarantees that linearity is met after a single full scale adjust. (One adjustment vs. multiple

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. It is measured after adjusting for

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c) Shifting fs adj. to pass

best straight line test

iterations of the adjustment.) The “end point test’’ uses a standard zero and F.S. adjustment procedure and is a much more stringent test for DAC linearity.

Power Supply Sensitivity: Power supply sensitivity is a measure of the effect of power supply changes on the DAC full-scale output.

Settling Time: Settling time is the time required from a code transition until the DAC output reaches within

⁄2LSB of the final output value. Full-scale settling time requires a zero to full-scale or full-scale to zero output change.

Full Scale Error: Full scale error is a measure of the output error between an ideal DAC and the actual device output. Ideally, for the DAC0830 series, full scale is V For V 10,0000V–39mV 9.961V. Full-scale error is adjustable to

10V and unipolar operation, V

REF

−1LSB.

REF

FULL-SCALE

zero.

Definition of Terms (Continued)

Differential Nonlinearity: The difference between any two

consecutive codes in the transfer curve from the theoretical 1 LSB to differential nonlinearity.

FIGURE 1. DAC0830 Functional Diagram

Typical Performance Characteristics

Monotonic: If the output of a DAC increases for increasing

digital input code, then the DAC is monotonic. An 8-bit DAC which is monotonic to 8 bits simply means that increasing digital input codes will produce an increasing analog output.

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Digital Input Threshold vs. Temperature

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Digital Input Threshold vs. V

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Gain and Linearity Error Variation vs. Temperature

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Typical Performance Characteristics (Continued)

Gain and Linearity Error

Write Pulse Width

Variation vs. Supply Voltage

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DAC0830 Series Application Hints

These DAC’s are the industry’s first microprocessor compatible, double-buffered 8-bit multiplying D to A converters. Double-buffering allows the utmost application flexibility from a digital control point of view. This 20-pin device is also pin for pin compatible (with one exception) with the DAC1230, a 12-bit MICRO-DAC. In the event that a system’s analog output resolution and accuracy must be upgraded, substituting the DAC1230 can be easily accomplished. By tying address bit A

to the ILE pin, a two-byte µP write instruction (double

precision) which automatically increments the address for the second byte write (starting with A This allows either an 8-bit or the 12-bit part to be used with no hardware or software changes. For the simplest 8-bit application, this pin should be tied to V in section 1.1).

Analog signal control versatility is provided by a precision R-2R ladder network which allows full 4-quadrant multiplication of a wide range bipolar reference voltage by an applied digital word.

1.0 DIGITAL CONSIDERATIONS

A most unique characteristic of these DAC’s is that the 8-bit digital input byte is double-buffered. This means that the data must transfer through two independently controlled 8-bit latching registers before being applied to the R-2R ladder network to change the analog output. The addition of a second register allows two useful control features. First, any DAC in a system can simultaneously hold the current DAC data in one register (DAC register) and the next data word in the second register (input register) to allow fast updating of the DAC output on demand. Second, and probably more important, double-buffering allows any number of DAC’s in a system to be updated to their new analog output levels simultaneously via a common strobe signal.

“1”) can be used.

(also see other uses

Data Hold Time

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The timing requirements and logic level convention of the register control signals have been designed to minimize or eliminate external interfacing logic when applied to most popular microprocessors and development systems. It is easy to think of these converters as 8-bit “write-only” memory locations that provide an analog output quantity.All inputs to these DAC’s meet TTL voltage level specs and can also be driven directly with high voltage CMOS logic in non-microprocessor based systems. To prevent damage to the chip from static discharge, all unused digital inputs should be tied to V are inadvertantly left floating, the DAC interprets the pin as a

or ground. If any of the digital inputs

logic “1”.

1.1 Double-Buffered Operation

Updating the analog output of these DAC’s in a double-buffered manner is basically a two step or double write operation. In a microprocessor system two unique system addresses must be decoded, one for the input latch controlled by the CS pin and a second for the DAC latch which is controlled by the XFER line. If more than one DAC is being driven,

Figure 2

, the CS line of each DAC would typically be decoded individually, but all of the converters could share a common XFER address to allow simultaneous updating of any number of DAC’s. The timing for this operation is shown,

Figure 3

It is important to note that the analog outputs that will change after a simultaneous transfer are those from the DAC’s whose input register had been modified prior to the XFER command.

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