National Semiconductor COP87L88GG Technical data

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COP87L88GG 8-Bit One-Time Programmable (OTP) Microcontroller

with UART and Three Multi-Function Timers

PRELIMINARY

COP87L88GG
8-Bit One-Time Programmable (OTP) Microcontroller
with UART and Three Multi-Function Timers

Y

General Description

The COP87L88GG OTP microcontroller is a member of the

TM

COP8

feature family using an 8-bit core architecture. It is
pin and software compatible to the mask ROM COP888GG
product family.

(Continued)

Features

Y

Full duplex UART

Y

Three 16-bit timers, each with two 16-bit registers
supporting:
Ð Processor independent PWM mode
Ð External event counter mode
Ð Input capture mode

Y

16 kbytes on-board OTP EPROM with security feature

Y

512 bytes on-board RAM

Additional Peripheral Features

Y

Idle Timer

Y

Multi-Input Wakeup (MIWU) with optional interrupts (8)

Y

WATCHDOGTMand clock monitor logic

Y

Two analog comparators

Y

MICROWIRE/PLUSTMserial I/O

I/O Features

Y

Memory mapped I/O

Y

Software selectable I/O options (TRI-STATEÉoutput,
push-pull output, weak pull-up input, high impedance in­put)

Y

Schmitt trigger inputs on ports G and L

Packages:
Ð 40 DIP with 36 I/O pins
Ð 44 PLCC with 40 I/O pins

CPU/Instruction Set Features

Y

1 ms instruction cycle time

Y

Fourteen multi-source vectored interrupts servicing
Ð External interrupt with selectable edge
Ð Idle Timer T0
Ð Three Timers (each with 2 interrupts)
Ð MICROWIRE/PLUS
Ð Multi-Input Wakeup
Ð Software trap
Ð UART (2)
Ð Default VIS (default interrupt)

Y

Versatile and easy to use instruction set

Y

8-bit Stack Pointer SPÐ(stack in RAM)

Y

Two 8-bit register indirect data memory pointers
(B and X)

Fully Static CMOS

Y

Two power saving modes: HALT and IDLE

Y

Single supply operation: 2.7V– 5.5V

Y

Temperature ranges:b40§Ctoa85§C

Development Support

Y

Emulation device for the COP888GG and COP888HG

Y

Real time emulation and full program debug offered by
MetaLink Development System

August 1996

Block Diagram

FIGURE 1. Block Diagram

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUS
PC

, is a registered trademark of International Business Machines Corporation.

É

iceMASTER

C

1996 National Semiconductor Corporation RRD-B30M96/Printed in U. S. A.

TM

, COP8TM, and WATCHDOGTMare trademarks of National Semiconductor Corporation.

TM

is a trademark of MetaLink Corporation.

TL/DD12532

TL/DD/12532– 1

http://www.national.com

General Description (Continued)

It is a fully static part, fabricated using double-metal silicon
gate microCMOS technology. Features include an 8-bit
memory mapped architecture, MICROWIRE/PLUS serial
I/O, three 16-bit timer/counters supporting three modes
(Processor Independent PWM generation, External Event
counter, and Input Capture mode capabilities), full duplex
UART, two comparators, and two power saving modes

Connection Diagrams

Plastic Chip Carrier

(HALT and IDLE), both with a multi-sourced wakeup/inter­rupt capability. This multi-sourced interrupt capability may
also be used independent of the HALT or IDLE modes.
Each I/O pin has software selectable configurations. The
devices operate over a voltage range of 2.7V to 5.5V. High
throughput is achieved with an efficient, regular instruction
set operating at a maximum rate of 1 ms per instruction.

Dual-In-Line Package

Top View

Order Number COP87L88GGV-XE

See NS Package Number V44A

TL/DD/12532– 2

TL/DD/12532– 3

Top View

Order Number COP87L88GGN-XE

See NS Package Number N40A

Note: -X Crystal Oscillator

-E Halt Enable

FIGURE 2. Connection Diagrams

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Connection Diagrams (Continued)

Pinouts for 40- and 44-Pin Packages

Port Type Alt. Fun Alt. Fun

L0 I/O MIWU 17 17
L1 I/O MIWU CKX 18 18
L2 I/O MIWU TDX 19 19
L3 I/O MIWU RDX 20 20
L4 I/O MIWU T2A 21 25
L5 I/O MIWU T2B 22 26
L6 I/O MIWU T3A 23 27
L7 I/O MIWU T3B 24 28

G0 I/O INT 35 39
G1 WDOUT 36 40
G2 I/O T1B 37 41
G3 I/O T1A 38 42
G4 I/O SO 3 3
G5 I/O SK 4 4
G6 I SI 5 5
G7 I/CKO HALT Restart 6 6

D0 O 25 29
D1 O 26 30
D2 O 27 31
D3 O 28 32

I0 I 9 9
I1 I COMP1IN
I2 I COMP1IN
I3 I COMP1OUT 12 12

I4 I COMP2IN
I5 I COMP2IN
I6 I COMP2OUT 15 15
I7 I 16 16

D4 O 29 33
D5 O 30 34
D6 O 31 35
D7 O 32 36

C0 I/O 39 43
C1 I/O 40 44
C2 I/O 1 1
C3 I/O 2 2
C4 I/O 21
C5 I/O 22
C6 I/O 23
C7 I/O 24

V

CC

GND 33 37
CKI 77
RESET

40-Pin 44-Pin

Pack. Pack.

b
a

b
a

10 10
11 11

13 13
14 14

88

34 38

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Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (V

Voltage at Any Pin

Total Current into V

DC Electrical Characteristics

)7V

CC

Pin (Source) 100 mA

CC

b

0.3V to V

a

CC

b

40§CsT

0.3V

Parameter Conditions Min Typ Max Units

Operating Voltage 2.7 5.5 V
Power Supply Ripple (Note 1) Peak-to-Peak 0.1 V

Supply Current (Note 2)

e

CKI

10 MHz V

e

CKI

4 MHz V

HALT Current (Note 3) V

IDLE Current (Note 2)

e

CKI

10 MHz V

e

CKI

1 MHz V

e

5.5V, t

CC

e

4.0V, t

CC

e

5.5V, CKIe0 MHz 12 mA

CC

e

V

4.0V, CKIe0 MHz 8 mA

CC

e

5.5V, t

CC

e

4.0V, t

CC

Input Levels
RESET

Logic High 0.8 V
Logic Low 0.2 V

CKI, (External and Crystal Osc. Modes)

Logic High 0.7 V
Logic Low 0.2 V

All Other Inputs

Logic High 0.7 V
Logic Low 0.2 V

Hi-Z Input Leakage V

Input Pullup Current V

e

5.5V

CC

e

5.5V 40 250 mA

CC

G and L Port Input Hysteresis (Note 7) 0.35 V

Output Current Levels
D Outputs

Source V

Sink (Note 4) V

All Others

Source (Weak Pull-Up Mode) V

Source (Push-Pull Mode) V

Sink (Push-Pull Mode) V

TRI-STATE Leakage V

e

4.5V, V

CC

e

V

2.7V, V

CC

e

4.5V, V

CC

e

V

2.7V, V

CC

e

4.5V, V

CC

e

V

2.7V, V

CC

e

4.5V, V

CC

e

V

2.7V, V

CC

e

4.5V, V

CC

e

V

2.7V, V

CC

e

5.5V

CC

Allowable Sink/Source Current per Pin
(Note 6)

D Outputs (Sink) 15 mA
All others 3mA

Maximum Input Current
without Latchup (Note 5)

RAM Retention Voltage, V

r

500 ns Rise
and Fall Time (min)

Input Capacitance 7pF

Load Capacitance on D2 1000 pF

Total Current out of GND Pin (Sink) 110 mA

Storage Temperature Range

Note:

Absolute maximum ratings indicate limits beyond

b

65§Ctoa140§C

which damage to the device may occur. DC and AC electri­cal specifications are not ensured when operating the de­vice at absolute maximum ratings.

s

a

85§C unless otherwise specified

A

CC

e

1 ms14mA

c

e

2.5 ms 4.5 mA

c

e

1 ms 3.5 mA

c

e

10 ms 0.7 mA

c

CC

CC

CC

b

2

e

3.3V 0.4 mA

OH

e

1.8V 0.2 mA

OH

e

1V 10 mA

OL

e

0.4V 2.0 mA

OL

e

2.7V 10 100 mA

OH

e

1.8V 2.5 33 mA

OH

e

3.3V 0.4 mA

OH

e

1.8V 0.2 mA

OH

e

0.4V 1.6 mA

OL

e

0.4V 0.7 mA

OL

b

2

CC

CC

CC

a

2 mA

CC

a

2 mA

g

200 mA

V

V
V

V
V

V
V

V

2V

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AC Electrical Characteristics

b

40§CsT

s

a

85§C unless otherwise specified

A

Parameter Conditions Min Typ Max Units

Instruction Cycle Time (tc)

s

Crystal, Resonator, 2.7V

R/C Oscillator 2.7V

4.5V

4.5V

s

V

4.5V 2.5 DC ms

CC

s

s

V

5.5V 1 DC ms

CC

s

s

V

4.5V 7.5 DC ms

CC

s

s

V

5.5V 3 DC ms

CC

Inputs

t

SETUP

t

HOLD

Output Propagation Delay (Note 6) R

t

PD1,tPD0

SO, SK 4.5VsV

4.5VsV

2.7V

4.5VsV

2.7V

L

2.7V

All Others 4.5V

2.7V

MICROWIRE Setup Time (t
MICROWIRE Hold Time (t
MICROWIRE Output Propagation Delay (t

)V

UWS

)V

UWH

UPD

CC

CC

)V

CC

s

5.5V 200 ns

CC

s

s

V

4.5V 500 ns

CC

s

5.5V 60 ns

CC

s

s

V

4.5V 150 ns

CC

e

s

s

s

t

t

t

e

2.2k, C

V
V
V

100 pF

L

s

5.5V 0.7 m s

CC

s

4.5V 1.75 ms

CC

s

5.5V 1.0 m s

CC

s

4.5V 2.5 m s

CC

4.5V 20 ns

4.5V 56 ns

4.5V 220 ns

Input Pulse Width (Note 7)

Interrupt Input High Time 1.0 t
Interrupt Input Low Time 1.0 t
Timer 1, 2, 3 Input High Time 1.0 t
Timer 1, 2, 3 Input Low Time 1.0 t

c

c

c

c

Reset Pulse Width 1.0 ms

e

t

Instruction Cycle Time

c

Note 1: Maximum rate of voltage change must be

Note 2: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180

and outputs driven low but not connected to a load.

Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations by bringing CKI high. Test Conditions: All inputs tied to V
ports in the TRI-STATE mode and tied to ground, all outputs low and tied to ground. The clock monitor is disabled.

Note 4: The user must guarantee that D2 pin does not source more than 10 mA during RESET. If D2 sources more than 10 mA during reset, the device will go into
programming mode.

Note 5: Pins G6 and RESET
biased at voltages
pins will not latch up. The voltage at the pins must be limited to

excludes ESD transients.

Note 6: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

Note 7: Parameter characterized but not tested.

are designed with a high voltage input network. These pins allow input voltageslVCCand the pins will have sink current to VCCwhen

l

VCC(the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCCis 750X (typical). These two

k

0.5 V/ms.

out of phase with CKI, inputs connected to V

§

, L and G

CC

k

14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning

CC

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Comparators AC and DC Characteristics V

CC

e

5V, T

e

25§C.

A

Parameter Conditions Min Typ Max Units

s

Input Offset Voltage 0.4VsV

IN

b

V

1.5V

CC

Input Common Mode Voltage Range 0.4 V

Low Level Output Current V

High Level Output Current V

e

0.4V 1.6 mA

OL

e

4.6V 1.6 mA

OH

g

10

g

25 mV

b

1.5 V

CC

DC Supply Current per Comparator (When Enabled) 250 mA

Response Time 100 pF Load 1 ms

TL/DD/12532– 4

FIGURE 3. MICROWIRE/PLUS Timing

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Pin Descriptions

VCCand GND are the power supply pins. All VCCand GND
pins must be connected.

CKI is the clock input. This can come from an R/C generat­ed oscillator, or a crystal oscillator (in conjunction with
CKO). See Oscillator Description section.

RESET

is the master reset input. See Reset Description

section.

The device contains three bidirectional 8-bit I/O ports (C, G
and L), where each individual bit may be independently con­figured as an input (Schmitt Trigger inputs on ports L and
G), output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these
I/O ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also
reserved for the input pins of each I/O port. (See the memo­ry map for the various addresses associated with the I/O
ports.)

Figure 4

DATA and CONFIGURATION registers allow for each port
bit to be individually configured under software control as
shown below:

CONFIGURATION DATA

Register Register

PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.

The Port L supports Multi-Input Wake Up on all eight pins.
L1 is used for the UART external clock. L2 and L3 are

shows the I/O port configurations. The

Port Set-Up

0 0 Hi-Z Input

(TRI-STATE Output)
0 1 Input with Weak Pull-Up
1 0 Push-Pull Zero Output
1 1 Push-Pull One Output

used for the UART transmit and receive. L4 and L5 are used
for the timer input functions T2A and T2B. L6 and L7 are
used for the timer input functions T3A and T3B.

The Port L has the following alternate features:

L0 MIWU

L1 MIWU or CKX

L2 MIWU or TDX

L3 MIWU or RDX

L4 MIWU or T2A

L5 MIWU or T2B

L6 MIWU or T3A

L7 MIWU or T3B

Port G is an 8-bit port with 5 I/O pins (G0, G2 –G5), an input
pin (G6), and a dedicated output pin (G7). Pins G0 and G2–
G6 all have Schmitt Triggers on their inputs. Pin G1 serves
as the dedicated WDOUT WATCHDOG output, while pin G7
is either input or output depending on the oscillator mask
option selected. With the crystal oscillator option selected,
G7 serves as the dedicated output pin for the CKO clock
output. With the single-pin R/C oscillator mask option se­lected, G7 serves as a general purpose input pin but is also
used to bring the device out of HALT mode with a low to
high transition on G7. There are two registers associated
with the G Port, a data register and a configuration register.
Therefore, each of the 5 I/O bits (G0, G2 –G5) can be indi­vidually configured under software control.

Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin (crystal clock option) or general purpose
input (R/C clock option), the associated bits in the data and
configuration registers for G6 and G7 are used for special
purpose functions as outlined on the next page. Reading
the G6 and G7 data bits will return zeros.

FIGURE 4. I/O Port Configurations

TL/DD/12532– 5

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Pin Descriptions (Continued)

Note that the chip will be placed in the HALT mode by writ­ing a ‘‘1’’ to bit 7 of the Port G Data Register. Similarly the
chip will be placed in the IDLE mode by writing a ‘‘1’’ to bit 6
of the Port G Data Register.

Writing a ‘‘1’’ to bit 6 of the Port G Configuration Register
enables the MICROWIRE/PLUS to operate with the alter­nate phase of the SK clock. The G7 configuration bit, if set
high, enables the clock start up delay after HALT when the
R/C clock configuration is used.

Config Reg. Data Reg.

G7 CLKDLY HALT

G6 Alternate SK IDLE

Port G has the following alternate features:

G0 INTR (External Interrupt Input)

G2 T1B (Timer T1 Capture Input)

G3 T1A (Timer T1 I/O)

G4 SO (MICROWIRE Serial Data Output)

G5 SK (MICROWIRE Serial Clock)

G6 SI (MICROWIRE Serial Data Input)

Port G has the following dedicated functions:

G1 WDOUT WATCHDOG and/or Clock Monitor dedicat-

ed output

G7 CKO Oscillator dedicated output or general purpose

input

Port C is an 8-bit I/O port. The 40-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation for these unterminated
pins will return unpredicatable values.

Port I is an eight-bit Hi-Z input port.

Port I1–I3 are used for Comparator 1. Port I4 –I6 are used
for Comparator 2.

The Port I has the following alternate features:

I1 COMP1

I2 COMP1aIN (Comparator 1 Positive Input)

I3 COMP1OUT (Comparator 1 Output)

I4 COMP2bIN (Comparator 2 Negative Input)

I5 COMP2

I6 COMP2OUT (Comparator 2 Output)

Port D is a recreated 8-bit output port that is preset high
when RESET
outputs (except D2) together in order to get a higher drive.

b

IN (Comparator 1 Negative Input)

a

IN (Comparator 2 Positive Input)

goes low. The user can tie two or more D port

Functional Description

The architecture of the device is modified Harvard architec­ture. With the Harvard architecture, the control store pro­gram memory (ROM) is separated from the data store mem­ory (RAM). Both ROM and RAM have their own separate
addressing space with separate address buses. The archi­tecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.

CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or
shift operation in one instruction (t

There are six CPU registers:

A is the 8-bit Accumulator Register

) cycle time.

c

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)

B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.

SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM ad­dress 06F with reset.

S is the 8-bit Data Segment Address Register used to ex­tend the lower half of the address range (00 to 7F) into 256
data segments of 128 bytes each.

All the CPU registers are memory mapped with the excep­tion of the Accumulator (A) and the Program Counter (PC).

PROGRAM MEMORY

The program memory consists of 16 kbytes of OTP
EPROM. These bytes may hold program instructions or con­stant data (data tables for the LAID instruction, jump vectors
for the JID instruction, and interrupt vectors for the VIS in­struction). The program memory is addressed by the 15-bit
program counter (PC). All interrupts in the devices vector to
program memory location 0FF Hex.

The device can be configured to inhibit external reads of the
program memory. This is done by programming the Security
Byte.

SECURITY FEATURE

The program memory array has an associate Security Byte
that is located outside of the program address range. This
byte can be addressed only from programming mode by a
programmer tool.

Security is an optional feature and can only be asserted
after the memory array has been programmed and verified.
A secured part will read all 00(hex) by a programmer. The
part will fail Blank Check and will fail Verify operations. A
Read operation will fill the programmer’s memory with
00(hex). The Security Byte itself is always readable with val­ue of 00(hex) if unsecure and FF(hex) if secure.

DATA MEMORY

The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data
and Pin), the control registers, the MICROWIRE/PLUS SIO
shift register, and the various registers, and counters asso­ciated with the timers (with the exception of the IDLE timer).
Data memory is addressed directly by the instruction or indi­rectly by the B, X, SP pointers and S register.

The data memory consists of 512 bytes of RAM. Sixteen
bytes of RAM are mapped as ‘‘registers’’ at addresses 0F0
to 0FF Hex. These registers can be loaded immediately,
and also decremented and tested with the DRSZ (decre­ment register and skip if zero) instruction. The memory
pointer registers X, SP, B and S are memory mapped into
this space at address locations 0FC to 0FF Hex respective­ly, with the other registers being available for general usage.

The instruction set permits any bit in memory to be set,
reset or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumu­lator (A) bits can also be directly and individually tested.

Note: RAM contents are undefined upon power-up.

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Data Memory Segment
RAM Extension

Data memory address 0FF is used as a memory mapped
location for the Data Segment Address Register (S).

The data store memory is either addressed directly by a
single byte address within the instruction, or indirectly rela­tive to the reference of the B, X, or SP pointers (each con­tains a single-byte address). This single-byte address allows
an addressing range of 256 locations from 00 to FF hex.
The upper bit of this single-byte address divides the data
store memory into two separate sections as outlined previ­ously. With the exception of the RAM register memory from
address locations 00F0 to 00FF, all RAM memory is memo­ry mapped with the upper bit of the single-byte address be­ing equal to zero. This allows the upper bit of the single-byte
address to determine whether or not the base address
range (from 0000 to 00FF) is extended. If this upper bit
equals one (representing address range 0080 to 00FF),
then address extension does not take place. Alternatively, if
this upper bit equals zero, then the data segment extension
register S is used to extend the base address range (from
0000 to 007F) from XX00 to XX7F, where XX represents the
8 bits from the S register. Thus the 128-byte data segment
extensions are located from addresses 0100 to 017F for
data segment 1, 0200 to 027F for data segment 2, etc., up
to FF00 to FF7F for data segment 255. The base address
range from 0000 to 007F represents data segment 0.

Figure 5

illustrates how the S register data memory exten­sion is used in extending the lower half of the base address
range (00 to 7F hex) into 256 data segments of 128 bytes
each, with a total addressing range of 32 kbytes from XX00
to XX7F. This organization allows a total of 256 data seg­ments of 128 bytes each with an additional upper base seg­ment of 128 bytes. Furthermore, all addressing modes are

available for all data segments. The S register must be
changed under program control to move from one data seg­ment (128 bytes) to another. However, the upper base seg­ment (containing the 16 memory registers, I/O registers,
control registers, etc.) is always available regardless of the
contents of the S register, since the upper base segment
(address range 0080 to 00FF) is independent of data seg­ment extension.

The instructions that utilize the stack pointer (SP) always
reference the stack as part of the base segment (Segment

0), regardless of the contents of the S register. The S regis­ter is not changed by these instructions. Consequently, the
stack (used with subroutine linkage and interrupts) is always
located in the base segment. The stack pointer will be inti­tialized to point at data memory location 006F as a result of
reset.

The 128 bytes of RAM contained in the base segment are
split between the lower and upper base segments. The first
112 bytes of RAM are resident from address 0000 to 006F
in the lower base segment, while the remaining 16 bytes of
RAM represent the 16 data memory registers located at ad­dresses 00F0 to 00FF of the upper base segment. No RAM
is located at the upper sixteen addresses (0070 to 007F) of
the lower base segment.

Additional RAM beyond these initial 128 bytes, however, will
always be memory mapped in groups of 128 bytes (or less)
at the data segment address extensions (XX00 to XX7F) of
the lower base segment. The additional 128 bytes of RAM
are memory mapped at address locations 0100 to 017F
hex.

*Reads as all ones.

TL/DD/12532– 21

FIGURE 5. RAM Organization

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Reset

The RESET input when pulled low initializes the microcon­troller. Initialization will occur whenever the RESET
pulled low. Upon initialization, the data and configuration
registers for ports L, G and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is
dedicated as the WATCHDOG and/or Clock Monitor error
output pin. Port D is set high. The PC, PSW, ICNTRL,
CNTRL, T2CNTRL and T3CNTRL control registers are
cleared. The Comparator Select Register is cleared. The S
register is initialized to zero. The Multi-Input Wakeup regis­ters WKEN and WKEDG are cleared. Wakeup register
WKPND is unknown. The stack pointer, SP, is initialized to
6F hex.

The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are in­hibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t
being initialized high will cause a Clock Monitor error follow-

clock cycles. The Clock Monitor bit

C

ing reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
output will continue until 16 t
the clock frequency reaching the minimum specified value,

–32 tCclock cycles following

C

at which time the G1 output will enter the TRI-STATE mode.

The external RC network shown in
to ensure that the RESET

Figure 6

pin is held low until the power

supply to the chip stabilizes.

RCl5cPower Supply Rise Time

FIGURE 6. Recommended Reset Circuit

input is

should be used

TL/DD/12532– 7

CRYSTAL OSCILLATOR

CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.

Table A shows the component values required for various
standard crystal values.

R/C OSCILLATOR

By selecting CKI as a single pin oscillator input, a single pin
R/C oscillator circuit can be connected to it. CKO is avail­able as a general purpose input, and/or HALT restart input.

Table B shows the variation in the oscillator frequencies as
functions of the component (R and C) values.

TL/DD/12532– 9

TL/DD/12532– 8

FIGURE 7. Crystal and R/C Oscillator Diagrams

TABLE A. Crystal Oscillator Configuration, T

R1 R2 C1 C2 CKI Freq

(kX)(MX) (pF) (pF) (MHz)

0 1 30 30– 36 10 V
0 1 30 30– 36 4 V
0 1 200 100–150 0.455 V

TABLE B. RC Oscillator Configuration, T

R C CKI Freq Instr. Cycle

(kX) (pF) (MHz) (ms)

3.3 82 2.2 to 2.7 3.7 to 4.6 V

5.6 100 1.1 to 1.3 7.4 to 9.0 V

6.8 100 0.9 to 1.1 8.8 to 10.8 V

Note: 3ksRs200k

50 pF

sCs

200 pF

e

25§C

A

Conditions

e

5V

CC

e

5V

CC

e

5V

CC

e

25§C

A

Conditions

e

5V

CC

e

5V

CC

e

5V

CC

Oscillator Circuits

The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input fre­quency is divided down by 10 to produce the instruction
cycle clock (1/t

Figure 7

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).

c

shows the Crystal and R/C oscillator diagrams.

Control Registers

CNTRL Register (Address XÊ00EE)

The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:

SL1 & SL0 Select the MICROWIRE/PLUS clock divide

IEDG External interrupt edge polarity select

MSEL Selects G5 and G4 as MICROWIRE/PLUS

T1C0 Timer T1 Start/Stop control in timer

T1C1 Timer T1 mode control bit

T1C2 Timer T1 mode control bit

T1C3 Timer T1 mode control bit

T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0

Bit 7 Bit 0

PSW Register (Address X

The PSW register contains the following select bits:

GIE Global interrupt enable (enables interrupts)

EXEN Enable external interrupt

BUSY MICROWIRE/PLUS busy shifting flag

EXPND External interrupt pending

T1ENA Timer T1 Interrupt Enable for Timer Underflow

T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA

C Carry Flag

HC Half Carry Flag

HC C T1PNDA T1ENA EXPND BUSY EXEN GIE

Bit 7 Bit 0

The Half-Carry bit is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and RC (Reset
Carry) instructions will respectively set or clear both the car­ry flags. In addition to the SC and RC instructions, ADC,
SUBC, RRC and RLC instructions affect the carry and Half
Carry flags.

ICNTRL Register (Address X

The ICNTRL register contains the following bits:

T1ENB Timer T1 Interrupt Enable for T1B Input capture

T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-

mWEN Enable MICROWIRE/PLUS interrupt

mWPND MICROWIRE/PLUS interrupt pending

T0EN Timer T0 Interrupt Enable (Bit 12 toggle)

T0PND Timer T0 Interrupt pending

e

by (00

(0

2, 01e4, 1xe8)

e

Rising edge, 1eFalling edge)

signals SK and SO respectively

modes 1 and 2

Timer T1 Underflow Interrupt Pending Flag in
timer mode 3

00EF)

Ê

or T1A Input capture edge

in mode 1, T1 Underflow in Mode 2, T1A cap­ture edge in mode 3)

00E8)

Ê

edge

ture edge

LPEN L Port Interrupt Enable (Multi-Input Wakeup/In-

terrupt)

Bit 7 could be used as a flag

Unused LPEN T0PND T0EN mWPND mWEN T1PNDB T1ENB

Bit 7 Bit 0

T2CNTRL Register (Address XÊ00C6)

The T2CNTRL register contains the following bits:

T2ENB Timer T2 Interrupt Enable for T2B Input capture

edge

T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-

ture edge

T2ENA Timer T2 Interrupt Enable for Timer Underflow

or T2A Input capture edge

T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA

in mode 1, T2 Underflow in mode 2, T2A cap­ture edge in mode 3)

T2C0 Timer T2 Start/Stop control in timer modes 1

and 2 Timer T2 Underflow Interrupt Pending
Flag in timer mode 3

T2C1 Timer T2 mode control bit

T2C2 Timer T2 mode control bit

T2C3 Timer T2 mode control bit

T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB

Bit 7 Bit 0

T3CNTRL Register (Address XÊ00B6)

The T3CNTRL register contains the following bits:

T3ENB Timer T3 Interrupt Enable for T3B Input capture

edge

T3PNDB Timer T3 Interrupt Pending Flag for T3B cap-

ture edge

T3ENA Timer T3 Interrupt Enable for Timer Underflow

or T3A Input capture edge

T3PNDA Timer T3 Interrupt Pending Flag (Autoload RA

in mode 1, T3 Underflow in mode 2, T3A cap­ture edge in mode 3)

T3C0 Timer T3 Start/Stop control in timer modes 1

and 2

Timer T3 Underflow Interrupt Pending Flag in
timer mode 3

T3C1 Timer T3 mode control bit

T3C2 Timer T3 mode control bit

T3C3 Timer T3 mode control bit

T3C3 T3C2 T3C1 T3C0 T3PNDA T3ENA T3PNDB T3ENB

Bit 7 Bit 0

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Timers

The device contains a very versatile set of timers (T0, T1,
T2, T3). All timers and associated autoreload/capture regis­ters power up containing random data.

TIMER T0 (IDLE TIMER)

The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer T0, which is a
16-bit timer. The Timer T0 runs continuously at the fixed
rate of the instruction cycle clock, t
or write to the IDLE Timer T0, which is a count down timer.

The Timer T0 supports the following functions:

X

Exit out of the Idle Mode (See Idle Mode description)

X

WATCHDOG logic (See WATCHDOG description)

X

Start up delay out of the HALT mode

The IDLE Timer T0 can generate an interrupt when the thir­teenth bit toggles. This toggle is latched into the T0PND
pending flag, and will occur every 4 ms at the maximum
clock frequency (t
interrupt from the thirteenth bit of Timer T0 to be enabled or

e

1 ms). A control flag T0EN allows the

c

disabled. Setting T0EN will enable the interrupt, while reset­ting it will disable the interrupt.

TIMER T1, TIMER T2 AND TIMER T3

The device has a set of three powerful timer/counter
blocks, T1, T2 and T3. The associated features and func­tioning of a timer block are described by referring to the
timer block Tx. Since the three timer blocks, T1, T2 and T3
are identical, all comments are equally applicable to any of
the three timer blocks.

Each timer block consists of a 16-bit timer, Tx, and two
supporting 16-bit autoreload/capture registers, RxA and
RxB. Each timer block has two pins associated with it, TxA
and TxB. The pin TxA supports I/O required by the timer
block, while the pin TxB is an input to the timer block. The
powerful and flexible timer block allows the device to easily
perform all timer functions with minimal software overhead.
The timer block has three operating modes: Processor Inde­pendent PWM mode, External Event Counter mode, and
Input Capture mode.

The control bits TxC3, TxC2, and TxC1 allow selection of
the different modes of operation.

Mode 1. Processor Independent PWM Mode

As the name suggests, this mode allows the device to gen­erate a PWM signal with very minimal user intervention. The
user only has to define the parameters of the PWM signal
(ON time and OFF time). Once begun, the timer block will
continuously generate the PWM signal completely indepen­dent of the microcontroller. The user software services the
timer block only when the PWM parameters require updat­ing.

In this mode the timer Tx counts down at a fixed rate of t
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from

. The user cannot read

c

the register RxA. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB.

The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.

Figure 8

shows a block diagram of the timer in PWM mode.

The underflows can be programmed to toggle the TxA out­put pin. The underflows can also be programmed to gener­ate interrupts.

Underflows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending flags under software control. Two control en­able flags, TxENA and TxENB, allow the interrupts from the
timer underflow to be enabled or disabled. Setting the timer
enable flag TxENA will cause an interrupt when a timer un­derflow causes the RxA register to be reloaded into the tim­er. Setting the timer enable flag TxENB will cause an inter­rupt when a timer underflow causes the RxB register to be
reloaded into the timer. Resetting the timer enable flags will
disable the associated interrupts.

Either or both of the timer underflow interrupts may be en­abled. This gives the user the flexibility of interrupting once
per PWM period on either the rising or falling edge of the
PWM output. Alternatively, the user may choose to interrupt
on both edges of the PWM output.

FIGURE 8. Timer in PWM Mode

Mode 2. External Event Counter Mode

This mode is quite similar to the processor independent
PWM mode described above. The main difference is that
the timer, Tx, is clocked by the input signal from the TxA pin.
The Tx timer control bits, TxC3, TxC2 and TxC1 allow the
timer to be clocked either on a positive or negative edge
from the TxA pin. Underflows from the timer are latched into
the TxPNDA pending flag. Setting the TxENA control flag
will cause an interrupt when the timer underflows.

In this mode the input pin TxB can be used as an indepen-

.

c

dent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag.

TL/DD/12532– 10

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Timers (Continued)

Figure 9

Event Counter mode.

Note: The PWM output is not available in this mode since the TxA pin is

shows a block diagram of the timer in External

being used as the counter input clock.

Underflows from the timer can also be programmed to gen­erate interrupts. Underflows are latched into the timer TxC0
pending flag (the TxC0 control bit serves as the timer under­flow interrupt pending flag in the Input Capture mode). Con­sequently, the TxC0 control bit should be reset when enter­ing the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
the TxPNDA and TxC0 pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.

Figure 10

shows a block diagram of the timer in Input Cap-

ture mode.

FIGURE 9. Timer in External Event Counter Mode

TL/DD/12532– 11

Mode 3. Input Capture Mode

The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode.

In this mode, the timer Tx is constantly running at the fixed
t

rate. The two registers, RxA and RxB, act as capture

c

registers. Each register acts in conjunction with a pin. The
register RxA acts in conjunction with the TxA pin and the
register RxB acts in conjunction with the TxB pin.

The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
TxC3, TxC2 and TxC1, allow the trigger events to be speci­fied either as a positive or a negative edge. The trigger con­dition for each input pin can be specified independently.

The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag
TxENA allows the interrupt on TxA to be either enabled or
disabled. Setting the TxENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.

FIGURE 10. Timer in Input Capture Mode

TL/DD/12532– 12

TIMER CONTROL FLAGS

The timers T1, T2 and T3 have indentical control structures.
The control bits and their functions are summarized below.

TxC0 Timer Start/Stop control in Modes 1 and 2

(Processor Independent PWM and External
Event Counter), where 1

e

Start, 0eStop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)

TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag

TxENA Timer Interrupt Enable Flag
TxENB Timer Interrupt Enable Flag

e

1

Timer Interrupt Enabled

e

0

Timer Interrupt Disabled

TxC3 Timer mode control
TxC2 Timer mode control
TxC1 Timer mode control

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