National Semiconductor COP87L88EK, COP87L88RK Technical data
查询COP87L88EK Family供应商
COP87L88EK/RK Family
8-Bit CMOS OTP Microcontrollers with 8k or 32k
Memory, Comparator, and Single-slope A/D Capability
General Description
The COP87L88EK/RK Family OTP (One Time Programmable) microcontrollers are highly integrated COP8
ture core devices with 16k or 32k memory and advanced
features including a Multi-Input Comparator and
Single-slope A/D capability. These multi-chip CMOS devices
are suited for applications requiring a full featured, low EMI
controller with an analog comparator, current source, and
voltage reference, and as pre-production devices for a
masked ROM design. Lower cost pin and software compatible 8k ROM versions (COP888EK) are available forusewith
a range of COP8 software and hardware development tools.
COP87L88EK/RK Family, 8-Bit CMOS OTP Microcontrollers with 8k or 32k Memory, Comparator,
and Single-slope A/D Capability
July 1999
Family features include an 8-bit memory mapped architecture, 10 MHz CKI (-XE=crystal oscillator) with 1 µs instruc-
™
tion cycle, three multi-function 16-bit timer/counters with
Fea-
PWM, MICROWIRE/PLUS
parator with seven input multiplexor, an analog current
source and V
modes, idle timer, MIWU, high current outputs, software selectable I/O options, WATCHDOG
2.7V to 5.5V operation and 28/40/44 pin packages.
Devices included in this datasheet are:
/2 reference, two power saving HALT/IDLE
CC
™
serial I/O, one analog com-
™
timer and Clock Monitor,
Device Memory (bytes) RAM (bytes) I/O Pins Packages Temperature
COP87L84EK 16k OTP EPROM 256 24 28 DIP/SOIC -40 to +85˚C
COP87L88EK 16k OTP EPROM 256 36/40 40 DIP, 44 PLCC -40 to +85˚C
COP87L84RK 32k OTP EPROM 256 24 28 DIP/SOIC -40 to +85˚C
COP87L88RK 32k OTP EPROM 256 36/40 40 DIP, 44 PLCC -40 to +85˚C
Key Features
n Analog function block with
— Analog comparator with seven input multiplexor
— Constant current source and V
n Three 16-bit timers, each with two 16-bit registers
supporting:
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
n 8 or 32 kbytes on-board EPROM with security feature
n 256 bytes on-board RAM
/2 reference
CC
Additional Peripheral Features
n Idle Timer
n Multi-Input Wake Up (MIWU) with optional interrupts (8)
n WATCHDOG and Clock Monitor logic
n MICROWIRE/PLUS serial I/O
I/O Features
n Software selectable I/O options ( TRI-STATE™Output,
Push-Pull Output, Weak Pull-Up Input, High Impedance
Input)
n Packages:
— 44 PLCC with 40 I/O pins
— 40 DIP with 36 I/O pins
— 28 DIP/SO with 24 I/O pins
n Schmitt trigger inputs on Port G and L
CPU/Instruction Set Feature
n 1 µs instruction cycle time
n Twelve multi-source vectored interrupts servicing
— External Interrupt with selectable edge
— Idle Timer T0
— Three Timers (Each with 2 interrupts)
— MICROWIRE/PLUS
— Multi-Input Wake Up
— Software Trap
— Default VIS (default interrupt)
n Versatile and easy to use instruction set
n 8-bit Stack Pointer (SP)—stack in RAM
n Two 8-bit Register Indirect Data Memory Pointers
(B, X)
Fully Static CMOS
n Two power saving modes: HALT and IDLE
n Single supply operation: 2.7V to 5.5V
n Temperature ranges: −40˚C to +85˚C
Development Support
n Emulation devices for the COP888EK/COP884EK
n Real time emulation and full program debug offered by
MetaLink Development System
COP8™is a trademark of National Semiconductor Corporation.
MICROWIRE/PLUS
TRI-STATE
WATCHDOG
iceMASTER
© 1999 National Semiconductor Corporation DS101133 www.national.com
™
is a trademark of National Semiconductor Corporation.
®
is a registered trademark of National Semiconductor Corporation.
™
is a trademark of National Semiconductor Corporation.
™
is a trademark of MetaLink Corporation.
Block Diagram
DS101133-1
FIGURE 1. Block Diagram
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Connection Diagrams
Plastic Chip Carrier
DS101133-2
Top View
Order Number COP87L88EKV-XE or COP87L88RKV-XE
See NS Plastic Chip Package Number V44A
Dual-In-Line Package
Dual-In-Line Package
DS101133-3
Top View
Order Number COP87L84EKN-XE or COP87L84RKN-XE
See NS Molded Package Number N40A
Note: -X Crystal Oscillator
-E Halt Mode Enabled
DS101133-4
Top View
Order Number COP87L84EKN-XE or COP87L84RKN-XE
See NS Molded Package Number N28B
Order Number COP87L84EKM-XE or COP87L84RKM-XE
See NS Molded Package Number M28B
FIGURE 2. Connection Diagrams
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Connection Diagrams (Continued)
Pinouts for 28-, 40-, and 44-Pin Packages
Port Type Alt. Fun Alt. Fun
L0 I/O MIWU 11 17 17
L1 I/O MIWU 12 18 18
L2 I/O MIWU 13 19 19
L3 I/O MIWU 14 20 20
L4 I/O MIWU T2A 15 21 25
L5 I/O MIWU T2B 16 22 26
L6 I/O MIWU T3A 17 23 27
L7 I/O MIWU T3B 18 24 28
G0 I/O INT 25 35 39
G1 WDOUT 26 36 40
G2 I/O T1B 27 37 41
G3 I/O T1A 28 38 42
G4 I/O SO 1 3 3
G5 I/O SK 2 4 4
G6ISI 355
G7 I/CKO HALT Restart 4 6 6
D0O 192529
D1O 202630
D2O 212731
D3O 222832
I0 I COMPIN1+ 7 9 9
I1 I COMPIN−/Current 8 10 10
Source Out
I2 I COMPIN0+ 9 11 11
I3 I COMPOUT/COMPIN2+ 10 12 12
I4 I COMPIN3+ 13 13
I5 I COMPIN4+ 14 14
I6 I COMPIN5+ 15 15
I7 I COMPOUT 16 16
D4 O 29 33
D5 O 30 34
D6 O 31 35
D7 O 32 36
C0 I/O 39 43
C1 I/O 40 44
C2 I/O 1 1
C3 I/O 2 2
C4 I/O 21
C5 I/O 22
C6 I/O 23
C7 I/O 24
V
CC
GND 23 33 37
CKI 5 7 7
RESET
28-Pin 40-Pin 44-Pin
Pack. Pack. Pack.
688
24 34 38
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor SalesOffice/
Distributors for availability and specifications.
Supply Voltage (V
Voltage at Any Pin −0.3V to V
)7V
CC
CC
+ 0.3V
Total Current into V
Pin (Source) 100 mA
CC
Total Current out of GND Pin (Sink) 110 mA
Storage Temperature Range −65˚C to +140˚C
Note 1:
Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
DC Electrical Characteristics
−40˚C ≤ TA≤ +85˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Operating Voltage 2.7 5.5 V
Power Supply Ripple (Note 3) Peak-to-Peak 0.1 V
CC
Supply Current (Note 4)
CKI=10 MHz V
CKI=4 MHz V
HALT Current (Note 5) V
=
CC
=
CC
=
CC
=
V
CC
=
5.5V, t
4.0V, t
1 µs 16.5 mA
c
=
2.5 µs 6.5 mA
c
5.5V, CKI=0 MHz 12 µA
4.0V, CKI=0 MHz 8 µA
IDLE Current (Note 4)
CKI=10 MHz V
CKI=4 MHz V
Input Levels (V
IH,VIL
)
=
CC
=
CC
5.5V, t
4.0V, t
=
1 µs 3.5 mA
c
=
10 µs 0.7 mA
c
RESET
Logic High 0.8 V
Logic Low 0.2 V
CC
CC
CKI, All Other Inputs
Logic High 0.7 V
Logic Low 0.2 V
Hi-Z Input Leakage V
Input Pullup Current V
=
5.5V −2 +2 µA
CC
=
5.5V, V
CC
=
0V −40 −250 µA
IN
G and L Port Input Hysteresis (Note 8) 0.35 V
CC
CC
CC
Output Current Levels
D Outputs
Source V
Sink V
=
4.5V, V
CC
=
4.5V, V
CC
=
3.3V −0.4 mA
OH
=
1V 10 mA
OL
All Others
Source (Weak Pull-Up Mode) V
Source (Push-Pull Mode) V
Sink (Push-Pull Mode) V
TRI-STATE Leakage V
=
4.5V, V
CC
=
4.5V, V
CC
=
4.5V, V
CC
=
6.0V −2 +2 µA
CC
=
2.7V −10 −110 µA
OH
=
3.3V −0.4 mA
OH
=
0.4V 1.6 mA
OL
Allowable Sink/Source Current per Pin
(Note 8)
D Outputs (Sink) 15 mA
All others 3mA
Maximum Input Current Room Temp
±
200 mA
without Latchup (Note 6)
RAM Retention Voltage, V
r
500 ns Rise 2 V
and Fall Time (min)
Input Capacitance 7pF
Load Capacitance on D2 1000 pF
V
V
V
V
V
V
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AC Electrical Characteristics
−40˚C ≤ TA≤ +85˚C unless otherwise specified
Parameter Conditions Min Typ Max Units
Instruction Cycle Time (t
Crystal, Resonator, 4.5V ≤ V
R/C Oscillator 4.5V ≤ V
Inputs
t
SETUP
t
HOLD
Output Propagation Delay (Note 7) R
t
PD1,tPD0
SO, SK 4.5V ≤ VCC≤ 5.5V 0.7 µs
All Others 4.50V ≤ V
MICROWIRE Setup Time (t
MICROWIRE Hold Time (t
MICROWIRE Output Propagation Delay (t
Input Pulse Width (Note 8)
Interrupt Input High Time 1.0 t
Interrupt Input Low Time 1.0 t
Timer 1, 2, 3 Input High Time 1.0 t
Timer 1, 2, 3 Input Low Time 1.0 t
Reset Pulse Width 1.0 µs
=
Note 2: t
Note 3: Maximum rate of voltage change must be
Note 4: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V
and outputs driven low but not connected to a load.
Note 5: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of I
sinking current; with L, C, G0, and G2–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to
V
in crystal clock mode.
Note 6: Pins G6 and RESET are designed with ahighvoltageinput network. These pins allow input voltages
biased at voltages>VCC(the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCCis 750Ω (typical). These two
pins will not latch up. The voltage at the pins must be limited to
cludes ESD transients.
Note 7: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 8: Parameter characterized but not tested.
Instruction Cycle Time
c
; clock monitor and comparator disabled. Parameter refers to HALTmode entered via setting bit 7 of the G Port data register.Part will pull up CKI during HALT
CC
)
c
≤ 5.5V 1.0 DC µs
CC
≤ 5.5V 3.0 DC µs
CC
4.5V ≤ VCC≤ 5.5V 200 ns
4.5V ≤ VCC≤ 5.5V 60 ns
=
L
) (Note 7) VCC≥ 4.5V 20 ns
UWS
) (Note 7) VCC≥ 4.5V 56 ns
UWH
)V
UPD
<
0.5 V/ms.
<
14V.WARNING: Voltages in excess of 14V will cause damage to the pins. This warning ex-
=
2.2k, C
100 pF
L
≤ 5.5V 1.0 µs
CC
≥ 4.5V 220 ns
CC
HALTis done with device neither sourcing nor
DD
>
VCCand the pins will have sink current to VCCwhen
c
c
c
c
CC
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Analog Function Block AC and DC Characteristics
=
V
5.0V, −40˚C ≤ T
CC
Parameter Conditions Min Typ Max Units
Input Offset Voltage 0.4V
Input Common Mode Voltage Range
(Note 10)
V
/2 Reference 4.5V<V
CC
DC Supply Current for
Comparator (when enabled)
DC Supply Current for
V
/2 Reference (when enabled)
CC
DC Supply Current for
Constant Current Source (when enabled)
Constant Current Source 4.5V
Current Source Variation over 4.5V
Common Mode Range Temp=Constant
Current Source Enable Time 1.5 2 µs
Comparator Response Time 100 mV Overdrive, 1 µs
Note 9: While performance characteristics are given at V
/2 reference and the constant current source is not guaranteed beyond the specified limits.
V
CC
Note 10: The device is capable of operating over a common mode voltage range of 0 to V
and 0.4V.
≤ +85˚C
A
<
<
V
VCC− 1.5V
IN
0.4 V
<
5.5V 0.5 VCC− 0.04 0.5 V
CC
=
V
5.5V
CC
=
V
5.5V
CC
=
V
5.5V
CC
<
<
V
5.5V 10 20 40 µA
CC
<
<
V
5.5V
CC
100 pF Load
=
5.0V, the analog function block will operate over the entire 2.5V–6.0V V
CC
− 1.5V, however increased offset voltage will be observed between 0V
CC
±
10
CC
±
25 mV
− 1.5 V
CC
0.5 VCC+ 0.04 V
250 µA
50 80 µA
200 µA
±
2µA
range. Accuracy of the
CC
FIGURE 3. MICROWIRE/PLUS Timing
Typical Performance Characteristics (−55˚C ≤ T
DS101133-19 DS101133-20
DS101133-18
=
A
+125˚C)
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Typical Performance Characteristics (−55˚C ≤ T
DS101133-21 DS101133-22
=
+125˚C) (Continued)
A
DS101133-23
DS101133-28
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DS101133-27
DS101133-29
Typical Performance Characteristics (−55˚C ≤ T
Pin Descriptions
VCCand GND are the power supply pins. All VCCand GND
pins must be connected.
CKI is the clockinput. This can come from an R/C generated
oscillator, or a crystal oscillator (in conjunction with CKO).
See Oscillator Description section.
RESET is the master reset input. See ResetDescription section.
The device contains three bidirectional 8-bit I/O ports (C, G
and L), where each individual bit may be independently configured as an input(Schmitt Trigger inputs on ports Land G),
output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these
I/O ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATAregister. A memory mapped address is also reserved for the input pins of each I/O port. (See the memory
map for the various addresses associated with theI/O ports.)
Figure 4
shows the I/O port configurations. The DATA and
CONFIGURATION registers allow for each port bit to be individually configured under software control as shown below:
CONFIGURA-
TION
Register Register
0 0 Hi-Z Input
0 1 Input with Weak Pull-Up
1 0 Push-Pull Zero Output
1 1 Push-Pull One Output
PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.
The Port L supports Multi-Input Wake Up on alleight pins. L4
and L5 are used for the timer input functions T2A and T2B.
L6 and L7 are used for the timer input functions T3A and
T3B.
DATA
Port Set-Up
(TRI-STATE Output)
The Port L has the following alternate features:
L7 MIWU or T3B
L6 MIWU or T3A
L5 MIWU or T2B
L4 MIWU or T2A
L3 MIWU
L2 MIWU
L1 MIWU
L0 MIWU
Port G is an 8-bit port with 5 I/O pins (G0, G2–G5), an input
pin (G6), and a dedicated output pin (G7). Pins G0 and
G2–G6 all have Schmitt Triggers on their inputs. Pin G1
serves as the dedicated WDOUT WATCHDOGoutput, while
pin G7 is either input or output depending on the oscillator
mask option selected. With the crystal oscillator option selected, G7 serves as the dedicated output pin for the CKO
clock output. With the single-pin R/C oscillator mask option
selected, G7 serves as a general purpose input pin but is
also used to bring the device out of HALT mode with alow to
high transition on G7. There are two registers associated
with the G Port, a data register and a configuration register.
Therefore, each of the 5 I/O bits (G0, G2–G5) can be individually configured under software control.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin (crystal clock option) or general purpose input (R/C clock option), the associated bits in the data and
configuration registers for G6 and G7 are used for special
purpose functions as outlined on the nextpage. Reading the
G6 and G7 data bits will return zeros.
=
+125˚C) (Continued)
A
DS101133-30
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Pin Descriptions (Continued)
FIGURE 4. I/O Port Configurations
Note that the chipwill beplaced inthe HALT mode by writing
a “1” to bit 7 of the Port G Data Register. Similarly the chip
will be placed inthe IDLEmode bywriting a “1” to bit 6 of the
Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register enables the MICROWIRE/PLUS to operate with the alternate
phase of the SK clock. The G7 configuration bit, if set high,
enables the clock start up delay after HALT when the R/C
clock configuration is used.
Config Reg. Data Reg.
G7 CLKDLY HALT
G6 Alternate SK IDLE
Port G has the following alternate features:
G6 SI (MICROWIRE Serial Data Input)
G5 SK (MICROWIRE Serial Clock)
G4 SO (MICROWIRE Serial Data Output)
G3 T1A (Timer T1 I/O)
G2 T1B (Timer T1 Capture Input)
G0 INTR (External Interrupt Input)
Port G has the following dedicated functions:
G7 CKO Oscillator dedicated output or general purpose
input
G1 WDOUT WATCHDOG and/or Clock Monitor dedi-
cated output
Port C is an 8-bit I/O port. The 40-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation for these unterminated pins
will return unpredicatable values.
PORTI is aneight-bit Hi-Z input port. The 28-pin device does
not have a full complement of Port I pins. The unavailable
pins are not terminated i.e., they are floating. A read operation for these unterminatedpins will return unpredictable values. The user must ensure that the software takes this into
account by either masking or restricting the accesses to bit
operations. The unterminated Port I pins will draw power
only when addressed.
Port I is an eight-bit Hi-Z input port.
Port I0–I7 are used for the analog function block.
The Port I has the following alternate features:
I7 COMPOUT (Comparator Output)
I6 COMPIN5+ (Comparator Positive Input 5)
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DS101133-5
I5 COMPIN4+ (Comparator Positive Input 4)
I4 COMPIN3+ (Comparator Positive Input 3)
I3 COMPOUT/COMPIN2+ (Comparator Output/
Comparator Positive Input 2))
I2 COMPIN0+ (Comparator Positive Input 0)
I1 COMPIN− (Comparator Negative Input/Current
Source Out)
I0 COMPIN1+ (Comparator Positive Input 1)
Port D is an 8-bitoutput port thatis presethigh when RESET
goes low. The user can tie two or more D port outputs (except D2) together in order to get a higher drive.
Note: Care must be exercised with the D2 pin operation. At RESET, the ex-
ternal loads on this pin must ensure that the output voltages stay
above 0.8 V
keep the external loading on D2 to
to prevent the chip from entering special modes. Also
CC
<
1000 pF.
Functional Description
The architecture of the device is modified Harvard architecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store
memory (RAM). Both ROM and RAM have their own separate addressing space with separate address buses. The architecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bitaddition, subtraction,logical or shift
operation in one instruction (t
There are six CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.
) cycle time.
c
Functional Description (Continued)
S is the 8-bit Data Segment Address Register used toextend
the lower half of the address range (00 to 7F) into 256 data
segments of 128 bytes each.
All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).
The device can be configured to inhibit external reads of the
program memory. This is done by programming the Security
Byte.
PROGRAM MEMORY
The program memory consists of 8192 bytes of OTP
EPROM. These bytes mayhold program instructions or constant data (data tables for the LAID instruction, jump vectors
for the JID instruction, and interrupt vectors for the VIS instruction). The program memory is addressed by the 15-bit
program counter (PC). All interrupts in the devices vector to
program memory location 0FF Hex.
The device can be configured to inhibit external reads of the
program memory. This is done by programming the Security
Byte.
SECURITY FEATURE
The program memory array has an associate Security Byte
that is located outside of the program address range. This
byte can be addressed only from programming mode by a
programmer tool.
Security is an optional feature andcan onlybe asserted after
the memory array has been programmed and verified. A secured part will read all 00(hex) by a programmer. The part
will fail Blank Check and will fail Verify operations. A Read
operation will fill the programmer’s memory with 00(hex).
The Security Byte itself is always readable with value of
00(hex) if unsecure and FF(hex) if secure.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers(Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X, SP pointers and S register.
The data memory consists of 256 bytes of RAM. Sixteen
bytes of RAM are mappedas “registers”at addresses0F0 to
0FF Hex. These registers can be loaded immediately, and
also decremented and tested with the DRSZ (decrement
register and skip if zero) instruction. The memory pointer
registers X, SP,B andS arememory mappedinto thisspace
at address locations 0FC to 0FF Hex respectively, with the
other registers being available for general usage.
The instruction set permitsany bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set,reset andtested. The accumulator (A) bits can also be directly and individually tested.
Note: RAM contents are undefined upon power-up.
Data Memory Segment RAM
Extension
Data memory address 0FF is used as a memory mapped location for the Data Segment Address Register (S).
The data store memory is either addressed directly by a
single byte address within the instruction, or indirectly relative to the reference of the B, X, or SP pointers (each contains a single-byte address). This single-byte address allows
an addressing range of256 locationsfrom 00to FFhex. The
upper bit of this single-byte address divides the data store
memory into two separate sections as outlined previously.
With the exception of the RAM register memory from address locations 00F0 to 00FF, all RAM memory is memory
mapped with the upper bit of the single-byte address being
equal to zero. This allows the upper bit ofthe single-byte address to determine whether or not the base address range
(from 0000 to 00FF) is extended. If this upper bit equals one
(representing address range 0080 to 00FF), then address
extension does not take place. Alternatively, if this upper bit
equals zero, then the data segment extension register S is
used to extend the base address range (from 0000 to 007F)
from XX00 to XX7F, where XX represents the 8 bits from the
S register. Thus the 128-byte data segment extensions are
located from addresses 0100 to 017F for data segment 1,
0200 to 027F for data segment 2, etc., up to FF00 to FF7F
for data segment 255.The base address range from 0000 to
007F represents data segment 0.
Figure 5
illustrates how the S register data memory extension is used in extending the lower half of the base address
range (00 to 7F hex) into 256 data segments of 128 bytes
each, with a total addressing range of 32 kbytes from XX00
to XX7F. This organization allows a total of 256 data segments of 128 bytes each with an additional upper base segment of 128 bytes. Furthermore, all addressing modes are
available for all data segments. The S register must be
changed under program control to move from one data segment (128 bytes) to another. However, the upper base segment (containing the 16 memory registers, I/O registers,
control registers, etc.) is always available regardless of the
contents of the S register, since the upper base segment
(address range 0080 to 00FF) is independent of data segment extension.
The instructions that utilize thestack pointer (SP)always reference the stack as part of the base segment (Segment 0),
regardless of the contents of the S register. The S register is
not changed by these instructions. Consequently, the stack
(used with subroutine linkage and interrupts) is always located in the base segment. The stack pointer will be intitialized to point at data memory location 006F as a result of reset.
The 128 bytes of RAM contained in the base segment are
split between the lower and upper base segments. The first
112bytes ofRAM are resident from address 0000 to 006F in
the lower base segment, while the remaining 16 bytes of
RAM represent the 16 data memory registers located at addresses 00F0 to 00FF of the upper base segment. No RAM
is located at the upper sixteen addresses (0070 to 007F) of
the lower base segment.
Additional RAM beyond these initial 128 bytes, however, will
always be memory mapped in groups of 128 bytes (or less)
at the data segment address extensions (XX00 to XX7F) of
the lower base segment. The additional 128 bytes of RAM
are memory mapped at address locations 0100 to 017F hex.
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Data Memory Segment RAM
Extension
(Continued)
*Reads as all ones.
DS101133-6
FIGURE 5. RAM Organization
Reset
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for ports L, G and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is anexception (asnoted below)since pinG1 is dedicated as the WATCHDOGand/or Clock Monitor error output
pin. Port D is set high. The PC, PSW, ICNTRL, CNTRL,
T2CNTRL and T3CNTRL control registers are cleared. The
Comparator Select Register is cleared. The S register is initialized to zero. The Multi-Input Wakeup registers WKEN and
WKEDG are cleared. Wakeup register WKPND is unknown.
The stack pointer, SP, is initialized to 6F hex.
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are inhibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k t
being initialized high will cause a Clock Monitor error following reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
output will continue until 16 t
the clock frequency reaching the minimum specified value,
at which time the G1 output will enter the TRI-STATE mode.
The external RC network shown in
to ensure that the RESETpin is heldlow until thepower supply to the chip stabilizes.
clock cycles. The Clock Monitor bit
C
–32 tCclock cycles following
C
Figure 6
should be used
RC>5 x Power Supply Rise Time
DS101133-7
FIGURE 6. Recommended Reset Circuit
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input frequency is divided down by 10 to produce the instruction
cycle clock (1/t
Note: External clocks with frequencies above about 4 MHz require the user
to drive the CKO (G7) pin with a signal 180 degrees out of phase with
CKI.
Figure 7
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop crystal (or resonator) controlled oscillator.
Table 1
standard crystal values.
R/C OSCILLATOR
By selecting CKI as a single pin oscillator input, a single pin
R/C oscillator circuit can beconnected toit. CKOis available
as a general purpose input, and/or HALT restart input.
Note: Use of the R/C oscillator option will result in higher electromagnetic
emissions.
Table 2
functions of the component (R and C) values.
).
c
shows the Crystal and R/C oscillator diagrams.
shows the component values required for various
shows the variation in the oscillator frequencies as
DS101133-8
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DS101133-9
FIGURE 7. Crystal and R/C Oscillator Diagrams
Oscillator Circuits (Continued)
TABLE 1. Crystal Oscillator Configuration, T
R1 R2 C1 C2 CKI Freq
(kΩ)(MΩ) (pF) (pF) (MHz)
0 1 30 30–36 10 V
0 1 30 30–36 4 V
0 1 200 100–150 0.455 V
TABLE 2. RC Oscillator Configuration, T
R C CKI Freq Instr. Cycle
(kΩ) (pF) (MHz) (µs)
3.3 82 2.2 to 2.7 3.7 to 4.6 V
5.6 100 1.1 to 1.3 7.4 to 9.0 V
6.8 100 0.9 to 1.1 8.8 to 10.8 V
Note 11: 3k ≤ R ≤ 200k
50 pF ≤ C ≤ 200 pF
=
25˚C
A
Conditions
=
CC
=
CC
=
CC
=
25˚C
A
Conditions
=
CC
=
CC
=
CC
5V
5V
5V
5V
5V
5V
Control Registers
CNTRL Register (Address X'00EE)
T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0
Bit 7 Bit 0
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
T1C3 Timer T1 mode control bit
T1C2 Timer T1 mode control bit
T1C1 Timer T1 mode control bit
T1C0 Timer T1 Start/Stop control in timer
modes 1 and 2, T1 Underflow Interrupt
Pending Flag in timer mode 3
MSEL Selects G5 and G4 as MICROWIRE/PLUS
IEDG External interrupt edge polarity select
SL1 & SL0 Select the MICROWIRE/PLUS clock divide
PSW Register (Address X'00EF)
HC C T1PNDA T1ENA EXPND BUSY EXEN GIE
Bit 7 Bit 0
The PSW register contains the following select bits:
HC Half Carry Flag
C Carry Flag
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload
T1ENA Timer T1 Interrupt Enable for Timer Underflow
EXPND External interrupt pending
BUSY MICROWIRE/PLUS busy shifting flag
EXEN Enable external interrupt
GIE Global interrupt enable (enables interrupts)
The Half-Carry flag is also affectedby all the instructionsthat
affect the Carry flag. The SC (Set Carry) and R/C (Reset
Carry) instructions will respectively set or clear boththe carry
signals SK and SO respectively
(0 = Rising edge, 1 = Falling edge)
by (00 = 2, 01 = 4, 1x = 8)
RA in mode 1, T1 Underflow in Mode 2, T1A
capture edge in mode 3)
or T1A Input capture edge
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.
ICNTRL Register (Address X'00E8)
Rsvd LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB
Bit 7 Bit 0
The ICNTRL register contains the following bits:
Rsvd This bit is reserved and must be zero
LPEN L Port Interrupt Enable (Multi-Input Wakeup/
Interrupt)
T0PND Timer T0 Interrupt pending
T0EN Timer T0 Interrupt Enable (Bit 12 toggle)
µWPND MICROWIRE/PLUS interrupt pending
µWEN Enable MICROWIRE/PLUS interrupt
T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-
ture edge
T1ENB TimerT1 InterruptEnable for T1B Inputcapture
edge
T2CNTRL Register (Address X'00C6)
T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB
Bit 7 Bit 0
The T2CNTRL control register contains the following bits:
T2C3 Timer T2 mode control bit
T2C2 Timer T2 mode control bit
T2C1 Timer T2 mode control bit
T2C0 Timer T2 Start/Stop control in timer
modes 1 and 2, T2 Underflow Interrupt Pending Flag in timer mode 3
T2PNDA Timer T2 Interrupt Pending Flag (Autoreload
RA in mode 1, T2 Underflow in mode 2, T2A
capture edge in mode 3)
T2ENA Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge
T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-
ture edge
T2ENB Timer T2 Interrupt Enable for Timer Underflow
or T2B Input capture edge
T3CNTRL Register (Address X'00B6)
T3C3 T3C2 T3C1 T3C0 T3PNDA T3ENA T3PNDB T3ENB
Bit 7 Bit 0
The T3CNTRL control register contains the following bits:
T3C3 Timer T3 mode control bit
T3C2 Timer T3 mode control bit
T3C1 Timer T3 mode control bit
T3C0 Timer T3 Start/Stop control in timer
modes 1 and 2, T3 Underflow Interrupt Pending Flag in timer mode 3
T3PNDA Timer T3 Interrupt Pending Flag (Autoreload
RA in mode 1, T3 Underflow in mode 2, T3A
capture edge in mode 3)
T3ENA Timer T3 Interrupt Enable for Timer Underflow
or T3A Input capture edge
T3PNDB Timer T3 Interrupt Pending Flag for T3B cap-
ture edge
T3ENB Timer T3 Interrupt Enable for Timer Underflow
or T3B Input capture edge
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