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COP680C
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National Semiconductor COP680C, COP681C, COP682C, COP880C, COP881C Technical data

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COP680C/COP681C/COP682C/COP880C/COP881C/ COP882C/COP980C/COP981C/COP982C Microcontrollers
General Description
Key Features
Y
16-bit multi-function timer supporting Ð PWM mode Ð External event counter mode Ð Input capture mode
Y
4 kbytes of ROM
Y
128 bytes of RAM
I/O Features
Y
Memory mapped I/O
Y
Software selectable I/O options (TRI-STATEÉ, Push­Pull, Weak Pull-Up Input, High Impedance Input)
Y
High current outputs (8 pins)
TM
TM
microcontroller family. They are fully
serial I/O, a 16-bit timer/counter with
August 1996
Y
Schmitt trigger inputs on Port G
Y
MICROWIRE PLUS serial I/O
Y
Packages: Ð 20 DIP/SO with 16 I/O pins Ð 28 DIP/SO with 24 I/O pins Ð 40 DIP, 36 I/O pins Ð 44 PLCC, 36 I/O pins
CPU/Instruction Set Features
Y
1 ms instruction cycle time
Y
Three multi-source interrupts servicing Ð External interrupt with selectable edge Ð Timer interrupt Ð Software interrupt
Y
Versatile and easy to use instruction set
Y
8-bit Stack Pointer (SP)Ðstack in RAM
Y
Two 8-bit Register Indirect Data Memory Pointers (B and X)
Fully Static CMOS
Y
Low current drain (typicallyk1 mA)
Y
Single supply operation: 2.5V to 6.0V
Y
Temperature ranges: 0§Cto70§C,b40§Ctoa85§C,
b
55§Ctoa125§C.
Development Support
Y
Emulation and OTP devices
Y
Real time emulation and full program debug offered by MetaLink’s development system
COP680C/COP681C/COP682C/COP880C/COP881C/COP882C/COP980C/COP981C/COP982C
Microcontrollers
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
TM
COPS
, HPCTM, MICROWIRETMand MICROWIRE/PLUSTMare trademarks of National Semiconductor Corporation.
TM
iceMASTER PC-XT
C
1996 National Semiconductor Corporation RRD-B30M106/Printed in U. S. A.
is a trademark of MetaLink Corporation.
and PC-ATÉare registered trademarks of International Business Machines Corporation.
É
TL/DD10802
http://www.national.com
Block Diagram
FIGURE 1
TL/DD/10802– 1
http://www.national.com 2
Connection Diagrams
Dual-In-Line Package
TL/DD/10802– 23
Top View
Order Number COP882C-XXX/N, COP982C-XXX/N,
COP882C-XXX/WM, COP982C-XXX/WM,
COP982C-XXX/N or COP982CH-XXX/WM
Dual-In-Line Package
Dual-In-Line Package (N)
and 28 Wide SO (WM)
TL/DD/10802– 5
Top View
Order Number COP881C-XXX/N, COP981C-XXX/N,
COP881C-XXX/WM, COP981C-XXX/WM,
COP981CH-XXX/N or COP981CH-XXX/WM
Plastic Chip Carrier
Top View
TL/DD/10802– 4
Order Number COP680C-XXX/N, COP880C-XXX/N,
COP980C-XXX/N or COP980CH-XXX/N
FIGURE 3. Connection Diagrams
Top View
TL/DD/10802– 3
Order Number COP680C-XXX/V, COP880C-XXX/V,
COP980C-XXX/V or COP980CH-XXX/V
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COP980C/COP981C/COP982C
Absolute Maximum Ratings
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage (V
Voltage at any Pin
)7V
CC
b
0.3V to V
CC
a
0.3V
Total Current into VCCPin (Source) 50 mA
DC Electrical Characteristics COP98xC; 0
Parameter Condition Min Typ Max Units
Operating Voltage
98XC 2.3 4.0 V 98XCH 4.0 6.0 V
Power Supply Ripple (Note 1) Peak to Peak 0.1 V
Supply Current
e
CKI
10 MHz V
CKIe4 MHz V
e
CKI
4 MHz V
e
CKI
1 MHz V (Note 2) HALT Current V (Note 3) V
Input Levels
RESET
, CKI Logic High 0.9 V Logic Low 0.1 V
All Other Inputs
Logic High 0.7 V Logic Low 0.2 V
Hi-Z Input Leakage V Input Pullup Current V
G Port Input Hysteresis 0.35 V
Output Current Levels D Outputs
Source V
Sink V
All Others
Source (Weak Pull-Up) V
Source (Push-Pull Mode) V
Sink (Push-Pull Mode) V
TRI-STATE Leakage V
Allowable Sink/Source Current Per Pin
D Outputs (Sink) 15 mA All Others 3mA
Maximum Input Current (Note 4) Without Latchup (Room Temp) Room Temp
RAM Retention Voltage, Vr 500 ns Rise and (Note 5) Fall Time (Min) 2.0 V
Input Capacitance 7pF
Load Capacitance on D2 1000 pF
e
6V, tce1 ms 6.0 mA
CC
e
6V, tce2.5 ms 4.4 mA
CC
e
4.0V, tce2.5 ms 2.2 mA
CC
e
4.0V, tce10 ms 1.4 mA
CC
e
6V, CKIe0 MHz
CC
e
4.0V, CKIe0 MHz
CC
e
6.0V
CC
e
6.0V, V
CC
e
CC
e
V
CC
e
CC
e
V
CC
e
CC
e
V
CC
e
CC
e
V
CC
e
CC
e
V
CC
e
CC
4.5V, V
2.3V, V
4.5V, V
2.3V, V
4.5V, V
2.3V, V
4.5V, V
2.3V, V
4.5V, V
2.3V, V
6.0V
IN
OH OH OL OL
OH OH OH OH OL OL
Total Current out of GND Pin (Sink) 60 mA
Storage Temperature Range
b
65§Ctoa140§C
Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electri­cal specifications are not ensured when operating the de­vice at absolute maximum ratings.
s
CsT
§
e
0V
e
3.8V
e
1.6V
e
1.0V 10 mA
e
0.4V 2 mA
e
3.2V
e
1.6V
e
3.8V
e
1.6V
e
0.4V 1.6 mA
e
0.4V 0.7
a
70§C unless otherwise specified
A
CC
CC
b
1.0
b
40
b
0.4 mA
b
0.2 mA
b
10
b
2.5
b
0.4 mA
b
0.2
b
1.0
CC
k
0.7 8 mA
k
0.4 5 mA
CC
CC
a
1.0 mA
b
250 mA
CC
b
110 mA
b
33 mA
a
1.0 mA
g
100 mA
V
V V
V V
V
http://www.national.com 4
COP980C/COP981C/COP982C
DC Electrical Characteristics
Note 1: Rate of voltage change must be less than 0.5V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V
and tied to ground, all outputs low and tied to ground.
Note 4: Pins G6 and RESET have sink current to V resistance to V
Note 5: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously.
CC
are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCCand the pins will
when biased at voltages greater than VCC(the pins do not have source current when biased at a voltage below VCC). The effective
CC
is 750X (typ). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
AC Electrical Characteristics 0
(Continued)
CsT
§
A
s
a
70§C unless otherwise specified
, L, C and G ports TRI-STATE
CC
Parameter Condition Min Typ Max Units
Instruction Cycle Time (tc)
Crystal/Resonator or External V (Div-by 10) 2.3V R/C Oscillator Mode V (Div-by 10) 2.3V
t
4.0V 1 DC ms
CC
CC
s
s
V
4.0V 2.5 DC ms
CC
t
4.0V 3 DC ms
s
s
V
4.0V 7.5 DC ms
CC
CKI Clock Duty Cycle (Note 6) freMax 40 60 %
Rise Time (Note 6) fr Fall Time (Note 6) fr
e
10 MHz Ext Clock 12 ns
e
10 MHz Ext Clock 8 ns
Inputs
t
SETUP
t
HOLD
Output Propagation Delay C t
PD1,tPD0
SO, SK V
All Others V
MICROWIRETMSetup Time (t MICROWIRE Hold Time (t MICROWIRE Output
Propagation Delay (t
UWS)
UWH)
) 220 ns
UPD
t
V
4.0V 200 ns
CC
2.3V V
CC
2.3VsV
L
CC
2.3V
CC
2.3V
s
s
V
4.0V 500 ns
CC
t
4.0V 60 ns
s
4.0V 150 ns
CC
e
100 pF, R
t
4.0V 0.7 ms
s
V
t
4.0V 1 ms
s
V
e
2.2 kX
L
s
4.0V 1.75 ms
CC
s
4.0V 2.5 ms
CC
20 ns 56 ns
Input Pulse Width
Interrupt Input High Time t Interrupt Input Low Time t Timer Input High Time t Timer Input Low Time t
C
C
C
C
Reset Pulse Width 1.0 ms
Note 6: Parameter characterized but not production tested.
http://www.national.com5
COP880C/COP881C/COP882C
Absolute Maximum Ratings
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage (V
Voltage at any Pin
Total Current into VCCPin (Source) 50 mA
)7V
CC
b
0.3V to V
CC
a
0.3V
Total Current out of GND Pin (Sink) 60 mA
Storage Temperature Range
b
65§Ctoa140§C
Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electri­cal specifications are not ensured when operating the de­vice at absolute maximum ratings.
DC Electrical Characteristics COP88xC;
b
40§CsT
s
a
85§C unless otherwise specified
A
Parameter Condition Min Typ Max Units
Operating Voltage 2.5 6.0 V Power Supply Ripple (Note 1) Peak to Peak 0.1 V
Supply Current
e
CKI
10 MHz V
e
CKI
4 MHz V
e
CKI
4 MHz V
CKIe1 MHz V
(Note 2) HALT Current V (Note 3) V
e
6V, tce1 ms 6.0 mA
CC
e
6V, tce2.5 ms 4.4 mA
CC
e
4.0V, tce2.5 ms 2.2 mA
CC
e
4.0V, tce10 ms 1.4 mA
CC
e
6V, CKIe0 MHz
CC
e
3.5V, CKIe0 MHz
CC
k
110 mA
k
0.5 6 mA
CC
V
Input Levels
RESET
, CKI Logic High 0.9 V Logic Low 0.1 V
CC
All Other Inputs
Logic High 0.7 V Logic Low 0.2 V
Hi-Z Input Leakage V Input Pullup Current V
CC CC
e e
6.0V
6.0V, V
e
0V
IN
CC
b
2
b
40
a
b
250 mA
G Port Input Hysteresis 0.35 V
CC
CC
2 mA
CC
V V
V V
V
Output Current Levels D Outputs
Source V
Sink V
All Others
Source (Weak Pull-Up) V
Source (Push-Pull Mode) V
Sink (Push-Pull Mode) V
TRI-STATE Leakage V
e
4.5V, V
CC
e
V
2.5V, V
CC
e
4.5V, V
CC
e
V
2.5V, V
CC
e
4.5V, V
CC
e
V
2.5V, V
CC
e
4.5V, V
CC
e
V
2.5V, V
CC
e
4.5V, V
CC
e
V
2.5V, V
CC
e
6.0V
CC
e
3.8V
OH
e
1.8V
OH
e
1.0V 10 mA
OL
e
0.4V 2 mA
OL
e
3.2V
OH
e
1.8V
OH
e
3.8V
OH
e
1.8V
OH
e
0.4V 1.6 mA
OL
e
0.4V 0.7
OL
b
0.4 mA
b
0.2 mA
b
10
b
2.5
b
0.4 mA
b
0.2
b
2.0
b
110 mA
b
33 mA
a
2.0 mA
Allowable Sink/Source Current Per Pin
D Outputs (Sink) 15 mA All Others 3mA
Maximum Input Current (Note 4) Without Latchup (Room Temp) Room Temp
g
100 mA
RAM Retention Voltage, Vr 500 ns Rise and (Note 5) Fall Time (Min) 2.0 V
Input Capacitance 7pF
Load Capacitance on D2 1000 pF
http://www.national.com 6
COP880C/COP881C/COP882C
DC Electrical Characteristics
Note 1: Rate of voltage change must be less than 0.5V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V
and tied to ground, all outputs low and tied to ground.
Note 4: Pins G6 and RESET have sink current to V resistance to V
Note 5: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously.
CC
are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCCand the pins will
when biased at voltages greater than VCC(the pins do not have source current when biased at a voltage below VCC). The effective
CC
is 750X (typ). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
AC Electrical Characteristics
(Continued)
b
40§CsT
s
a
85§C unless otherwise specified
A
, L, C and G ports TRI-STATE
CC
Parameter Condition Min Typ Max Units
Instruction Cycle Time (tc)
Crystal/Resonator or External V (Div-by 10) 2.5V R/C Oscillator Mode V (Div-by 10) 2.5V
t
4.5V 1 DC ms
CC
CC
k
s
V
4.5V 2.5 DC ms
CC
t
4.5V 3 DC ms
k
s
V
4.5V 7.5 DC ms
CC
CKI Clock Duty Cycle (Note 6) freMax 40 60 %
Rise Time (Note 6) fr Fall Time (Note 6) fr
e
10 MHz Ext Clock 12 ns
e
10 MHz Ext Clock 8 ns
Inputs
t
SETUP
t
HOLD
Output Propagation Delay C t
PD1,tPD0
SO, SK V
All Others V
MICROWIRETMSetup Time (t MICROWIRE Hold Time (t MICROWIRE Output
Propagation Delay (t
UWS)
UWH)
) 220 ns
UPD
t
V
4.5V 200 ns
CC
2.5V V
CC
2.5VsV
L
CC
2.5V
CC
2.5V
k
s
V
4.5V 500 ns
CC
t
4.5V 60 ns
k
4.5V 150 ns
CC
e
100 pF, R
t
4.5V 0.7 ms
s
V
t
4.5V 1 ms
s
V
e
2.2 kX
L
k
4.5V 1.75 ms
CC
k
4.5V 2.5 ms
CC
20 ns 56 ns
Input Pulse Width
Interrupt Input High Time t Interrupt Input Low Time t Timer Input High Time t Timer Input Low Time t
C
C
C
C
Reset Pulse Width 1.0 ms
Note 6: Parameter characterized but not production tested.
Timing Diagram
FIGURE 2. MICROWIRE/PLUS Timing
TL/DD/10802– 2
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COP680C/COP681C/COP682C
Absolute Maximum Ratings
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage (V
Voltage at Any Pin
Total Current into VCCPin (Source) 40 mA
)6V
CC
b
0.3V to V
CC
a
0.3V
Total Current Out of GND Pin (Sink) 48 mA
Storage Temperature Range
Note:
Absolute maximum ratings indicate limits beyond
b
65§Ctoa140§C
which damage to the device may occur. DC and AC electri­cal specifications are not ensured when operating the de­vice at absolute maximum ratings.
DC Electrical Characteristics COP68xC:
b
55§CsT
s
a
125§C unless otherwise specified
A
Parameter Condition Min Typ Max Units
Operating Voltage 4.5 5.5 V Power Supply Ripple (Note 1) Peak to Peak 0.1 V
CC
V
Supply Current (Note 2)
e
CKI
10 MHz V
e
CKI
4 MHz V
HALT Current (Note 3) V
e
5.5V, tce1 ms 8.0 mA
CC
e
5.5V, tce2.5 ms 4.4 mA
CC
e
5.5V, CKIe0 MHz
CC
k
10 30 mA
Input Levels
RESET
, CKI Logic High 0.9 V Logic Low 0.1 V
CC
All Other Inputs
Logic High 0.7 V Logic Low 0.2 V
Hi-Z Input Leakage V Input Pullup Current V
CC
CC
e e
5.5V
5.5V, V
e
0V
IN
CC
b
5
b
35
a
b
300 mA
G Port Input Hysteresis 0.35 V
CC
CC
5 mA
CC
V V
V V
V
Output Current Levels
D Outputs
Source V Sink V
All Others
Source (Weak Pull-Up) V Source (Push-Pull Mode) V Sink (Push-Pull Mode) V TRI-STATE Leakage V
CC
CC
CC
CC
CC
CC
e e
e e e e
4.5V, V
4.5V, V
4.5V, V
4.5V, V
4.5V, V
5.5V
e
3.8V
OH
e
1.0V 9 mA
OL
e
3.2V
OH
e
3.2V
OH
e
0.4V 1.4 mA
OL
b
0.35 mA
b
9
b
0.35 mA
b
5.0
b
120 mA
a
5.0 mA
Allowable Sink/Source Current per Pin
D Outputs (Sink) 12 mA All Others 2.5 mA
Maximum Input Current (Room Temp)
without Latchup (Note 4) Room Temp
g
100 mA
RAM Retention Voltage, Vr (Note 5) 500 ns Rise and Fall Time (Min) 2.5 V
Input Capacitance 7pF
Load Capacitance on D2 1000 pF
Note 1: Rate of voltage change must be less than 0.5V/ms.
Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 3: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V
and tied to ground, all outputs low and tied to ground.
Note 4: Pins G6 and RESET have sink current to V resistance to V
Note 5: To maintain RAM integrity, the voltage must not be dropped or raised instantaneously.
CC
are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCCand the pins will
when biased at voltages greater than VCC(the pins do not have source current when biased at a voltage below VCC). The effective
CC
is 750X (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
, L and G ports TRI-STATE
CC
http://www.national.com 8
COP680C/COP681C/COP682C
AC Electrical Characteristics
b
55§CsT
s
a
125§C unless otherwise specified
A
Parameter Condition Min Typ Max Units
Instruction Cycle Time (tc)
Ext. or Crystal/Resonant V (Div-by 10)
t
4.5V 1 DC ms
CC
CKI Clock Duty Cycle freMax 40 60 % (Note 6)
Rise Time (Note 6) fre10 MHz Ext Clock 12 ns Fall Time (Note 6) fr
MICROWIRE Setup Time (t MICROWIRE Hold Time (t MICROWIRE Output Valid Time (t
UPD
)
)20ns
UWS
)56ns
UWH
e
10 MHz Ext Clock 8 ns
220 ns
Input Pulse Width
Interrupt Input High Time t Interrupt Input Low Time t Timer Input High Time t Timer Input Low Time t
C
C
C
C
Reset Pulse Width 1 ms
Note 6: Parameter characterized but not production tested.
http://www.national.com9
Typical Performance Characteristics (
b
40§CsT
s
a
85§C)
A
HallÐI
DD
TL/DD/10802– 16
Port L/C/G Weak Pull-Up Source Current
TL/DD/10802– 18
Port L/C/G Push-Pull Sink Current
DynamicÐIDD(Crystal Clock Option)
TL/DD/10802– 17
Port L/C/G Push-Pull Source Current
TL/DD/10802– 19
Port D Source Current
TL/DD/10802– 20
Port D Sink Current
http://www.national.com 10
TL/DD/10802– 21
TL/DD/10802– 22
Pin Descriptions
VCCand GND are the power supply pins.
CKI is the clock input. This can come from an external source, a R/C generated oscillator or a crystal (in conjunc­tion with CKO). See Oscillator description.
RESET
is the master reset input. See Reset description.
PORT I is an 8-bit Hi-Z input port. The 28-pin device does not have a full complement of Port I pins. The unavailable pins are not terminated i.e., they are floating. A read opera­tion for these unterminated pins will return unpredictable values. The user must ensure that the software takes this into account by either masking or restricting the accesses to bit operations. The unterminated Port I pins will draw power only when addressed.
PORT L is an 8-bit I/O port.
PORT C is a 4-bit I/O port.
There are two registers associated with the L and C ports: a data register and a configuration register. Therefore, each L and C I/O bit can be individually configured under software control as shown below:
Config. Data Ports L and C Setup
0 0 Hi-Z Input (TRI-STATE Output) 0 1 Input with Pull-Up (Weak One Output) 1 0 Push-Pull Zero Output 1 1 Push-Pull One Output
On the 28-pin part, it is recommended that all bits of Port C be configured as outputs.
PORT G is an 8-bit port with 6 I/O pins (G0– G5) and 2 input pins (G6, G7). All eight G-pins have Schmitt Triggers on the inputs.
There are two registers associated with the G port: a data register and a configuration register. Therefore, each G port bit can be individually configured under software control as shown below:
Config. Data Port G Setup
0 0 Hi-Z Input (TRI-STATE Output) 0 1 Input with Pull-Up (Weak One Output) 1 0 Push-Pull Zero Output 1 1 Push-Pull One Output
Since G6 and G7 are input only pins, any attempt by the user to configure them as outputs by writing a one to the configuration register will be disregarded. Reading the G6 and G7 configuration bits will return zeros. The device will be placed in the HALT mode by writing to the G7 bit in the G-port data register.
Six pins of Port G have alternate features:
G0 INTR (an external interrupt)
G3 TIO (timer/counter input/output)
G4 SO (MICROWIRE serial data output)
G5 SK (MICROWIRE clock I/O)
G6 SI (MICROWIRE serial data input)
G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input (general purpose input)
Pins G1 and G2 currently do not have any alternate func­tions.
CC
to pre-
Functional Description
Figure 1
shows the block diagram of the internal architec­ture. Data paths are illustrated in simplified form to depict how the various logic elements communicate with each oth­er in implementing the instruction set of the device.
ALU AND CPU REGISTERS
The ALU can do an 8-bit addition, subtraction, logical or shift operation in one cycle time.
There are five CPU registers:
A is the 8-bit Accumulator register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is the 8-bit address register, can be auto incremented or decremented.
X is the 8-bit alternate address register, can be incremented or decremented.
PROGRAM MEMORY
Program memory consists of 4096 bytes of ROM. These bytes may hold program instructions or constant data. The program memory is addressed by the 15-bit program coun­ter (PC). ROM can be indirectly read by the LAID instruction for table lookup.
DATA MEMORY
The device has 128 bytes of RAM. Sixteen bytes of RAM are mapped as ‘‘registers’’ that can be loaded immediately, decremented or tested. Three specific registers: B, X and SP are mapped into this space, the other bytes are available for general usage.
The instruction set permits any bit in memory to be set, reset or tested. All I/O and registers (except the A & PC) are memory mapped; therefore, I/O bits and register bits can be directly and individually set, reset and tested. A is not mem­ory mapped, but bit operations can be still performed on it.
Note: RAM contents are undefined upon power-up.
RESET
The RESET troller. Initialization will occur whenever the RESET pulled low. Upon initialization, the ports L, G and C are placed in the TRI-STATE mode and the Port D is set high. The PC, PSW and CNTRL registers are cleared. The data and configuration registers for Ports L, G and C are cleared.
The external RC network shown in Figure 4 should be used to ensure that the RESET supply to the chip stabilizes.
input when pulled low initializes the microcon-
input is
pin is held low until the power
http://www.national.com11
Functional Description (Continued)
Table II shows the variation in the oscillator frequencies as functions of the component (R and C) values.
RCt5X Power Supply Rise Time
TL/DD/10802– 6
FIGURE 4. Recommended Reset Circuit
OSCILLATOR CIRCUITS
Figure 5
shows the three clock oscillator configurations.
A. CRYSTAL OSCILLATOR
The device can be driven by a crystal clock. The crystal network is connected between the pins CKI and CKO.
Table I shows the component values required for various standard crystal values.
B. EXTERNAL OSCILLATOR
CKI can be driven by an external clock signal. CKO is avail­able as a general purpose input and/or HALT restart con­trol.
C. R/C OSCILLATOR
CKI is configured as a single pin RC controlled Schmitt trig­ger oscillator. CKO is available as a general purpose input
FIGURE 5. Crystal and R-C Connection Diagrams
OSCILLATOR MASK OPTIONS
The device can be driven by clock inputs between DC and 10 MHz.
and/or HALT restart control.
TABLE I. Crystal Oscillator Configuration, T
e
25§C
A
R1 R2 C1 C2 CKI Freq
(kX)(MX) (pF) (pF) (MHz)
0 1 30 30– 36 10 V 0 1 30 30– 36 4 V
5.6 1 200 100– 150 0.455 V
TABLE II. RC Oscillator Configuration, T
e
25§C
A
R C CKI Freq. Instr. Cycle
(kX) (pF) (MHz) (ms)
3.3 82 2.2 to 2.7 3.7 to 4.6 V
5.6 100 1.1 to 1.3 7.4 to 9.0 V
6.8 100 0.9 to 1.1 8.8 to 10.8 V
Note: (R/C Oscillator Configuration): 3ksRs200k, 50 pFsCs200 pF.
TL/DD/10802– 7
Conditions
e
CC
e
2.5V
CC
e
CC
Conditions
e
5V
CC
e
5V
CC
e
5V
CC
5V
5V
http://www.national.com 12
Functional Description (Continued)
The device has three mask options for configuring the clock input. The CKI and CKO pins are automatically configured upon selecting a particular option.
Ð Crystal (CKI/10); CKO for crystal configuration
Ð External (CKI/10); CKO available as G7 input
Ð R/C (CKI/10); CKO available as G7 input
G7 can be used either as a general purpose input or as a control input to continue from the HALT mode.
HALT MODE
The device supports a power saving mode of operation: HALT. The controller is placed in the HALT mode by setting the G7 data bit, alternatively the user can stop the clock input. In the HALT mode all internal processor activities in­cluding the clock oscillator are stopped. The fully static ar­chitecture freezes the state of the controller and retains all information until continuing. In the HALT mode, power re­quirements are minimal as it draws only leakage currents and output current. The applied voltage (V creased down to Vr (minimum RAM retention voltage) with­out altering the state of the machine.
INTERRUPTS
There are three interrupt sources, as shown below.
A maskable interrupt on external G0 input (positive or nega­tive edge sensitive under software control)
A maskable interrupt on timer underflow or timer capture
A non-maskable software/error interrupt on opcode zero
INTERRUPT CONTROL
The GIE (global interrupt enable) bit enables the interrupt function. This is used in conjunction with ENI and ENTI to select one or both of the interrupt sources. This bit is reset when interrupt is acknowledged.
) may be de-
CC
ENI and ENTI bits select external and timer interrupt re­spectively. Thus the user can select either or both sources to interrupt the microcontroller when GIE is enabled.
IEDG selects the external interrupt edge (0
e
1
falling edge). The user can get an interrupt on both
e
rising edge,
rising and falling edges by toggling the state of IEDG bit after each interrupt.
IPND and TPND bits signal which interrupt is pending. After interrupt is acknowledged, the user can check these two bits to determine which interrupt is pending. This permits the interrupts to be prioritized under software. The pending flags have to be cleared by the user. Setting the GIE bit high inside the interrupt subroutine allows nested interrupts.
The software interrupt does not reset the GIE bit. This means that the controller can be interrupted by other inter­rupt sources while servicing the software interrupt.
INTERRUPT PROCESSING
The interrupt, once acknowledged, pushes the program counter (PC) onto the stack and the stack pointer (SP) is decremented twice. The Global Interrupt Enable (GIE) bit is reset to disable further interrupts. The microcontroller then vectors to the address 00FFH and resumes execution from that address. This process takes 7 cycles to complete. At the end of the interrupt subroutine, any of the following three instructions return the processor back to the main pro­gram: RET, RETSK or RETI. Either one of the three instruc­tions will pop the stack into the program counter (PC). The stack pointer is then incremented twice. The RETI instruc­tion additionally sets the GIE bit to re-enable further inter­rupts.
Note: There is always the possibility of an interrupt occurring during an in-
struction which is attempting to reset the GIE bit or any other interrupt enable bit. If this occurs when a single cycle instruction is being used to reset the interrupt enable bit, the interrupt enable bit will be reset but an interrupt may still occur. This is because interrupt processing is started at the same time as the interrupt bit is being reset. To avoid this scenario, the user should always use a two, three or four cycle instruction to reset interrupt enable bits.
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Functional Description (Continued)
FIGURE 6. Interrupt Block Diagram
DETECTION OF ILLEGAL CONDITIONS
The device contains a hardware mechanism that allows it to detect illegal conditions which may occur from coding er­rors, noise and ‘brown out’ voltage drop situations. Specifi­cally it detects cases of executing out of undefined ROM area and unbalanced stack situations.
Reading an undefined ROM location returns 00 (hexadeci­mal) as its contents. The opcode for a software interrupt is also ‘00’. Thus a program accessing undefined ROM will cause a software interrupt.
Reading an undefined RAM location returns an FF (hexade­cimal). The subroutine stack grows down for each subrou­tine call. By initializing the stack pointer to the top of RAM, the first unbalanced return instruction will cause the stack pointer to address undefined RAM. As a result the program will attempt to execute from FFFF (hexadecimal), which is an undefined ROM location and will trigger a software inter­rupt.
MICROWIRE/PLUS
TM
MICROWIRE/PLUS is a serial synchronous bidirectional communications interface. The MICROWIRE/PLUS capabil­ity enables the device to interface with any of National Semiconductor’s MICROWIRE peripherals (i.e. A/D con­verters, display drivers, EEPROMS, etc.) and with other mi­crocontrollers which support the MICROWIRE/PLUS inter­face. It consists of an 8-bit serial shift register (SIO) with serial data input (SI), serial data output (SO) and serial shift clock (SK).
Figure 7
shows the block diagram of the MICRO-
WIRE/PLUS interface.
The shift clock can be selected from either an internal source or an external source. Operating the MICROWIRE/ PLUS interface with the internal clock source is called the Master mode of operation. Similarly, operating the MICRO­WIRE/PLUS interface with an external shift clock is called the Slave mode of operation.
TL/DD/10802– 8
TABLE III
SL1 SL0 SK Cycle Time
00 2t 01 4t 1x 8t
C
C
C
where,
tCis the instruction cycle clock.
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the MI­CROWIRE/PLUS arrangement to start shifting the data. It gets reset when eight data bits have been shifted. The user may reset the BUSY bit by software to allow less than 8 bits to shift. The devoce may enter the MICROWIRE/PLUS mode either as a Master or as a Slave.
Figure 8
shows how two COP880C microcontrollers and several peripherals may be interconnected using the MICROWIRE/PLUS arrange­ment.
Master MICROWIRE/PLUS Operation
In the MICROWIRE/PLUS Master mode of operation the shift clock (SK) is generated internally. The MICROWIRE/ PLUS Master always initiates all data exchanges. (See
ure 8
). The MSEL bit in the CNTRL register must be set to
Fig-
enable the SO and SK functions onto the G Port. The SO and SK pins must also be selected as outputs by setting appropriate bits in the Port G configuration register. Table IV summarizes the bit settings required for Master mode of operation.
SLAVE MICROWIRE/PLUS OPERATION
In the MICROWIRE/PLUS Slave mode of operation the SK clock is generated by an external source. Setting the MSEL bit in the CNTRL register enables the SO and SK functions onto the G Port. The SK pin must be selected as an input and the SO pin is selected as an output pin by appropriately setting up the Port G configuration register. Table IV sum­marizes the settings required to enter the Slave mode of operation.
The user must set the BUSY flag immediately upon entering the Slave mode. This will ensure that all data bits sent by the Master will be shifted properly. After eight clock pulses the BUSY flag will be cleared and the sequence may be repeated. (See
Figure 8
.)
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Functional Description (Continued)
TABLE IV
G4 G5
Config. Config.
Bit Bit
1 1 SO Int. SK SI MICROWIRE Master
0 1 TRI-STATE Int. SK SI MICROWIRE Master
1 0 SO Ext. SK SI MICROWIRE Slave
0 0 TRI-STATE Ext. SK SI MICROWIRE Slave
TIMER/COUNTER
The device has a powerful 16-bit timer with an associated 16-bit register enabling them to perform extensive timer functions. The timer T1 and its register R1 are each orga­nized as two 8-bit read/write registers. Control bits in the register CNTRL allow the timer to be started and stopped under software control. The timer-register pair can be oper­ated in one of three possible modes. Table V details various timer operating modes and their requisite control settings.
G4 G5 G6
Fun. Fun. Fun.
Operation
MODE 1. TIMER WITH AUTO-LOAD REGISTER
In this mode of operation, the timer T1 counts down at the instruction cycle rate. Upon underflow the value in the regis­ter R1 gets automatically reloaded into the timer which con­tinues to count down. The timer underflow can be pro­grammed to interrupt the microcontroller. A bit in the control register CNTRL enables the TIO (G3) pin to toggle upon timer underflows. This allow the generation of square-wave outputs or pulse width modulated outputs under software control. (See
Figure 9.
)
MODE 2. EXTERNAL COUNTER
In this mode, the timer T1 becomes a 16-bit external event counter. The counter counts down upon an edge on the TIO pin. Control bits in the register CNTRL program the counter to decrement either on a positive edge or on a negative edge. Upon underflow the contents of the register R1 are automatically copied into the counter. The underflow can also be programmed to generate an interrupt. (See
Figure 9
MODE 3. TIMER WITH CAPTURE REGISTER
Timer T1 can be used to precisely measure external fre­quencies or events in this mode of operation. The timer T1 counts down at the instruction cycle rate. Upon the occur­rence of a specified edge on the TIO pin the contents of the timer T1 are copied into the register R1. Bits in the control register CNTRL allow the trigger edge to be specified either as a positive edge or as a negative edge. In this mode the user can elect to be interrupted on the specified trigger edge. (See
Figure 10
.)
)
FIGURE 7. MICROWIRE/PLUS Block Diagram
TL/DD/10802– 9
FIGURE 8. MICROWIRE/PLUS Application
TL/DD/10802– 10
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Functional Description (Continued)
TABLE V. Timer Operating Modes
CNTRL Timer
Bits Operation Mode T Interrupt Counts
765 On
0 0 0 External Counter W/Auto-Load Reg. Timer Underflow TIO Pos. Edge 0 0 1 External Counter W/Auto-Load Reg. Timer Underflow TIO Neg. Edge 0 1 0 Not Allowed Not Allowed Not Allowed 0 1 1 Not Allowed Not Allowed Not Allowed 1 0 0 Timer W/Auto-Load Reg. Timer Underflow t 1 0 1 Timer W/Auto-Load Reg./Toggle TIO Out Timer Underflow t 1 1 0 Timer W/Capture Register TIO Pos. Edge t 1 1 1 Timer W/Capture Register TIO Neg. Edge t
TIMER PWM APPLICATION
Figure 11
shows how a minimal component D/A converter can be built out of the Timer-Register pair in the Auto-Re­load mode. The timer is placed in the ‘‘Timer with auto re­load’’ mode and the TIO pin is selected as the timer output. At the outset the TIO pin is set high, the timer T1 holds the on time and the register R1 holds the signal off time. Setting TRUN bit starts the timer which counts down at the instruc­tion cycle rate. The underflow toggles the TIO output and copies the off time into the timer, which continues to run. By
FIGURE 9. Timer/Counter Auto
TL/DD/10802– 11
Reload Mode Block Diagram
alternately loading in the on time and the off time at each successive interrupt a PWM frequency can be easily gener­ated.
C
C
C
C
FIGURE 10. Timer Capture Mode Block Diagram
TL/DD/10802– 12
http://www.national.com 16
FIGURE 11. Timer Application
TL/DD/10802– 13
Control Registers
CNTRL REGISTER (ADDRESS X’00EE)
The Timer and MICROWIRE/PLUS control register contains the following bits:
SL1 & SL0 Select the MICROWIRE/PLUS clock divide-by
IEDG External interrupt edge polarity select
MSEL Enable MICROWIRE/PLUS functions SO and
TRUN Start/Stop the Timer/Counter (1
TC3 Timer input edge polarity select (0
TC2 Selects the capture mode
TC1 Selects the timer mode
TC1 TC2 TC3 TRUN MSEL IEDG SL1 SL0
BIT 7 BIT 0
PSW REGISTER (ADDRESS X’00EF)
The PSW register contains the following select bits:
GIE Global interrupt enable
ENI External interrupt enable
BUSY MICROWIRE/PLUS busy shifting
IPND External interrupt pending
ENTI Timer interrupt enable
TPND Timer interrupt pending
C Carry Flag
HC Half carry Flag
HC C TPND ENTI IPND BUSY ENI GIE
Bit 7 Bit 0
e
(0
rising edge, 1efalling edge)
SK
stop)
e
edge, 1
falling edge)
e
run, 0
e
rising
Addressing Modes
REGISTER INDIRECT
This is the ‘‘normal’’ mode of addressing. The operand is the memory addressed by the B register or X register.
DIRECT
The instruction contains an 8-bit address field that directly points to the data memory for the operand.
IMMEDIATE
The instruction contains an 8-bit immediate field as the op­erand.
REGISTER INDIRECT (AUTO INCREMENT AND DECREMENT)
This is a register indirect mode that automatically incre­ments or decrements the B or X register after executing the instruction.
RELATIVE
This mode is used for the JP instruction, the instruction field is added to the program counter to get the new program location. JP has a range of from byte relative jump (JP tion). There are no ‘pages’ when using JP, all 15 bits of PC are used.
a
b
31 toa32 to allow a one
1 is implemented by a NOP instruc-
Memory Map
e
into data memory address space.
Address Contents
00 to 6F On Chip RAM Bytes 70 to 7F Unused RAM Address Space (Reads as all Ones)
80 to BF Expansion Space for future use
C0 to CF Expansion Space for I/O and Registers
D0 to DF On Chip I/O and Registers
D0 Port L Data Register D1 Port L Configuration Register D2 Port L Input Pins (Read Only) D3 Reserved for Port L D4 Port G Data Register D5 Port G Configuration Register D6 Port G Input Pins (Read Only) D7 Port I Input Pins (Read Only) D8 Port C Data Register D9 Port C Configuration Register DA Port C Input Pins (Read Only) DB Reserved for Port C DC Port D Data Register
DD–DF Reserved for Port D
E0 to EF On Chip Functions and Registers
E0–E7 Reserved for Future Parts
E8 Reserved
E9 MICROWIRE/PLUS Shift Register EA Timer Lower Byte EB Timer Upper Byte EC Timer Autoload Register Lower Byte ED Timer Autoload Register Upper Byte EE CNTRL Control Register EF PSW Register
F0 to FF On Chip RAM Mapped as Registers
FC X Register FD SP Register FE B Register
Reading unused memory locations below 7FH will return all ones. Reading other unused memory locations will return undefined data.
http://www.national.com17
Instruction Set
REGISTER AND SYMBOL DEFINITIONS
Registers
A 8-bit Accumulator register B 8-bit Address register X 8-bit Address register SP 8-bit Stack pointer register PC 15-bit Program counter register PU upper 7 bits of PC PL lower 8 bits of PC C 1-bit of PSW register for carry HC Half Carry GIE 1-bit of PSW register for global interrupt enable
Instruction Set
ADD add AwAaMemI ADC add with carry A
SUBC subtract with carry A
AND Logical AND A OR Logical OR A XOR Logical Exclusive-OR A IFEQ IF equal Compare A and MemI, Do next if A IFGT IF greater than Compare A and MemI, Do next if AlMemI IFBNE IF B not equal Do next if lower 4 bits of B DRSZ Decrement Reg. ,skip if zero Reg SBIT Set bit 1 to bit,
RBIT Reset bit 0 to bit,
IFBIT If bit If bit,
X Exchange A with memory AÝMem LD A Load A with memory A LD mem Load Direct memory Immed. Mem LD Reg Load Register memory Immed. Reg
X Exchange A with memory[B X Exchange A with memory[X LD A Load A with memory[B LD A Load A with memory[X LD M Load Memory Immediate
CLRA Clear A Aw0 INCA Increment A A DECA Decrement A A LAID Load A indirect from ROM A DCORA DECIMAL CORRECT A A RRCA ROTATE A RIGHT THRU C C SWAPA Swap nibbles of A A7...A4 SC Set C C RC Reset C C IFC If C If C is true, do next instruction IFNC If not C If C is not true, do next instruction
JMPL Jump absolute long PCwii (iie15 bits, 0 to 32k) JMP Jump absolute PC11..0 JP Jump relative short PC JSRL Jump subroutine long JSR Jump subroutine JID Jump indirect PL RET Return from subroutine SP RETSK Return and Skip SP RETI Return from Interrupt SPa2,PL INTR Generate an interrupt NOP No operation PC
]
] ] ]
Symbols
[B]
Memory indirectly addressed by B register
[X]
Memory indirectly addressed by X register Mem Direct address memory or[B MemI Direct address memory or[B]or Immediate data Imm 8-bit Immediate data Reg Register memory: addresses F0 to FF (Includes B, X
and SP) Bit Bit number (0 to 7)
w
Loaded with
Ý
Exchanged with
w
AaMemIaC, CwCarry
w
Half Carry
HC
w
AaMemIaC, CwCarry
w
Half Carry
HC
w
A and MemI
w
A or MemI
w
A xor MemI
w
Regb1, skip if Reg goes to 0
e
Mem (bit
Mem
Mem is true, do next instr.
A A A A
[B]
[SP] [SP]
[SP]
0 to 7 immediate)
w
MemI
w
Imm
w
Imm
[B]
Ý
[X]
Ý
[B]
w
w
w
w
w
w
xA7x
w
w
w
a a
(B
[X]
(X
w
Imm (BwBg1)
Aa1 Ab1 ROM(PU,A) BCD correction (follows ADC, SUBC)
Ý
1, HCw1 0, HCw0
w
i(ie12 bits)
w
PCar(risb31 toa32, not 1)
w
PL,[SP-1
w
PL,[SP-1
ROM(PU,A)
2,PL
w
2,PL
w
w
w
PL,[SPb1
w
PCa1
i
w
Bg1)
(B
w
Xg1)
(X
w
Bg1)
w
Xg1)
...xA0xC
A3...A0
]
w
PU,SP-2,PCwii
]
w
PU,SP-2,PC11.. 0wi
[SP]
w
,PU
[SP]
w
,PU
[SP]
w
,PU
]
w
PU,SP-2,PCw0FF
]
e
MemI
Imm
[
]
SP-1
[
SP-1],Skip next instruction
[
SP-1],GIE
w
1
http://www.national.com 18
OPCODE LIST Bits 3–0
21
32
43
54
65
76
a
a
a
a
a
17 INTR 0
18 JP
19 JP
20 JP
21 JP
a
a
a
a
a
0400-04FF 0400-04FF
22 JP
a
0500-05FF 0500-05FF
a
23 JP
a
0600-06FF 0600-06FF
87
a
24 JP
a
a
a
98
25 JP
0800-08FF 0800-08FF
10 9
a
26 JP
a
0900-09FF 0900-09FF
11 A
a
27 JP
a
0A00-0AFF 0A00-0AFF
12 B
a
28 JP
a
0B00-0BFF 0B00-0BFF
13 C
a
29 JP
a
0C00-0CFF 0C00-0CFF
14 D
a
30 JP
a
0D00-0DFF 0D00-0DFF
16 F
15 E
a
a
31 JP
32 JP
a
a
0F00-0FFF 0F00-0FFF
0E00–0EFF 0E00 –0EFF
]
]
B
B
[
* 0000-00FF 0000-00FF
* 0100-01FF 0100-01FF
* 0200-02FF 0200-02FF
* 0300-03FF 0300-03FF
]
]
]
]
]
B
B
B
[
Bits 7–4
[
1,
0,
]
]
B
[
B
[
i
iA,
Ý
Ý
*
i DRSZ 0F0 RRCA RC ADC A, ADC A, IFBIT LD B, 0F IFBNE 0 JSR JMP JP
i DRSZ 0F1 SC SUBC A, SUBC IFBIT LD B, 0E IFBNE 1 JSR JMP JP
Ý
i DRSZ 0F2 X A, X A, IFEQ A, IFEQ IFBIT LD B, 0D IFBNE 2 JSR JMP JP
Ý
Ý
[
2,
]
B
[
iA,
] Ý
a
B
][
a
X
[
i DRSZ 0F3 X A, X A, IFGT A, IFGT IFBIT LD B, 0C IFBNE 3 JSR JMP JP
Ý
B
[
3,
]
B
[
iA,
] Ý
b
B
][
b
X
[
i DRSZ 0F4 LAID ADD A, ADD IFBIT CLRA LD B, 0B IFBNE 4 JSR JMP JP
Ý
B
[
4,
]
B
[
iA,
Ý
*
i DRSZ 0F5 JID AND A, AND IFBIT SWAPA LD B, 0A IFBNE 5 JSR JMP JP
Ý
]
B
[
5,
]
B
[
iA,
Ý
*
i DRSZ 0F6 X A, X A, XOR A, XOR IFBIT DCORA LD B, 9 IFBNE 6 JSR JMP JP
Ý
* 0700-07FF 0700-07FF
]
]
B
B
[
[
6,
7,
]
]
B
B
[
[
iA,
iA,
Ý
Ý
]
B
][
X
**
[
i DRSZ 0F7 OR A, OR IFBIT LD B, 8 IFBNE 7 JSR JMP JP
Ý
i DRSZ 0F8 NOP LD A, IFC SBIT RBIT LD B, 7 IFBNE 8 JSR JMP JP
Ý
[
0,
1,
]
]
B
B
[
[
i0,
Ý
*
** * 1,
i DRSZ 0FA LD A, LD A, LD INCA SBIT RBIT LD B, 5 IFBNE 0A JSR JMP JP
i DRSZ 0F9 IFNC SBIT RBIT LD B, 6 IFBNE 9 JSR JMP JP
Ý
Ý
]
]
B
B
[
[
3,
2,
]
]
B
B
[
[
i2,
i3,
Ý
Ý
,
,
]
]
a
b
B
B
][
][
a
b
B
B
][
][
a
b
X
X
[
[
i DRSZ 0FB LD A, LD A, LD DECA SBIT RBIT LD B, 4 IFBNE 0B JSR JMP JP
Ý
]
B
[
4,
]
B
[
i * 4,
Ý
i DRSZ 0FD DIR JSRL LD A, RETSK SBIT RBIT LD B, 2 IFBNE 0D JSR JMP JP
i DRSZ 0FC LD Md, JMPL X A,Md SBIT RBIT LD B, 3 IFBNE 0C JSR JMP JP
Ý
Ý
]
B
[
5,
]
B
[
Md 5,
i DRSZ 0FE LD A, LD A, LD RET SBIT RBIT LD B, 1 IFBNE 0E JSR JMP JP
Ý
]
]
B
B
[
[
7,
6,
]
]
B
B
[
[
i6,
Ý
,
]
B
][
B
][
X
** * 7,
[
1 DRSZ 0FF RETI SBIT RBIT LD B, 0 IFBNE 0F JSR JMP JP
Ý
FE D C BA 9 87 6 5 4 3 2 1 0
JP -15 JP -31 LD 0F0,
JP -14 JP -30 LD 0F1,
JP -13 JP -29 LD 0F2,
JP -12 JP -28 LD 0F3,
JP -11 JP -27 LD 0F4,
JP -10 JP -26 LD 0F5,
JP -9 JP -25 LD 0F6,
JP -8 JP -24 LD 0F7,
JP -7 JP -23 LD 0F8,
JP -6 JP -22 LD 0F9,
JP -5 JP -21 LD 0FA,
JP -4 JP -20 LD 0FB,
JP -3 JP -19 LD 0FC,
JP -2 JP -18 LD 0FD,
JP -1 JP -17 LD 0FE,
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JP -0 JP -16 LD 0FF,
where, i is the immediate data Md is a directly addressed memory location * is an unused opcode (see following table)
Instruction Execution Time
Most instructions are single byte (with immediate address­ing mode instruction taking two bytes).
Most single instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be skipped, where x equals the number of bytes in the skipped instruction opcode.
See the BYTES and CYCLES per INSTRUCTION table for details.
Arithmetic and Logic Instructions
[B]
ADD 1/1 3/4 2/2 ADC 1/1 3/4 2/2 SUBC 1/1 3/4 2/2 AND 1/1 3/4 2/2 OR 1/1 3/4 2/2 XOR 1/1 3/4 2/2 IFEQ 1/1 3/4 2/2 IFGT 1/1 3/4 2/2 IFBNE 1/1 DRSZ 1/3
SBIT 1/1 3/4 RBIT 1/1 3/4 IFBIT 1/1 3/4
Memory Transfer Instructions
Register Register Indirect
Indirect Direct Immed. Auto Incr & Decr
[B][X][
XA,* 1/1 1/3 2/3 1/2 1/3 LD A,* 1/1 1/3 2/3 2/2 1/2 1/3 LD B,Imm 1/1 (If B LD B,Imm 2/3 (If B LD Mem,Imm 2/2 3/3 2/2 LD Reg,Imm 2/3
l
e
*
Memory location addressed by B or X or directly.
BYTES and CYCLES per INSTRUCTION
The following table shows the number of bytes and cycles for each instruction in the format of byte/cycle.
Direct Immed.
a
b
a,Xb
][
B
,B
X
]
k
16)
l
15)
Instructions UsingA&C
CLRA 1/1 INCA 1/1 DECA 1/1 LAID 1/3 DCORA 1/1 RRCA 1/1 SWAPA 1/1 SC 1/1 RC 1/1 IFC 1/1 IFNC 1/1
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Transfer of Control Instructions
JMPL 3/4 JMP 2/3 JP 1/3 JSRL 3/5 JSR 2/5 JID 1/3 RET 1/5 RETSK 1/5 RETI 1/5 INTR 1/7 NOP 1/1
BYTES and CYCLES per INSTRUCTION
The following table shows the instructions assigned to un­used opcodes. This table is for information only. The opera­tions performed are subject to change without notice. Do not use these opcodes.
Unused
Opcode Opcode
60 NOP A9 NOP 61 NOP AF LD A,[B 62 NOP B1 C 63 NOP B4 NOP
67 NOP B5 NOP 8C RET B7 X A,[X 99 NOP B9 NOP 9F LD[B], A7 X A,[B A8 NOP
Instruction
Ý
]
(Continued)
Unused
iBF LDA,
Instruction
x
HC
]
[
X
]
]
Option List
The mask programmable options are listed out below. The options are programmed at the same time as the ROM pat­tern to provide the user with hardware flexibility to use a variety of oscillator configuration.
OPTION 1: CKI INPUT
e
1 Crystal (CKI/10) CKO for crystal con-
e
2 External (CKI/10) CKO available as G7
e
3 R/C (CKI/10) CKO available as G7
OPTION 2: BONDING
e
1 44-Pin PLCC
e
2 40-Pin DIP
e
3 28-Pin SO
e
4 28-Pin DIP
The following option information is to be sent to National along with the EPROM.
Option Data
Option 1 ValueÐis: CKI Input
Option 2 ValueÐis: COP Bonding
figuration
input
input
Development Support
SUMMARY
iceMASTERTM: IM-COP8/400ÐFull feature in-circuit em-
#
ulation for all COP8 products. A full set of COP8 Basic and Feature Family device and package specific probes are available.
COP8 Debug Module: Moderate cost in-circuit emulation
#
and development programming unit.
COP8 Evaluation and Programming Unit: EPU-
#
COP880CÐlow cost In-circuit simulation and develop­ment programming unit.
Assembler: COP8-DEV-IBMA. A DOS installable cross
#
development Assembler, Linker, Librarian and Utility Software Development Tool Kit.
C Compiler: COP8C. A DOS installable cross develop-
#
ment Software Tool Kit.
OTP/EPROM Programmer Support: Covering needs
#
from engineering prototype, pilot production to full pro­duction environments.
http://www.national.com21
Development Support (Continued)
iceMASTER (IM) IN-CIRCUIT EMULATION
See
Figure 12
The iceMASTER IM-COP8/400 with its device specific COP8 Probe provides a rich feature set for developing, test­ing and maintaining product:
Real-time in-circuit emulation; full 2.4V –5.5V operation
#
range, full DC-10 MHz clock. Chip options are program­mable or jumper selectable.
Direct connection to application board by package com-
#
patible socket or surface mount assembly.
Full 32 kbyte of loadable programming space that over-
#
lays (replaces) the on-chip ROM or EPROM. On-chip RAM and I/O blocks are used directly or recreated on the probe as necessary.
Full 4k frame synchronous trace memory. Address, in-
#
struction, and 8 unspecified, circuit connectable trace lines. Display can be HLL source (e.g., C source), assem­bly or mixed.
A full 64k hardware configurable break, trace on, trace
#
off control, and pass count increment events.
Tool set integrated interactive symbolic debuggerÐsup-
#
ports both assembler (COFF) and C Compiler (.COD) linked object formats.
Real time performance profiling analysis; selectable
#
bucket definition.
for configuration.
Watch windows, content updated automatically at each
#
execution break.
Instruction by instruction memory/register changes dis-
#
played on source window when in single step operation.
Single base unit and debugger software reconfigurable to
#
support the entire COP8 family; only the probe personali­ty needs to change. Debugger software is processor cus­tomized, and reconfigured from a master model file.
Processor specific symbolic display of registers and bit
#
level assignments, configured from master model file.
Halt/Idle mode notification.
#
On-line HELP customized to specific processor using
#
master model file.
Includes a copy of COP8-DEV-IBMA assembler and link-
#
er SDK.
IM Order Information
Base Unit
IM-COP8/400-1 iceMASTER base unit,
IM-COP8/400-2 iceMASTER base unit,
iceMASTER Probe
MHW-880C20DWPC 20 DIP
MHW-880C28DWPC 28 DIP
MHW-880CJ40DWPC 40 DIP
MHW-880CJ44PWPC 44 PLCC
DIP to SO Adapters
MHW-SOIC20 20 SO
MHW-SOIC28 28 DIP
110V power supply
220V power supply
FIGURE 12. COP8 iceMASTER Environment
http://www.national.com 22
TL/DD/10802– 24
Development Support (Continued)
iceMASTER DEBUG MODULE (DM)
The iceMASTER Debug Module is a PC based, combination in-circuit emulation tool and COP8 based OTP/EPROM pro­gramming tool developed and marketed by MetaLink Corpo­ration to support the whole COP8 family of products. Nation­al is a resale vendor for these products.
See
Figure 13
The iceMASTER Debug Module is a moderate cost devel­opment tool. It has the capability of in-circuit emulation for a specific COP8 microcontroller and in addition serves as a programming tool for COP8 OTP and EPROM product fami­lies. Summary of features is as follows:
Real-time in-circuit emulation; full operating voltage
#
range operation, full DC-10 MHz clock.
All processor I/O pins can be cabled to an application
#
development board with package compatible cable to socket and surface mount assembly.
Full 32 kbyte of loadable programming space that over-
#
lays (replaces) the on-chip ROM or EPROM. On-chip RAM and I/O blocks are used directly or recreated as necessary.
100 frames of synchronous trace memory. The display
#
can be HLL source (C source), assembly or mixed. The most recent history prior to a break is available in the trace memory.
Configured break points; uses INTR instruction which is
#
modestly intrusive.
SoftwareÐonly supported features are selectable.
#
Tool set integrated interactive symbolic debuggerÐsup-
#
ports both assembler (COFF) and C Compiler (.COD) SDK linked object formats.
Instruction by instruction memory/register changes dis-
#
played when in single step operation.
Debugger software is processor customized, and recon-
#
figured from a master model file.
for configuration.
Processor specific symbolic display of registers and bit
#
level assignments, configured from master model file.
Halt/Idle mode notification.
#
Programming menu supports full product line of program-
#
mable OTP and EPROM COP8 products. Program data is taken directly from the overlay RAM.
Programming of 44 PLCC and 68 PLCC parts requires
#
external programming. adapters.
Includes wallmount power supply.
#
On-board VPP generator from 5V input or connection to
#
external supply supported. Rquires VPP level adjustment per the family programming specification (correct level is provided on an on-screen pop-down display).
On-line HELP customized to specific processor using
#
master model file.
Includes a copy of COP8-DEV-IBMA assembler and link-
#
er SDK.
DM Order Information
Debug Model Unit
COP8-DM/880C
Cable Adapters
DM-COP8/20D 20 DIP
DM-COP8/28D 28 DIP
DM-COP8/40D 40 DIP
DM-COP8/44P 44 PLCC
DIP to SO Adapters
DM-COP8/20D-SO 20 SO
DM-COP8/28D-SO 28 SO
FIGURE 13. COP8-DM Environment
TL/DD/10802– 25
http://www.national.com23
Development Support (Continued)
iceMASTER EVALUATION PROGRAMMING UNIT (EPU)
The iceMASTER EPU-COP880C is a PC based, in-circuit simulation tool to support the feature family COP8 products.
See
Figure 14
Non-real-time in-circuit simulation. Program overlay
#
memory is PC resident; instructions are downloaded over RS-232 as executed. Approximate performance is 20 kHz.
Includes a 40 pin DIP cable adapter. Other target pack-
#
ages are not supported. All processor I/O pins are ca­bled to the application development environment.
Full 32 kbyte of loadable programmable space that over-
#
lays (replaces) the on-chip ROM or EPROM. On-chip RAM and I/O blocks are used directly or recreated as necessary.
On-chip timer and WATCHDOG execution are not well
#
synchronized to the instruction simulation.
100 frames of synchronous trace memory. The display
#
can be HLL source (e.g., C source), assembly or mixed. The most recent history prior to a break is available in the trace memory.
Up to eight software configured break points; uses INTR
#
instruction which is modestly intrusive.
Common look-feel debugger software across all Meta-
#
Link productsÐonly supported features are selectable.
for configuration.
Tool set integrated interactive symbolic debuggerÐsup-
#
ports both assembler (COFF) and C Compiler (.COD) SDK linked object formats.
Instruction by instruction memory/register changes dis-
#
played when in single step operation.
Processor specific symbolic display of registers and bit
#
level assignments, configured from master model file.
Halt/Idle mode notification. Restart requires special han-
#
dling.
Programming menu supports full product line of program-
#
mable OTP and EPROM COP8 products. Only a 40 ZIF socket is available on the EPU unit. Adapters are avail­able for other part package configurations.
Integral wall mount power supply provides 5V and devel-
#
ops the required V
Includes a copy of COP8-DEV-IBMA assembler, linker
#
SDK.
Evaluation Programming Unit
EPU-COP880C Evaluation Programming Unit
General Programming Adapters
COP8-PGMA-DS 28 and 20 DIP and SOIC adapter
COP8-PGMA-DS44P 28 and 20 DIP and SOIC plus 44
to program parts.
PP
EPU Order Information
with debugger and programmer control software with 40 ZIF programming socket.
PLCC adapter
FIGURE 14. EPU-COP8 Tool Environment
http://www.national.com 24
TL/DD/10802– 26
Development Support (Continued)
COP8 ASSEMBLER/LINKER SOFTWARE DEVELOPMENT TOOL KIT
National Semiconductor offers a relocateable COP8 macro cross assembler, linker, librarian and utility software devel­opment tool kit. Features are summarized as follows:
Basic and Feature Family instruction set by ‘‘device’’
#
type.
Nested macro capability.
#
Extensive set of assembler directives.
#
Supported on PC/DOS platform.
#
Generates National standard COFF output files.
#
Integrated Linker and Librarian.
#
Integrated utilities to generate ROM code file outputs.
#
DUMPCOFF utility.
#
This product is integrated as a part of MetaLink tools as a development kit, fully supported by the MetaLink debugger. It may be ordered separately or it is bundled with the Meta­Link products at no additional cost.
Order Information
Assembler SDK:
COP8-DEV-IBMA Assembler SDK on installable 3.5
PC/DOS Floppy Disk Drive format. Periodic upgrades and most recent version is available on National’s BBS and Internet.
Manufacturer
BP (800) 225-2102 Microsystems (713) 688-4600
Data I/O (800) 426-1045
HI–LO (510) 623-8860 Call Asia
ICE (800) 624-8949 Technology (919) 430-7915 Fax: 0-1226-370-434
MetaLink (800) 638-2423
Systems (408) 263-6667 General Fax:
Needhams (916) 924-8037
North
America
Fax: (713) 688-0920
(206) 881-6444 North America Fax: (206) 882-1043
(602) 926-0797 Fax:a49-80 9123 86 Fax: (602) 693-0681
Fax: (916) 924-8065
×
Approved List
COP8 C COMPILER
A C Compiler is developed and marketed by Byte Craft Lim­ited. The COP8C compiler is a fully integrated development tool specifically designed to support the compact embed­ded configuration of the COP8 family of products.
Features are summarized as follows:
ANSI C with some restrictions and extensions that opti-
#
mize development for the COP8 embedded application.
BITS data type extension. Register declarationÝpragma
#
with direct bit level definitions.
C language support for interrupt routines.
#
Expert system, rule based code geration and optimiza-
#
tion.
Performs consistency checks against the architectural
#
definitions of the target COP8 device.
Generates program memory code.
#
Supports linking of compiled object or COP8 assembled
#
object formats.
Global optimization of linked code.
#
Symbolic debug load format fully sourced level support-
#
ed by the MetaLink debugger.
INDUSTRY WIDE OTP/EPROM PROGRAMMING SUPPORT
Programming support, in addition to the MetaLink develop­ment tools, is provided by a full range of independent ap­proved vendors to meet the needs from the engineering laboratory to full production.
Europe Asia
a
49-8152-4183
a
49-8856-932616
a
44-0734-440011 Call
a
44-1226-767404
a
49-80 9156 96-0
a
41-1-9450300
a
852-234-16611
a
852-2710-8121
a
886-2-764-0215
a
Fax:
886-2-756-6403
a
852-737-1800
a
886-2-917-3005
a
886-2-911-1283
http://www.national.com25
Development Support (Continued)
AVAILABLE LITERATURE
For more information, please see the COP8 Basic Family User’s Manual, Literature Number 620895, COP8 Feature Family User’s Manual, Literature Number 620897 and Na­tional’s Family of 8-bit Microcontrollers COP8 Selection Guide, Literature Number 630009.
DIAL-A-HELPER SERVICE
Dial-A-Helper is a service provided by the Microcontroller Applications group. The Dial-A-Helper is an Electronic Infor­mation System that may be accessed as a Bulletin Board System (BBS) via data modem, as an FTP site on the Inter­net via standard FTP client application or as an FTP site on the Internet using a standard Internet browser such as Net­scape or Mosaic.
The Dial-A-Helper system provides access to an automated information storage and retrieval system . The system capa­bilities include a MESSAGE SECTION (electronic mail, when accessed as a BBS) for communications to and from the Microcontroller Applications Group and a FILE SEC­TION which consists of several file areas where valuable application software and utilities could be found.
DIAL-A-HELPER BBS via a Standard Modem
Modem: CANADA/U.S.: (800) NSC-MICRO
EUROPE: ( Baud: 14.4k Set-Up: Length: 8-Bit
Operation: 24 Hours, 7 Days
DIAL-A-HELPER via FTP
ftp nscmicro.nsc.com user: anonymous password: username
(800) 672-6427
a
49) 0-8141-351332
Parity: None Stop Bit: 1
@
yourhost.site.domain
DIAL-A-HELPER via WorldWide Web Browser
ftp://nscmicro.nsc.com
National Semiconductor on the WorldWide Web
See us on the WorldWide Web at: http://www.national.com
CUSTOMER RESPONSE CENTER
Complete product information and technical support is avail­able from National’s customer response centers.
CANADA/U.S.: Tel: (800)272-9959
email: support@tevm2.nsc.com
EUROPE: email: europe.support@nsc.com
Deutsch Tel:
English Tel:
a
49 (0) 180-530 85 85
a
49 (0) 180-532 78 32
Fran3ais Tel:a49 (0) 180-532 93 58
Italiano Tel:
JAPAN: Tel:
a
49 (0) 180-534 16 80
a
81-043-299-2309
S.E. ASIA: Beijing Tel: (a86) 10-6856-8601
Shanghai Tel: (a86) 21-6415-4092
Hong Kong Tel: (a852) 2737-1600
Korea Tel: (a82) 2-3771-6909
Malaysia Tel: (a60-4) 644-9061
Singapore Tel: (a65) 255-2226
Taiwan Tel:
a
886-2-521-3288
AUSTRALIA: Tel: (a61) 3-9558-9999
INDIA: Tel: (a91) 80-559-9467
http://www.national.com 26
Physical Dimensions inches, (millimeters)
Order Number COP882C-XXX/WM, COP982C-XXX/WM, COP682C-XXX/WM or COP982CH-XXX/WM
Order Number COP881C-XXX/WM, COP981C-XXX/WM, COP681C-XXX/WM or COP981CH-XXX/WM
Small Outline Molded Dual-In-Line Package (M)
NS Package Number M20B
Small Outline Molded Dual-In-Line Package (M)
NS Package Number M28B
http://www.national.com27
Physical Dimensions inches, (millimeters)
Order Number COP882C-XXX/N, COP682C-XXX/N, COP982C-XXX/N or COP982CH-XXX/N
Order Number COP881C-XXX/N, COP681C-XXX/N, COP981C-XXX/N or COP981CH-XXX/N
Molded Dual-In-Line Package (N)
NS Package Number N20B
Molded Dual-In-Line Package (N)
NS Package Number N28B
http://www.national.com 28
Physical Dimensions inches, (millimeters) (Continued)
Order Number COP880C-XXX/N, COP680C-XXX/N, COP980C-XXX/N or COP980CH-XXX/N
Molded Dual-In-Line Package (N)
NS Package Number N40A
http://www.national.com29
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Microcontrollers
Order Number COP880C-XXX/V, COP680C-XXX/V, COP980C-XXX/V or COP980CH-XXX/V
Plastic Leaded Chip Carrier (V)
NS Package Number V44A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: Arlington, TX 76017 Email: europe.support@nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408 Tel: 1(800) 272-9959 Deutsch Tel: Fax: 1(800) 737-7018 English Tel:
http://www.national.com
COP680C/COP681C/COP682C/COP880C/COP881C/COP882C/COP980C/COP981C/COP982C
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Fran3ais Tel: Italiano Tel:a49 (0) 180-534 16 80 Fax: (852) 2736-9960
a
49 (0) 180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2308
a
49 (0) 180-530 85 85 Tsimshatsui, Kowloon
a
49 (0) 180-532 78 32 Hong Kong
a
49 (0) 180-532 93 58 Tel: (852) 2737-1600
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