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COP404C
Technical data
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National Semiconductor COP404C Technical data

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COP404C ROMless CMOS Microcontrollers
COP404C ROMless CMOS Microcontrollers
April 1992
General Description
The COP404C ROMless Microcontroller is a member of the
TM
COPS
MICROBUSTMand MICROWIRETMare trademarks of National Semiconductor Corporation. TRI-STATE
is a registered trademark of National Semiconductor Corporation.
É
Block Diagram
Features
Y
Accurate emulation of the COP444C, COP424C and COP410C
Y
Lowest Power Dissipation (50 mW typical)
Y
Fully static (can turn off the clock)
Y
Power saving IDLE state and HALT mode
Y
4 ms instruction time, plus software selectable clocks
Y
128c4 RAM, addresses 2kc8 ROM
Y
True vectored interrupt, plus restart
Y
Three-level subroutine stack
Y
Single supply operation (2.4V to 5.5V)
Y
Programmable read/write 8-bit timer/event counter
Y
Internal binary counter register with MICROWIRE serial I/O capability
Y
General purpose and TRI-STATEÉoutputs
Y
LSTTL/CMOS compatible
Y
MICROBUSTMcompatible
Y
Software/hardware compatible with other members of the COP400 family
TM
TL/DD/5530– 1
FIGURE 1. Block Diagram
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/DD/5530
Absolute Maximum Ratings
Supply Voltage 6V
Voltage at any pin
Total Allowable Source Current 25 mA
Total Allowable Sink Current 25 mA
b
0.3V to V
CC
a
0.3V
Operating temperature range 0§toa70§C
Storage temperature range
b
65§Ctoa150§C
Lead temperature (soldering, 10 sec.) 300§C
DC Electrical Characteristics 0
s
CsT
70§C unless otherwise specified
§
a
Parameter Conditions Min Max Units
Operating Voltage 2.4 5.5 V Power Supply Ripple peak to peak 0.1 V (Notes 4, 5)
Supply Current V (Note 1) V
HALT Mode Current V (Note 2) V
e
CC
e
CC
e
V
CC
(T
is instruction cycle time)
c
e
CC
e
CC
2.4V, t
5.0V, t
5.0V, t
5.0V, F
2.4V, F
e
64 ms 120 mA
c
e
16 ms 700 mA
c
e
4 ms 3000 mA
c
e
IN
e
IN
0 kHz, T 0 kHz, T
e
25§C20mA
A
e
25§C6mA
A
CC
V
Input Voltage Levels RESET
, D0 (clock input)
CKI
Logic High 0.9 V Logic Low 0.1 V
CC
All other inputs (Note 7) Logic High 0.7 V Logic Low 0.2 V
CC
CC
CC
V V
V V
Input Pull-up current V
Hi-Z input leakage
CC
e
4.5V, V
e
0 30 330 mA
IN
b
1
a
1 mA
Input capacitance 7pF (Note 4)
Output Voltage Levels Standard outputs LSTTL Operation V
Logic High I Logic Low I
CMOS Operation
Logic High I Logic Low I
e
5.0Vg10%
CC
eb
100 mA 2.7 V
OH
e
400 mA 0.4 V
OL
eb
10 mAV
OH
e
10 mA 0.2 V
OL
b
0.2 V
CC
Output current levels
Sink (Note 6) V
Source (Standard option) V
Source (Low current option) V
e
4.5V, V
CC
e
V
2.4V, V
CC
e
4.5V, V
CC
e
V
2.4V, V
CC
e
4.5V, V
CC
e
V
2.4V, V
CC
e
V
OUT
CC
e
V
OUT
CC
e
0V 0.5 mA
OUT
e
0V 0.1 mA
OUT
e
0V 30 330 mA
OUT
e
0V 6 80 mA
OUT
1.2 mA
0.2 mA
Allowable Sink/Source current per pin 5 mA (Note 6)
Allowable Loading on CKOH 100 pF Current needed to over-ride HALT
(Note 3) To continue V To halt V
CC CC
e e
TRI-STATE leakage current
Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
4.5V, V
4.5V, V
e
2V
IN
CC
e
7V
IN
CC
b
2.5
.7 mA
1.6 mA
a
2.5 mA
2
COP404C
s
AC Electrical Characteristics
0§CsT
Parameter Conditions Min Max Units
Instruction Cycle V
) 4.5VlV
Time (t
c
Operating CKI V Frequency 4.5V
Duty Cycle (Note 4) f Rise Time (Note 4) f
Fall Time (Note 4) 40 ns Instruction Cycle Re30k, V
Time using D0 as a C RC Oscillator Dual­Clock Input (Note 4)
INPUTS: (See t
SETUP
t
HOLD
OUTPUT PROPAGATION DELAY V
IP7±IP0, A10 ±A8, SKIP
t
PD1,tPD0
AD/DATA
t
PD1,tPD0
ALL OTHER OUTPUTS
t
PD1
MICROBUS TIMING C Read Operation (
Chip select stable before RDbt Chip select hold time for RDbt RD pulse widthbt Data delay from RDbt
Fig. 3
)
,t
PD0
Fig. 4
)
CSR
RCS
RR
RD
CC
CC
e
1
e
1
e
G Inputs Tc/4a.7 ms SI Input IP Input 1.0 ms All Others V
CC
4.5V
OUT
V
CC
4.5VlV
V
CC
4.5V
V
CC
4.5V
e
L
RD to data floatingbtDF(Note 4) 250 ns Write Operation ( Chip select stable before WRbt Chip select hold time for WRbt WR pulse widthbt Data set-up time for WRbt Data hold time for WRbt INTR transition time from WRbt
Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI and all other pins pulled up to VCCwith 20k resistors. See current drain equation on page 16.
Note 2: Test conditions: All inputs tied to V
Note 3: When forcing HALT, current is only needed for a short time (approx. 200 ns) to flip the HALT flip-flop.
Note 4: This parameter is only sampled and not 100% tested. Variation due to the device included.
Note 5: Voltage change must be less than 0.1 V
Note 6: SO output sink current must be limited to keep V
Note 7: MB
Fig. 5
)
CSW
WCS
WW
DW
WD
WI
; L lines in TRI-STATE mode and tied to Ground; all outputs tied to Ground.
CC
ina1msperiod.
CC
less than 0.2 VCCto prevent entering test mode.
, TIN, DUAL, SEL10, SEL20, input levels at VCCor VSS.
OL
70§C unless otherwise specified
A
t
4.5V 4 DC ms
t
2.4V 16 DC ms
CC
t
4.5V DC 1.0 MHz
t
l
V
2.4V DC 250 kHz
CC
4 MHz 40 60 % 4 MHz external clock 60 ns
e
5V
CC
82 pF 8 16 m s
t
V
4.5V
CC
* 1.7 m s
t
4.5V 0.25 ms
t
l
V
2.4V 1.0 m s
CC
e
t
4.5V 1.94 ms
t
4.5V 375 ns
l
l
4.5V 1.0 ms
l
50 pF, V
e
1.5V, C
CC
V
CC
V
CC
100 pF, R
L
t
2.4V 7.75 ms
t
2.4V 1.5 ms
t
2.4V 4.0 ms
e
5Vg5%
CC
e
5K
L
0.3 ms
65 ns 20 ns
400 ns
375 ns
65 ns
20 ns 400 ns 320 ns 100 ns
700 ns
3
Connection Diagram
Dual-In-Line Package
Order Number COP404CN
See NS Package Number N48A
TL/DD/5530– 2
Pin Descriptions
Pin Description
V
CC
V
SS
CKI Clock input RS CKOI General purpose input L0±L7 8 TRI-STATE I/O G0±G3 4 general purpose I/O D1±D3 3 general purpose outputs D0 Either general purpose output
IN0±IN3 4 general purpose inputs SO Serial data output SI Serial data input SK Serial data clock output IP0±IP7 I/O for ROM address and data A8, A9, A10 3 address outputs SKIP Skip status output AD/DATA MB CKOH Halt I/O pin DUAL TIN
SEL10 SEL20 UNUSED Ground
FIGURE 2
Most positive voltage Ground
Reset input
or Dual-Clock RC input
Clock output MICROBUS select input
Dual-Clock select input Timer input select pin (should be connected to GND) COP410C emulation select input COP424C emulation select input
Figure 1
The internal architecture is shown in are illustrated in simplified form to depict how the various logic elements communicate with each other in implement­ing the instruction set of the device. Positive logic is used. When a bit is set, it is a logic ‘‘1’’, when a bit is reset, it is a logic ‘‘0’’.
PROGRAM MEMORY
Program Memory consists of a 2048-byte external memory (typically PROM). Words of this memory may be program instructions, constants or ROM addressing data.
ROM addressing is accomplished by a 11-bit PC register which selects one of the 8-bit words contained in ROM. A new address is loaded into the PC register during each in­struction cycle. Unless the instruction is a transfer of control instruction, the PC register is loaded with the next sequen­tial 11-bit binary count value.
Three levels of subroutine nesting are implemented by a three level deep stack. Each subroutine call or interrupt
. Data paths
pushes the next PC address into the stack. Each return pops the stack back into the PC register.
DATA MEMORY
Data memory consists of a 512-bit RAM, organized as 8 data registers of 16 mented by a 7-bit B register whose upper 3 bits (B of 8 data registers and lower 4 bits (B digits in the selected data register. While the 4-bit contents of the selected RAM digit (M) are usually loaded into or from, or exchanged with, the A register (accumulator), it may also be loaded into or from the Q latches or T counter or loaded from the L ports. RAM addressing may also be performed directly by the LDD and XAD instructions based upon the immediate operand field of these instructions. The B
register also serves as a source register for 4-bit data
d
sent directly to the D outputs.
4
c
4-bit digits. RAM addressing is imple-
) select 1 of 16 4-bit
d
) select 1
r
Timing Diagrams
FIGURE 3. Input/Output Timing
FIGURE 4. MICROBUS Read Operation Timing
TL/DD/5530– 3
TL/DD/5530– 4
FIGURE 5. MICROBUS Write Operation Timing
5
TL/DD/5530– 5
Functional Description
INTERNAL LOGIC
The processor contains its own 4-bit A register (accumula­tor) which is the source and destination register for most I/O, arithmetic, logic, and data memory access operations. It can also be used to load the B register, to load and input 4 bits of the 8-bit Q latch or T counter, L I/O ports data, to input 4-bit G, or IN ports, and to perform data exchanges with the SIO register.
A 4-bit adder performs the arithmetic and logic functions, storing the results in A. It also outputs a carry bit to the 1-bit C register, most often employed to indicate arithmetic over­flow. The C register in conjunction with the XAS instruction and the EN register, also serves to control the SK output.
The 8-bit T counter is a binary up counter which can be loaded to and from M and A using CAMT and CTMA instruc­tions. This counter is operated as a time-base counter. When the T counter overflows, an overflow flag will be set (see SKT and IT instructions below). The T counter is cleared on reset. A functional block diagram of the timer/ counter is illustrated in
Figure 10a
Four general-purpose inputs, IN3 –IN0, are provided. IN1, IN2 and IN3 may be selected (by pulling MB Read Strobe, Chip Select, and Write Strobe inputs, respec­tively, for use in MICROBUS application.
The D register provides 4 general-purpose outputs and is used as the destination register for the 4-bit contents of B In the dual clock mode, D0 latch controls the clock selection (see dual oscillator below).
The G register contents are outputs to a 4-bit general-pur­pose bidirectional I/O port. G0 may be selected as an out­put for MICROBUS applications.
The Q register is an internal, latched, 8-bit register, used to hold data loaded to or from M and A, as well as 8-bit data from ROM. Its contents are outputted to the L I/O ports when the L drivers are enabled under program control. With the MICROBUS option selected, Q can also be loaded with the 8-bit contents of the L I/O ports upon the occurrence of a write strobe from the host CPU.
The 8 L drivers, when enabled, output the contents of latched Q data to the L I/O port. Also, the contents of L may be read directly into A and M. As explained above, the MI­CROBUS option allows L I/O port data to be latched into the Q register.
The SIO register functions as a 4-bit serial-in/serial-out shift register for MICROWIRE as a binary counter (depending on the contents of the EN register). Its contents can be exchanged with A.
The XAS instruction copies C into the SKL latch. In the counter mode, SK is the output SKL; in the shift register mode, SK outputs SKL ANDed with the clock.
and Bdportions of the B
r
.
pin low) as
TM
I/O and COPS peripherals, or
EN is an internal 4-bit register loaded by the LEI instruction. The state of each bit of this register selects or deselects the particular feature associated with each bit of the EN regis­ter:
0. The least significant bit of the enable register, EN0, se­lects the SIO register as either a 4-bit shift register or a 4­bit binary counter. With EN0 set, SIO is an asynchronous binary counter, decrementing its value by one upon each low-going pulse (‘‘1’’ to ‘‘0’’) occurring on the SI input. Each pulse must be at least two instruction cycles wide. SK outputs the value of SKL. The SO output equals the value of EN3. With EN0 reset, SIO is a serial shift register left shifting 1 bit each instruction cycle time. The data present at SI goes into the least significant bit of SIO. SO can be enabled to output the most significant bit of SIO each cycle time. The SK outputs SKL ANDed with the instruction cycle clock.
1. With EN1 set, interrupt is enabled. Immediately following an interrupt, EN1 is reset to disable further interrupts.
2. With EN2 set, the L drivers are enabled to output the data in Q to the L I/O port. Resetting EN2 disables the L driv­ers, placing the L I/O port in a high-impedance input state.
3. EN3, in conjunction with EN0, affects the SO output. With EN0 set (binary counter option selected) SO will output
.
d
the value loaded into EN3. With EN0 reset (serial shift register option selected), setting EN3 enables SO as the output of the SIO shift register, outputting serial shifted data each instruction time. Resetting EN3 with the serial shift register option selected disables SO as the shift reg­ister output; data continues to be shifted through SIO and can be exchanged with A via an XAS instruction but SO remains set to ‘‘0’’.
INTERRUPT
The following features are associated with interrupt proce­dure and protocol and must be considered by the program­mer when utilizing interrupts.
a. The interrupt, once recognized as explained below,
pushes the next sequential program counter address
a
(PC
1) onto the stack. Any previous contents at the bot­tom of the stack are lost. The program counter is set to hex address 0FF (the last word of page 3) and EN1 is reset.
b. An interrupt will be recognized only on the following con-
ditions:
1. EN1 has been set.
2. A low-going pulse (‘‘1’’ to ‘‘0’’) at least two instruction
cycles wide has occurred on the IN1 input.
3. A currently executing instruction has been completed.
TABLE I. ENABLE REGISTER MODES Ð BITS EN0 AND EN3
EN0 EN3 SIO SI SO SK
0 0 Shift Register Input to Shift 0 If SKLe1, SKeclock
e
0 1 Shift Register Input to Shift Serial If SKL
Register If SKL
Register out If SKL 1 0 Binary Counter Input to Counter 0 SK 1 1 Binary Counter Input to Counter 1 SK
0, SKe0
e
1, SKeclock
e
0, SKe0
e
SKL
e
SKL
6
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