National Semiconductor ADC12L030, ADC12L032, ADC12L034, ADC12L038 Technical data

ADC12L030/ADC12L032/ADC12L034/ADC12L038

3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold

June 1999

ADC12L030/ADC12L032/ADC12L034/ADC12L038 3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O

A/D Converters with MUX and Sample/Hold

General Description

The ADC12L030 family is 12-bit plus sign successive approximation A/D converters with serial I/O and configurable input multiplexers. These devices are fully tested with a single 3.3Vpower supply. The ADC12L032, ADC12L034 and ADC12L038 have 2, 4 and 8 channel multiplexers, respectively. Differential multiplexer outputs and A/D inputs are available onthe MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 pins. The ADC12L030 has a two channel multiplexer with the multiplexer outputs and A/D inputs internally connected. On request, these A/Ds go through a self calibration process that adjusts linearity, zero and full-scale errors to less than

⁄2LSB each.

The analog inputs can be configured to operate in various combinations of single-ended, differential, or pseudo-differential modes.Afully differential unipolar analog input range (0V to +3.3V) can be accommodated with a single +3.3V supply. In the differential modes, valid outputs are obtained even when the negative inputs are greater than the positive because of the 12-bit plus sign two’scompliment output data format.

The serial I/O is configured to comply with NSC’s MICROWIRE references, see the LM4040 or LM4041 data sheets.

™

and Motorola’s SPI standards. For voltage

Features

n 0V to 3.3V analog input range with single 3.3V power

supply

n Serial I/O ( MICROWIRE and SPI Compatible) n 2, 4, or 8 channel differential or single-ended multiplexer n Analog input sample/hold function n Power down mode n Variable resolution and conversion rate n Programmable acquisition time n Variable digital output word length and format n No zero or full scale adjustment required n Fully tested and guaranteed with a 2.5V reference n No Missing Codes over temperature

Key Specifications

n Resolution 12-bit plus sign n 12-bit plus sign conversion time 8.8 µs (min) n 12-bit plus sign sampling rate 73 kHz (max) n Integral linearity error n Single supply 3.3V n Power dissipation 15 mW (max) n Power down 40 µW (typ)

1 LSB (max)

10%

Applications

n Portable Medical instruments n Portable computing n Portable Test equipment

ADC12L038 Simplified Block Diagram

DS011830-1

COPS™microcontrollers, HPC™and MICROWIRE™are trademarks of National Semiconductor Corporation.

™

Microsoft

is a trademark of Microsoft Corporation.

Ordering Information

Industrial Temperature Range NS Package

−40˚C ≤ T

≤ +85˚C Number

ADC12L030CIWM M16B ADC12L032CIWM M20B ADC12L034CIWM M24B ADC12L038CIWM M28B

Connection Diagrams

16-Pin Wide Body

SO Packages

ADC12L030/ADC12L032/ADC12L034/ADC12L038

DS011830-2

Top View

20-Pin Wide Body

SO Packages

24-Pin Wide Body

SO Packages

DS011830-4

Top View

248-Pin Wide Body

SO Packages

DS011830-3

Top View

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DS011830-5

Top View

Pin Descriptions

CCLK The clock applied to this input controls the

sucessive approximation conversion time interval and the acquisition time. The rise and fall times of the clock edges should not exceed 1 µs.

SCLK This is the serial data clock input. The clock

applied to this input controls the rate at which the serial data exchange occurs. The rising edge loads the information on the DI pin into the multiplexer address and mode select shift register. This address controls which channel of the analog input multiplexer (MUX) is selected and the mode of operation for the A/D. With CSlow the falling edge ofSCLK shifts the data resulting from the previous ADC conversion out on DO, with the exception of the first bit of data. When CS is low continuously, the first bit of the data is clocked out on the rising edge of EOC (end of conversion). When CS is toggled the falling edge of CS always clocks out the first bit of data. CS should be brought low when SCLK is low. The rise and fall times of the clock edges should not exceed 1 µs.

DI This is the serial data input pin. The data ap-

plied to this pin is shifted by the rising edge of SCLK into the multiplexer address and mode select register. signment of the multiplexer address and the mode select data.

DO The data output pin. This pin is an active push/

pull output when CS is Low. When CS is High this output is in TRI-STATE. The A/D conversion result (D0–D12) and converter status data are clocked out by the falling edge of SCLK on this pin. The word length and format of this result can vary (see and format are controlled by the data shifted into the multiplexer address and mode select register (see

EOC This pin is an active push/pull output and indi-

cates the status of the ADC12L030/2/4/8. When low, it signals that the A/D is busy with a conversion, auto-calibration, auto-zero or power down cycle. The rising edge of EOC signals the end of one of these cycles.

This is the chip select pin. When a logic low is applied to this pin, the rising edge of SCLK shifts the data on DI into the address register. This low also brings DO out of TRI-STATE. With CSlow the falling edge ofSCLK shifts the data resulting from the previous ADC conversion out on DO, with the exception of the first bit of data. When CS is low continuously, the first bit of the data is clocked out on the rising edge of EOC (end of conversion). When CS is toggled the falling edge of CS always clocks out the first bit of data. CS should be brought low when SCLK is low. The falling edge of CS resets a conversion in progress and starts the sequence for a new conversion. When CS is brought back low during a conversion, that conversion is prematurely ended. The data in the output latches may be corrupted. Therefore, when CS is brought back low during a

Tables 2, 3, 4, 5

Table 1

Table 5

show the as-

). The word length

conversion in progress the data output at that time should be ignored. CS may also be left continuously low. In this case it is imperative that the correct number of SCLK pulses be applied to the ADC in order to remain synchronous. After the ADC supply power is applied, it expects to see 13 clock pulses for each I/O sequence. The number of clock pulses the ADC expects is the same as the digital output word length. This word length can be modified by the data shifted in on the DO pin.

Table 5

details the data required.

DOR

This is the data output ready pin. This pin is an active push/pull output. It is low when the conversion result is being shifted out and goes high to signal that all the data has been shifted out.

CONV

A logic low is required on this pin to program any mode or change the ADC’s configuration as listed in the Mode Programming Table (

Table 5

) such as 12-bit conversion, 8-bit conversion,Auto Cal,Auto Zero etc.When this pin is high theADC is placed in the read data only mode. While in the read data only mode, bringing CS low and pulsing SCLK will only clock out on DO any data stored in the ADCs output shift register.The data on DI will be neglected. A new conversion will not be started and the ADC will remain in the mode and/or configuration previously programmed. Read data only cannot be performed while a conversion, Auto-Cal or Auto-Zero are in progress.

PD This is the power down pin. When PD is high

the A/D is powered down; when PD is low the A/D is powered up. The A/D takes a maximum of 700 µs to power up after the command is given.

CH0–CH7 These are the analog inputs of the MUX. A

channel input is selected by the address information at the DI pin, which is loaded on the rising edge of SCLK into the address register (see

Tables 2, 3, 4

The voltage applied to these inputs should not exceed V

+ or go below GND. Exceeding this

range on an unselected channel will corrupt the reading of a selected channel.

COM This pin is another analog input pin. It is used

as a pseudo ground when the analog multiplexer is single-ended.

MUXOUT1, MUXOUT2

A/DIN1, A/DIN2

These are the multiplexer output pins.

These are the converter input pins. MUXOUT1 is usually tied to A/DIN1. MUXOUT2 is usually tied to A/DIN2. If external circuitry is placed between MUXOUT1 and A/DIN1, or MUXOUT2 and A/DIN2 it may be necessary to protect these pins. The voltage at these pins should not exceed V

Figure 5

+ This is the positive analog voltage reference

REF

or go belowAGND (see

input. In order tomaintain accuracy the voltage range of V

REF(VREF

REF

+−V

REF

−) is

ADC12L030/ADC12L032/ADC12L034/ADC12L038

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Pin Descriptions (Continued)

to 3.3 VDCand the voltage at V

cannot exceed V

+. See

Figure 6

mended bypassing.

− The negative voltage reference input. In order

REF

to maintain accuracy the voltage at this pin must not go below GND or exceed V

Figure 6

+, VD+ These are the analog and digital power supply

pins. V

and V

are not connected together

on the chip. These pins should be tied to the same power supply and bypassed separately (see

Figure 6

+ and VD+ is 3.0 VDCto 5.5 VDC.

). The operating voltage range of

DGND This is the digital ground pin (see AGND This is the analog ground pin (see

ADC12L030/ADC12L032/ADC12L034/ADC12L038

REF

for recom-

+. (See

Figure 6

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ADC12L030/ADC12L032/ADC12L034/ADC12L038

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required, please contact the NationalSemiconductor Sales Office/ Distributors for availability and specifications.

Positive Supply Voltage

=VA+=VD+) 6.5V

Voltage at Inputs and Outputs

except CH0–CH7 and COM −0.3V to V

Voltage at Analog Inputs

CH0–CH7 and COM GND −5V to V

+−VD+| 300 mV

Input Current at Any Pin (Note 3) Package Input Current (Note 3) Package Dissipation at

= 25˚C (Note 4) 500 mW

+0.3V

30 mA

120 mA

+5V

Operating Ratings (Notes 1, 2)

Operating Temperature Range T

ADC12L030CIWM, ADC12L032CIWM, ADC12L034CIWM, ADC12L038CIWM −40˚C ≤ T

Supply Voltage

=VA+=VD+) +3.0V to +5.5V

+−VD+| ≤ 100 mV

+ 0VtoVA+

REF

− 0VtoV

REF

REF(VREF

REF

+−V

Common Mode Voltage Range

−) 1V to VA+

REF

ESD Susceptability (Note 5)

Human Body Model 1500V

Soldering Information

N Packages (10 seconds) 260˚C SO Package (Note 6):

A/DIN1, A/DIN2, MUXOUT1

and MUXOUT2 Voltage Range 0V to V

A/D IN Common Mode Voltage Range

Vapor Phase (60 seconds) 215˚C Infrared (15 seconds) 220˚C

Storage Temperature −65˚C to +150˚C

Converter Electrical Characteristics

The following specifications apply for V+=VA+=VD+ = +3.3 VDC,V sion mode, f

CK=fSK

1.250V common-mode voltage, and 10(t

MIN

to T

; all other limits TA=TJ= 25˚C. (Notes 7, 8, 9)

MAX

= 5 MHz, RS=25Ω, source impedance for V

) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=

Symbol Parameter Conditions Typical

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 12 + sign Bits (min)

+ILE Positive Integral Linearity Error After Auto-Cal (Notes 12, 18)

−ILE Negative Integral Linearity Error After Auto-Cal (Notes 12, 18) DNL Differential Non-Linearity After Auto-Cal

Positive Full-Scale Error After Auto-Cal (Notes 12, 18) Negative Full-Scale Error After Auto-Cal (Notes 12, 18) Offset Error After Auto-Cal (Notes 5, 18)

(+)=VIN(−) = 1.250V

DC Common Mode Error After Auto-Cal (Note 15)

TUE Total Unadjusted Error After Auto-Cal

(Notes 12, 13, 14)

Resolution with No Missing Codes 8-bit + sign mode 8 + sign Bits (min)

+INL Positive Integral Linearity Error 8-bit + sign mode (Note 12)

−INL Negative Integral Linearity Error 8-bit + sign mode (Note 12) DNL Differential Non-Linearity 8-bit + sign mode

Positive Full-Scale Error 8-bit + sign mode (Note 12) Negative Full-Scale Error 8-bit + sign mode (Note 12) Offset Error 8-bit + sign mode,

after Auto-Zero (Note 13) V

(+)=VIN(−) = + 1.250V

+ = +2.500 VDC,V

REF

+ and V

REF

− ≤ 25Ω, fully-differential input with fixed

REF

(Note 10)

1/2

1 LSB

≤ TA≤ T

MIN

≤ +85˚C

MAX

REF

−=0VDC, 12-bit + sign conver-

Limits Units

(Note 11)

1 LSB (max)

2 LSB (max)

3.5 LSB (max)

1/2 LSB (max)

3/4 LSB (max)

1/2 LSB (max)

(Limits)

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Converter Electrical Characteristics (Continued)

The following specifications apply for V+=VA+=VD+ = +3.3 VDC,V sion mode, f

CK=fSK

1.250V common-mode voltage, and 10(t

MIN

to T

; all other limits TA=TJ= 25˚C. (Notes 7, 8, 9)

MAX

= 5 MHz, RS=25Ω, source impedance for V

) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=

Symbol Parameter Conditions Typical

STATIC CONVERTER CHARACTERISTICS

TUE Total Unadjusted Error 8-bit + sign mode

after Auto-Zero

(Notes 12, 13, 14) Multiplexer Channel to Channel Matching Power Supply Sensitivity V

= +3.3V±10%

Offset Error

+ Full-Scale Error

− Full-Scale Error

ADC12L030/ADC12L032/ADC12L034/ADC12L038

+ Integral Linearity Error

− Integral Linearity Error Output Data from (Note 20) +10 LSB (max) “12-Bit Conversion of Offset” −10 LSB (min) (see

Table 5

) Output Data from (Note 20) 4095 LSB (max) “12-Bit Conversion of Full-Scale” 4093 LSB (min) (see

Table 5

)

UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS

S/(N+D) Signal-to-Noise Plus f

Distortion Ratio f

−3 dB Full Power Bandwidth V

= 1 kHz, VIN= 2.5 V

= 20 kHz, VIN= 2.5 V

= 40 kHz, VIN= 2.5 V

= 2.5 VPP, where S/(N+D)

drops 3 dB

DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS

S/(N+D) Signal-to-Noise Plus f

Distortion Ratio f

−3 dB Full Power Bandwidth V

= 1 kHz, VIN=±2.5V 77.0 dB

= 20 kHz, VIN=±2.5V 73.9 dB

= 40 kHz, VIN=±2.5V 67.0 dB

=±2.5V, where S/(N+D)

drops 3 dB

REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS

REF

A/D

Reference Input Capacitance 85 pF A/DIN1 and A/DIN2 Analog Input 75 pF Capacitance A/DIN1 and A/DIN2 Analog Input V Leakage Current V

= +3.3V or

=0V

CH0–CH7 and COM Input Voltage GND − 0.05 V (min)

CH0–CH7 and COM Input Capacitance

MUXOUT

MUX Output Capacitance 20 pF Off Channel Leakage (Note 16) On Channel = 3.3V and −0.01 −0.3 µA (min) CH0–CH7 and COM Pins Off Channel = 0V

On Channel = 0V and 0.01 0.3 µA (max) Off Channel = 3.3V

+ = +2.500 VDC,V

REF

+ and V

REF

PP PP

− ≤ 25Ω, fully-differential input with fixed

−=0VDC, 12-bit + sign conver-

REF

Limits Units

(Note 10)

0.05 LSB

0.5

0.5 LSB

(Note 11)

3/4 LSB (max)

1 LSB (max)

1.5 LSB (max)

69.4 dB

68.3 dB

65.7 dB 31 kHz

40 kHz

0.1

1.0 µA (max)

+ + 0.05 V (max)

10 pF

(Limits)

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Converter Electrical Characteristics (Continued)

The following specifications apply for V+=VA+=VD+ = +3.3 VDC,V sion mode, f

CK=fSK

1.250V common-mode voltage, and 10(t

MIN

to T

; all other limits TA=TJ= 25˚C. (Notes 7, 8, 9)

MAX

= 5 MHz, RS=25Ω, source impedance for V

) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=

Symbol Parameter Conditions Typical

REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS

On Channel Leakage (Note 16) On Channel = 3.3V and 0.01 0.3 µA (max) CH0–CH7 and COM Pins Off Channel = 0V

On Channel = 0V and −0.01 −0.3 µA (min) Off Channel = 3.3V

MUXOUT1 and MUXOUT2 V Leakage Current V

MUXOUT MUXOUT

MUX On Resistance VIN= 1.65V and 1300 1900 Ω (max)

MUXOUT

Matching Channel to Channel VIN= 1.65V and 5 %

MUXOUT

Channel to Channel Crosstalk V

= 3.3V or 0.01 0.3 µA (max) =0V

= 1.55V

= 3.3 VPP,fIN= 40 kHz −72 dB

MUX Bandwidth 90 kHz

+ = +2.500 VDC,V

REF

+ and V

REF

− ≤ 25Ω, fully-differential input with fixed

REF

(Note 10)

−=0VDC, 12-bit + sign conver-

Limits Units

(Note 11)

(Limits)

ADC12L030/ADC12L032/ADC12L034/ADC12L038

DC and Logic Electrical Characteristics

The following specifications apply for V+=VA+=VD+ = +3.3 VDC,V sion mode, f

CK=fSK

1.250V common-mode voltage, and 10(t

MIN

to T

; all other limits TA=TJ= 25˚C. (Notes 7, 8, 9)

MAX

= 5 MHz, RS=25Ω, source impedance for V

) acquisition time unless otherwise specified. Boldface limits apply for TA=TJ=

Symbol Parameter Conditions Typical Limits Units

CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS

V V I I

IN(1)

IN(0) IN(1) IN(0)

Logical “1” Input Voltage V+= 3.6V 2.0 V (min) Logical “0” Input Voltage V+= 3.0V 0.8 V (max) Logical “1” Input Current VIN= 3.3V 0.005 1.0 µA (max) Logical “0” Input Current VIN= 0V −0.005 −1.0 µA (min)

DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS

V I

−I

OUT

OUT(1)

OUT(0)

SC SC

Logical “1” Output Voltage V+= 3.0V, I

= 3.0V, I Logical “0” Output Voltage V+= 3.0V, I TRI-STATE Output Current V

Output Short Circuit Source Current V Output Short Circuit Sink Current V

= 0V −0.1 −3.0 µA (max)

OUT

= 3.3V 0.1 3.0 µA (max)

OUT

=0V 14 6.5 mA (min)

OUT

=VD+168.0 mA (min)

OUT

OUT OUT OUT

POWER SUPPLY CHARACTERISTICS

+ Digital Supply Current Awake 1.1 1.5 mA (max)

CS = HIGH, Powered Down, CCLK on CS = HIGH, Powered Down, CCLK off

+ Positive Analog Supply Current Awake 2.2 3.0 mA (max)

CS = HIGH, Powered Down, CCLK on CS = HIGH, Powered Down, CCLK off

REF

Reference Input Current Awake 70 µA

CS = HIGH, Powered Down

+ = +2.500 VDC,V

REF

+ and V

REF

− ≤ 25Ω, fully-differential input with fixed

−=0VDC, 12-bit + sign conver-

REF

(Note 10) (Note 11) (Limits)

= −360 µA 2.4 V (min) = − 10 µA 2.9 V (min) = 1.6 mA 0.4 V (max)

600 µA

12 µA

10 µA

0.1 µA

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AC Electrical Characteristics

The following specifications apply for V+=VA+=VD+ = +3.3 VDC,V sion mode, t with fixed 1.250V common-mode voltage, and 10(t

A=TJ=TMIN

= 3 ns, fCK=fSK= 5 MHz, RS=25Ω, source impedance for V

r=tf

to T

; all other limits TA=TJ= 25˚C. (Note 17)

MAX

) acquisition time unless otherwise specified. Boldface limits apply for

Symbol Parameter Conditions Typical Limits Units

Conversion Clock (CCLK) Frequency 10 5 MHz (max)

Serial Data Clock SCLK Frequency 10 5 MHz (max)

Conversion Clock Duty Cycle 40 % (min)

Serial Data Clock Duty Cycle 40 % (min)

ADC12L030/ADC12L032/ADC12L034/ADC12L038

Conversion Time 12-Bit + Sign or 12-Bit 44(tCK) 44(tCK) (max)

8-Bit + Sign or 8-Bit 21(t

Acquisition Time 6 Cycles Programmed 6(tCK) 6(tCK) (min) (Note 19) 7(t

10 Cycles Programmed 10(t

18 Cycles Programmed 18(t

34 Cycles Programmed 34(t

CAL

SYNC

Self-Calibration Time 4944(tCK) 4944(tCK) (max)

Auto-Zero Time 76(tCK) 76(tCK) (max)

Self-Calibration or Auto-Zero 2(tCK) 2(tCK) (min) Synchronization Time 3(t from DOR 0.40 µs (min)

DOR

DOR High Time when CS is Low Continuously

for Read Data and Software Power Up/Down

CONV

HPU

CONV Valid Data Time 8(tSK) 8(tSK) (max)

Hardware Power-Up Time, Time from 250 700 µs (max) PD Falling Edge to EOC Rising Edge

+ = +2.500 VDC,V

REF

−=0VDC, 12-bit + sign conver-

REF

+ and V

− ≤ 25Ω, fully-differential input

REF

(Note 10) (Note 11) (Limits)

1 MHz (min)

0 Hz (min)

60 % (max)

8.8 µs (max)

) 21(tCK) (max)

4.2 µs (max)

) (max)

1.2 µs (min)

1.4 µs (max)

) 10(tCK) (min)

11(t

) (max)

2.0 µs (min)

2.2 µs (max)

) 18(tCK) (min)

19(t

) (max)

3.6 µs (min)

3.8 µs (max)

) 34(tCK) (min)

35(t

) (max)

6.8 µs (min)

7.0 µs (max)

988.8 µs (max)

15.2 µs (max)

) (max)

0.60 µs (max)

9(t

) 9(tSK) (max)

1.8 µs (max)

1.6 µs (max)

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AC Electrical Characteristics (Continued)

The following specifications apply for V+=VA+=VD+ = +3.3 VDC,V sion mode, t with fixed 1.250V common-mode voltage, and 10(t

A=TJ=TMIN

= 3 ns, fCK=fSK= 5 MHz, RS=25Ω, source impedance for V

r=tf

to T

; all other limits TA=TJ= 25˚C. (Note 17)

MAX

) acquisition time unless otherwise specified. Boldface limits apply for

Symbol Parameter Conditions Typical Limits Units

SPU

Software Power-Up Time, Time from

EOC Rising Edge

ACC

Access Time Delay from 25 60 ns (max) CS Falling Edge to DO Data Valid

SET-UP

Set-Up Time of CS Falling Edge to 50 ns (min) Serial Data Clock Rising Edge

DELAY

Delay from SCLK Falling 0 5 ns (min) Edge to CS Falling Edge

t1H,t

HDI

Delay from CS Rising Edge to RL= 3k, CL= 100 pF 70 100 ns (max)

DO TRI-STATE

DI Hold Time from Serial Data 5 15 ns (min) Clock Rising Edge

SDI

DI Set-Up Time from Serial Data 5 10 ns (min) Clock Rising Edge

HDO

DO Hold Time from Serial Data RL= 3k, CL= 100 pF 35 65 ns (max) Clock Falling Edge 5 ns (min)

DDO

Delay from Serial Data Clock 50 90 ns (max) Falling Edge to DO Data Valid

RDO

DO Rise Time, TRI-STATE to High RL= 3k, CL= 100 pF 10 40 ns (max) DO Rise Time, Low to High 10 40 ns (max)

FDO

DO Fall Time, TRI-STATE to Low RL= 3k, CL= 100 pF 15 40 ns (max) DO Fall Time, High to Low 15 40 ns (max)

Delay from CS Falling Edge 50 80 ns (max) to DOR Falling Edge

Delay from Serial Data Clock Falling 45 80 ns (max) Edge to DOR Rising Edge

OUT

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified. Note 3: When the input voltage (V

The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 20 mA to four. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

allowable power dissipation at any temperature is P T

Capacitance of Logic Inputs 10 pF Capacitance of Logic Outputs 20 pF

) at any pin exceeds the power supplies (V

=(TJmax − TA)/θJAor the number given in the Absolute Maximum Ratings,whichever is lower. For this device,

max = 150˚C. The typical thermal resistance (θJA) of these parts when board mounted follow:

+ = +2.500 VDC,V

REF

GND or V

−=0VDC, 12-bit + sign conver-

REF

+ and V

− ≤ 25Ω, fully-differential input

REF

(Note 10) (Note 11) (Limits)

500 700 µs (max)Serial Data Clock Falling Edge to

VA+orVD+), the current at that pin should be limited to 20 mA.

max, θJAand the ambient temperature, TA. The maximum

ADC12L030/ADC12L032/ADC12L034/ADC12L038

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AC Electrical Characteristics (Continued)

Thermal

Part Number Resistance

ADC12L030CIWM 70˚C/W ADC12L032CIWM 64˚C/W ADC12L034CIWM 57˚C/W ADC12L038CIWM 50˚C/W

Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National

Semiconductor Linear Data Book for other methods of soldering surface mount devices. Note 7: Two on-chip diodes are tied to each analog input through a series resistor as shownbelow.Input voltage magnitudeup to 5V above V

will not damage this device. However, errors in theA/Dconversion can occur (if these diodes are forward biased by more than 50 mV) ifthe input voltage magnitude of selected or unselected analog input go above V

to ensure accurate conversions.

+ or below GND by more than 50 mV.As an example, if VA+ is 3.0 VDC, full-scale input voltage must be ≤3.05

ADC12L030/ADC12L032/ADC12L034/ADC12L038

+ or 5V below GND

DS011830-6

Note 8: To guarantee accuracy, it is required that the V pin.

Note 9: With the test condition for V Note 10: Typicals are at T Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive

full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions

between 1 to 0 and 0 to +1 (see

Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors. Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together. Note 16: Channel leakage current is measured after the channel selection. Note 17: Timingspecifications are tested at the TTLlogic levels, V

to 1.4V. Note 18: The ADC12L030 family’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will

result in a maximum repeatability uncertainty of 0.2 LSB.

Note 19: If SCLK and CCLK are driven from the same clock source, then t Note 20: The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output

data from these modes are not an indication of the accuracy of a conversion result.

REF(VREF

= 25˚C and represent most likely parametric norm.

J=TA

Figure 4

+ and VD+ be connected together to the same power supply with separate bypass capacitors at each V

+−V

−) given as +2.500V the 12-bit LSB is 610 µV and the 8-bit LSB is 9.8 mV.

REF

Figure 2

and

Figure 3

= 0.4V for a falling edge and VIH= 2.4V for a rising edge. TRI-STATEoutput voltage is forced

is 6, 10, 18 or 34 clock periods minimum and maximum.

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AC Electrical Characteristics (Continued)

FIGURE 1. Transfer Characteristic

ADC12L030/ADC12L032/ADC12L034/ADC12L038

DS011830-7

DS011830-8

FIGURE 2. Simplified Error Curve vs Output Code without Auto-Calibration or Auto-Zero Cycles

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