National Semiconductor ADC122S655 Technical data

February 25, 2008

ADC122S655 Dual 12-Bit, 200 kSPS to 500 kSPS, Simultaneous Sampling A/D Converter

General Description

The ADC122S655 is a dual 12-bit, 200 kSPS to 500 kSPS simultaneous sampling Analog-to-Digital (A/D) converter. The analog inputs on both channels are sampled simultaneously to preserve their relative phase information to each other. The converter is based on a successive-approximation register architecture where the differential nature of the analog inputs is maintained from the internal track-and-hold circuits throughout the A/D converter to provide excellent common-mode signal rejection. The ADC122S655 features an external reference that can be varied from 1.0V to VA.

The ADC122S655's serial data output is binary 2's complement and is compatible with several standards, such as SPI™, QSPI™, MICROWIRE™, and many common DSP serial interfaces. The serial clock (SCLK) and chip select bar

) are shared by both channels.

(CS

Operating from a single 5V analog supply and a reference voltage of 2.5V, the total power consumption while operating at 500 kSPS is typically 11 mW. With the ADC122S655 operating in power-down mode, the power consumption reduces to 3 µW. The differential input, low power consumption, and small size make the ADC122S655 ideal for direct connection to sensors in motor control applications.

Operation is guaranteed over the industrial temperature range of −40°C to +105°C and clock rates of 6.4 MHz to 16 MHz. The ADC122S655 is available in a 10-lead MSOP package.

Features

True Simultaneous Sampling Differential Inputs

■

Guaranteed performance from 200 kSPS to 500 kSPS

■

External Reference

■

Wide Input Common-Mode Voltage Range

■

Single High-Speed Serial Data Output

■

Operating Temperature Range of −40°C to +105°C

■

SPI™/QSPI™/MICROWIRE™/DSP compatible Serial

■

Interface

Key Specifications

Conversion Rate 200 kSPS to 500 kSPS

■

INL ±1 LSB (max)

■

DNL ±0.95 LSB (max)

■

SNR 71 dBc (min)

■

THD -72 dBc (min)

■

ENOB 11.25 bits (min)

■

Power Consumption at 500 kSPS

■

Converting, VA = 5V, V

—

Power-Down, VA = 5V, V

—

= 2.5V 11 mW (typ)

REF

= 2.5V 3 µW (typ)

REF

Applications

Motor Control

■

Power Meters/Monitors

■

Multi-Axis Positioning Systems

■

Instrumentation and Control Systems

■

Data Acquisition Systems

■

Medical Instruments

■

Direct Sensor Interface

■

Connection Diagram

30051905

TRI-STATE® is a trademark of National Semiconductor Corporation.

MICROWIRE™ is a trademark of National Semiconductor Corporation.

QSPI™ and SPI™ are trademarks of Motorola, Inc.

Ordering Information

Order Code Temperature Range Description Top Mark

ADC122S655CIMM −40°C to +105°C 10-Lead MSOP Package, 1000 Units Tape & Reel X96C

ADC122S655

ADC122S655CIMMX −40°C to +105°C 10-Lead MSOP Package, 3500 Units Tape & Reel X96C

ADC122S655EB Evaluation Board

Block Diagram

30051902

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Pin Descriptions and Equivalent Circuits

Pin No. Symbol Description

Voltage Reference Input. A voltage reference between 1V and VA must be applied to this

REF

input. V

µF. A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µF is recommended

for enhanced performance.

2 CHA+

3 CHA−

4 CHB−

5 CHB+

Non-Inverting Input for Channel A. CHA+ is the positive analog input for the differential

signal applied to Channel A.

Inverting Input for Channel A. CHA− is the negative analog input for the differential signal

applied to Channel A.

Inverting Input for Channel B. CHB− is the negative analog input for the differential signal

applied to Channel B.

Non-Inverting Input for Channel B. CHB+ is the positive analog input for the differential

signal applied to Channel B.

6 GND Ground. GND is the ground reference point for all signals applied to the ADC122S655.

Analog Power Supply input. A voltage source between 4.5V and 5.5V must be applied to

this input. VA must be decoupled to GND with a minimum ceramic capacitor value of 0.1

µF. A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µF is recommended

for enhanced performance.

Serial Data Output for Channel A and Channel B. The serial data output word is comprised

OUT

of 4 null bits, 12 data bits (ChA conversion result), 4 null bits, and 12 data bits (ChB

conversion result). During a conversion, the data is output on the falling edges of SCLK

and is valid on the rising edges.

9 SCLK Serial Clock. SCLK is used to control data transfer and serves as the conversion clock.

10 CS

Chip Select Bar. CS is active low. The ADC122S655 is actively converting when CS is

LOW and Power-Down Mode when CS is HIGH. A conversion begins on the fall of CS.

must be decoupled to GND with a minimum ceramic capacitor value of 0.1

REF

ADC122S655

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Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

ADC122S655

Analog Supply Voltage V

Voltage on Any Pin to GND −0.3V to (VA +0.3V)

Input Current at Any Pin (Note 3) ±10 mA

Package Input Current (Note 3) ±50 mA

Power Consumption at TA = 25°C

ESD Susceptibility (Note 5) Human Body Model Machine Model Charge Device Model

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

−0.3V to 6.5V

See (Note 4)

2500V

250V

1000V

Operating Ratings (Notes 1, 2)

Operating Temperature Range

Supply Voltage, V

Reference Voltage, V

REF

Input Common-Mode Voltage, VCMSee Figure 9 (Sect 2.3)

Digital Input Pins Voltage Range 0 to V

Clock Frequency 6.4 MHz to 16 MHz

Differential Analog Input Voltage −V

−40°C ≤ TA ≤ +105°C

+4.5V to +5.5V

REF

Package Thermal Resistance

Package

10-lead MSOP 240°C / W

Soldering process must comply with National

Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6)

ADC122S655 Converter Electrical Characteristics (Note 7)

The following specifications apply for VA = +4.5V to 5.5V, V otherwise noted. Boldface limits apply for TA = T

MIN

to T

Symbol Parameter Conditions Typical Limits Units

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 12 Bits

INL

DNL

Integral Non-Linearity ±0.5 ±1 LSB (max)

Integral Non-Linearity Matching 0.02 LSB

Differential Non-Linearity ±0.4 ±0.95 LSB (max)

Differential Non-Linearity Matching 0.02 LSB

Offset Error 0.2 ±3 LSB (max)

Offset Error Matching 0.1 LSB

Positive Gain Error −2 ±5 LSB (max)

Positive Gain Error Matching 0.2 LSB

Negative Gain Error 3 ±8 LSB (max)

Negative Gain Error Matching 0.2 LSB

DYNAMIC CONVERTER CHARACTERISTICS

SINAD Signal-to-Noise Plus Distortion Ratio

SNR Signal-to-Noise Ratio

THD Total Harmonic Distortion

SFDR Spurious-Free Dynamic Range

ENOB Effective Number of Bits

FPBW −3 dB Full Power Bandwidth

ISOL Channel-to-Channel Isolation

fIN = 100 kHz, −0.1 dBFS

Output at 70.7%FS with

FS Input

fIN < 1 MHz

ANALOG INPUT CHARACTERISTICS

DCL

INA

CMRR Common Mode Rejection Ratio

Differential Input Range

DC Leakage Current

Input Capacitance

VIN = V

In Track Mode 20 pF

In Hold Mode 3 pF

See the Specification Definitions for the

test condition

= 2.5V, f

REF

; all other limits are at TA = 25°C.

MAX

= 6.4 to 16 MHz, fIN = 100 kHz, CL = 25 pF, unless

SCLK

Differential

Input

Single-Ended

Input

−90 dBc

or VIN = -V

REF

72.5 69.5 dBc (min)

73.2 71 dBc (min)

−83 −72 dBc (max)

84 72 dBc (min)

11.8 11.25 bits (min)

26 MHz

22 MHz

−V

REF

±1 µA (max)

−90 dB

1.0V to V

to +V

V (min)

V (max)

REF

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Symbol Parameter Conditions Typical Limits Units

REF

Reference Voltage Range

1.0 V (min)

V (max)

DIGITAL INPUT CHARACTERISTICS

IND

Input High Voltage 2.4 V (min)

Input Low Voltage 0.8 V (max)

Input Current

VIN = 0V or V

±1 µA (max)

Input Capacitance 2 4 pF (max)

DIGITAL OUTPUT CHARACTERISTICS

OZH

OUT

Output High Voltage

Output Low Voltage

, I

TRI-STATE Leakage Current

OZL

TRI-STATE Output Capacitance

= 200 µA VA − 0.02

SOURCE

= 1 mA VA − 0.09

SOURCE

= 200 µA

SINK

= 1 mA

SINK

Force 0V or V

0.01 0.4 V (max)

0.08 V

±1 µA (max)

2 4 pF (max)

VA − 0.2

V (min)

Output Coding Binary 2'S Complement

POWER SUPPLY CHARACTERISTICS

IVA (Conv)

VREF

(Conv)

IVA (PD)

VREF

PWR

(Conv)

PWR

(PD)

Analog Supply Voltage

Analog Supply Current, Continuously

Converting

Reference Current, Continuously

Converting

Analog Supply Current, Power Down

Mode (CS high)

Reference Current, Power Down Mode

(PD)

(CS high)

Power Consumption, Continuously

Converting

Power Consumption, Power Down Mode

(CS high)

PSRR Power Supply Rejection Ratio

= 16 MHz, fS = 500 kSPS, fIN = 20

SCLK

kHz, VA = 5V

= 16 MHz, fS = 500 kSPS, V

SCLK

REF

2.5V

= 16 MHz, VA = 5.0V

SCLK

= 0, VA = 5.0V (Note 8)

SCLK

= 16 MHz, V

SCLK

= 0, V

SCLK

REF

= 16 MHz, fS = 500 kSPS, fIN = 20

kHz, VA = 5.0V, V

= 16 MHz, VA = 5.0V, V

SCLK

= 0, VA = 5.0V, V

SCLK

= 2.5V

REF

= 2.5V (Note 8)

= 2.5V

REF

= 2.5V

REF

= 2.5V

See the Specification Definitions for the

test condition

2.2 2.75 mA (max)

50 60 µA (max)

15 µA

0.5 1.1 µA (max)

0.05 µA

0.05 0.1 µA (max)

11.1 13.9 mW (max)

75 µW

2.6 5.8 µW (max)

−85 dB

4.5 V (min)

5.5 V (max)

AC ELECTRICAL CHARACTERISTICS

SCLK

ACQ

CONV

Maximum Clock Frequency 20 16 MHz (min)

Minimum Clock Frequency 1.6 6.4 MHz (max)

Maximum Sample Rate 625 500 kSPS (min)

Minimum Sample Rate 50 200 kSPS (min)

Track/Hold Acquisition Time 3 SCLK cycles

Conversion Time 12 SCLK cycles

Aperture Delay 6 ns

ADC122S655

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ADC122S655 Timing Specifications (Note 7)

The following specifications apply for VA = +4.5V to 5.5V, V noted. Boldface limits apply for TA = T

Symbol Parameter Conditions Typical Limits Units

ADC122S655

CSSU

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.

Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < GND or VIN > VA), the current at that pin should be limited to 10 mA. The 50

mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to five.

Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values for maximum power dissipation listed above will be reached only when the ADC122S655 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided.

Note 5: Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged through 0 Ω. Charge device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.

Note 6: Reflow temperature profiles are different for lead-free packages.

Note 7: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 8: Guaranteed by design, characterization, or statistical analysis and is not tested at final test.

Note 9: While the maximum sample rate is f

Note 10: t

CS Setup Time prior to an SCLK rising edge

DIS

Enable Time after the falling edge of CS

OUT

Hold time after an SCLK Falling edge

OUT

Access time after an SCLK Falling edge

OUT

Disable Time after the rising edge of CS

OUT

(Note 10)

SCLK High Time 25 ns (min)

SCLK Low Time 25 ns (min)

Rise Time

OUT

Fall Time

OUT

is the time for D

DIS

to change 10%.

OUT

to T

MIN

/32, the actual sample rate may be lower than this by having the CS rate slower than f

SCLK

: all other limits TA = 25°C.

MAX

= 2.5V, f

REF

= 6.4 MHz to 16 MHz, CL = 25 pF, unless otherwise

SCLK

4 7 ns (min)

1/ f

SCLK

1/ f

SCLK

- 3

9 20 ns (max)

9 6 ns (min)

20 26 ns (max)

10 20 ns (max)

7 ns

/32.

SCLK

ns (max)

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