February 2006
ADC121S051
Single Channel, 200 to 500 ksps, 12-Bit A/D Converter
ADC121S051 Single Channel, 200 to 500 ksps, 12-Bit A/D Converter
General Description
The ADC121S051 is a low-power, single channel CMOS
12-bit analog-to-digital converter with a high-speed serial
interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC121S051 is
fully specified over a sample rate range of 200 ksps to
500 ksps. The converter is based upon a successiveapproximation register architecture with an internal trackand-hold circuit.
The output serial data is straight binary, and is compatible
with several standards, such as SPI
MICROWIRE, and many common DSP serial interfaces.
The ADC121S051 operates with a single supply that can
range from +2.7V to +5.25V. Normal power consumption
using a +3.6V or +5.25V supply is 1.7 mW and 8.7 mW,
respectively. The power-down feature reduces the power
consumption to as low as 2.6 µW using a +5.25V supply.
The ADC121S051 is packaged in 6-lead LLP and SOT-23
packages. Operation over the industrial temperature range
of −40˚C to +85˚C is guaranteed.
™
, QSPI™,
Features
n Specified over a range of sample rates.
n 6-lead LLP and SOT-23 packages
n Variable power management
n Single power supply with 2.7V - 5.25V range
™
n SPI
/QSPI™/MICROWIRE/DSP compatible
Key Specifications
n DNL +0.5/-0.25 LSB (typ)
n INL +0.45/-0.40 LSB (typ)
n SNR 72.0 dB (typ)
n Power Consumption
— 3.6V Supply 1.7 mW (typ)
— 5.25V Supply 8.7 mW (typ)
Applications
n Portable Systems
n Remote Data Acquisition
n Instrumentation and Control Systems
Pin-Compatible Alternatives by Resolution and Speed
All devices are fully pin and function compatible.
Resolution Specified for Sample Rate Range of:
50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps
12-bit ADC121S021 ADC121S051 ADC121S101
10-bit ADC101S021 ADC101S051 ADC101S101
8-bit ADC081S021 ADC081S051 ADC081S101
Connection Diagram
20144605
Ordering Information
Order Code Temperature Range Description Top Mark
ADC121S051CISD −40˚C to +85˚C 6-Lead LLP Package X4C
ADC121S051CISDX −40˚C to +85˚C 6-Lead LLP Package, Tape and Reel X4C
ADC121S051CIMF −40˚C to +85˚C 6-Lead SOT-23 Package X13C
ADC121S051CIMFX −40˚C to +85˚C 6-Lead SOT-23 Package, Tape & Reel X13C
ADC121S051EVAL SOT-23 Evaluation Board
TRI-STATE®is a trademark of National Semiconductor Corporation
™
QSPI
and SPI™are trademarks of Motorola, Inc.
© 2006 National Semiconductor Corporation DS201446 www.national.com
Block Diagram
ADC121S051
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Description
ANALOG I/O
3V
DIGITAL I/O
4 SCLK Digital clock input. This clock directly controls the conversion and readout processes.
5 SDATA
6CS
POWER SUPPLY
1V
2 GND The ground return for the supply and signals.
PAD GND
IN
A
Analog input. This signal can range from 0V to VA.
Digital data output. The output samples are clocked out of this pin on falling edges of
the SCLK pin.
Chip select. On the falling edge of CS, a conversion process begins.
Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source
and bypassed to GND witha1µFcapacitor and a 0.1 µF monolithic capacitor located
within 1 cm of the power pin.
For package suffix CISD(X) only, it is recommended that the center pad should be
connected to ground.
20144607
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ADC121S051
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Analog Supply Voltage V
A
Voltage on Any Digital Pin to GND −0.3V to 6.5V
Voltage on Any Analog Pin to GND −0.3V to (V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Consumption at T
= 25˚C See (Note 4)
A
ESD Susceptibility (Note 5)
Human Body Model
Machine Model
Junction Temperature +150˚C
Storage Temperature −65˚C to +150˚C
−0.3V to 6.5V
+0.3V)
A
±
10 mA
±
20 mA
3500V
300V
Operating Ratings (Notes 1, 2)
Operating Temperature Range −40˚C ≤ T
V
Supply Voltage +2.7V to +5.25V
A
Digital Input Pins Voltage Range
(regardless of supply voltage)
Analog Input Pins Voltage Range 0V to V
Clock Frequency 1 MHz to 10 MHz
Sample Rate up to 500 ksps
Package Thermal Resistance
Package θ
6-lead LLP 94˚C / W
6-lead SOT-23 265˚C / W
Soldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications. Refer to
www.national.com/packaging. (Note 6)
ADC121S051 Converter Electrical Characteristics (Notes 7, 9)
The following specifications apply for VA= +2.7V to 5.25V, f
= 15 pF, unless otherwise noted. Boldface limits apply for TA=T
C
L
Symbol Parameter Conditions Typical
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 12 Bits
= +2.7V to +3.6V
V
A
INL Integral Non-Linearity
V
= +4.75 to +5.25V
A
= +2.7V to +3.6V
V
A
DNL Differential Non-Linearity
V
= +4.75 to +5.25V
A
= +2.7V to +3.6V −0.18
V
V
OFF
Offset Error
GE Gain Error
A
V
= +4.75 to +5.25V +1.9
A
V
= +2.7V to +3.6V −0.62
A
V
= +4.75 to +5.25V −1.50
A
DYNAMIC CONVERTER CHARACTERISTICS
V
= +2.7V to 5.25V
SINAD Signal-to-Noise Plus Distortion Ratio
SNR Signal-to-Noise Ratio
THD Total Harmonic Distortion
SFDR Spurious-Free Dynamic Range
ENOB Effective Number of Bits
Intermodulation Distortion, Second
IMD
Order Terms
Intermodulation Distortion, Third
Order Terms
A
= 100 kHz, −0.02 dBFS
f
IN
V
= +2.7V to 5.25V
A
= 100 kHz, −0.02 dBFS
f
IN
V
= +2.7V to 5.25V
A
= 100 kHz, −0.02 dBFS
f
IN
V
= +2.7V to 5.25V
A
= 100 kHz, −0.02 dBFS
f
IN
V
= +2.7V to 5.25V
A
= 100 kHz, −0.02 dBFS
f
IN
V
= +5.25V
A
= 103.5 kHz, fb= 113.5 kHz
f
a
V
= +5.25V
A
= 103.5 kHz, fb= 113.5 kHz
f
a
= 4 MHz to 10 MHz, f
SCLK
MIN
to T
SAMPLE
: all other limits TA= 25˚C.
MAX
+0.45
−0.40 LSB (min)
+0.75 LSB (max)
−0.45 LSB (min)
+0.50 +1.0 LSB (max)
−0.25 −0.9 LSB (min)
+0.80 LSB (max)
−0.50 LSB (min)
72 70 dB (min)
72 70.8 dB (min)
−83 dB
84 dB
11.7 11.3 Bits (min)
−83 dB
−82 dB
A
−0.3V to +5.25V
JA
= 200 ksps to 500 ksps,
Limits
(Note 9)
±
1.0
±
1.2
±
1.5
LSB (max)
LSB (max)
LSB (max)
≤ +85˚C
A
Units
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ADC121S051 Converter Electrical Characteristics (Notes 7, 9) (Continued)
The following specifications apply for VA= +2.7V to 5.25V, f
= 15 pF, unless otherwise noted. Boldface limits apply for TA=T
C
L
Symbol Parameter Conditions Typical
ADC121S051
DYNAMIC CONVERTER CHARACTERISTICS
V
= +5V 11 MHz
FPBW -3 dB Full Power Bandwidth
A
V
= +3V 8 MHz
A
ANALOG INPUT CHARACTERISTICS
V
I
C
IN
DCL
INA
Input Range 0 to V
DC Leakage Current
Input Capacitance
Track Mode 30 pF
Hold Mode 4 pF
DIGITAL INPUT CHARACTERISTICS
= +5.25V 2.4 V (min)
V
V
IH
V
IL
I
IN
C
IND
Input High Voltage
Input Low Voltage
Input Current VIN=0VorV
Digital Input Capacitance 2 4 pF (max)
A
V
= +3.6V 2.1 V (min)
A
= +5V 0.8 V (max)
V
A
V
= +3V 0.4 V (max)
A
DIGITAL OUTPUT CHARACTERISTICS
I
V
V
I
I
C
OZH
OZL
OH
OL
OUT
Output High Voltage
Output Low Voltage
,
TRI-STATE®Leakage Current
TRI-STATE®Output Capacitance 2 4 pF (max)
SOURCE
I
SOURCE
= 200 µA 0.03 0.4 V (max)
I
SINK
I
= 1 mA 0.1 V
SINK
Output Coding Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS
V
A
Supply Voltage
VA= +5.25V,
Supply Current, Normal Mode
(Operational, CS low)
I
A
Supply Current, Shutdown (CS high)
f
V
f
VA= +5.25V, f
f
V
f
Power Consumption, Normal Mode
(Operational, CS low)
P
D
Power Consumption, Shutdown (CS
high)
VA= +5.25V 8.7 15.8 mW (max)
V
V
f
V
f
= 200 ksps
SAMPLE
= +3.6V,
A
= 200 ksps
SAMPLE
= 0 ksps
SAMPLE
= +5.25V, f
A
= 0 ksps
SAMPLE
= +3.6V 1.7 4.7 mW (max)
A
= +5.25V, f
A
= 0 ksps
SAMPLE
= +5.25V, f
A
= 0 ksps
SAMPLE
AC ELECTRICAL CHARACTERISTICS
f
SCLK
f
S
t
CONV
Clock Frequency (Note 8)
Sample Rate (Note 8)
Conversion Time 16 SCLK cycles
= 4 MHz to 10 MHz, f
SCLK
MIN
A
to T
: all other limits TA= 25˚C.
MAX
= 200 ksps to 500 ksps,
SAMPLE
A
±
0.1
= 200 µA VA− 0.07 VA− 0.2 V (min)
=1mA VA− 0.1 V
±
0.1
1.66 3.0 mA (max)
0.46 1.3 mA (max)
= 0 MHz,
SCLK
SCLK
SCLK
SCLK
= 10 MHz,
= 0 MHz,
= 10 MHz,
500 nA
60 µA
2.6 µW
315 µW
Limits
(Note 9)
±
1 µA (max)
±
1 µA (max)
±
10 µA (max)
Units
2.7 V (min)
5.25 V (max)
4 MHz (min)
10 MHz (max)
200 ksps (min)
500 ksps (max)
V
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ADC121S051 Converter Electrical Characteristics (Notes 7, 9) (Continued)
The following specifications apply for VA= +2.7V to 5.25V, f
= 15 pF, unless otherwise noted. Boldface limits apply for TA=T
C
L
Symbol Parameter Conditions Typical
AC ELECTRICAL CHARACTERISTICS
DC SCLK Duty Cycle f
t
ACQ
Track/Hold Acquisition Time 400 ns (max)
= 10 MHz 50
SCLK
Throughput Time Acquisition Time + Conversion Time 20 SCLK cycles
t
QUIET
t
AD
t
AJ
(Note 10) 50 ns (min)
Aperture Delay 3 ns
Aperture Jitter 30 ps
= 4 MHz to 10 MHz, f
SCLK
MIN
to T
= 200 ksps to 500 ksps,
SAMPLE
: all other limits TA= 25˚C.
MAX
Limits
(Note 9)
40 % (min)
60 % (max)
Units
ADC121S051 Timing Specifications
The following specifications apply for VA= +2.7V to 5.25V, GND = 0V, f
f
= 200 ksps to 500 ksps, Boldface limits apply for TA=T
SAMPLE
MIN
Symbol Parameter Conditions Typical Limits Units
t
CS
t
SU
t
EN
t
ACC
t
CL
t
CH
t
H
t
DIS
t
POWER-UP
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supply (that is, V
mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute
Maximum Rating specification does not apply to the V
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms.
Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under
Operating Ratings.
Note 9: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 10: Minimum Quiet Time required by bus relinquish and the start of the next conversion.
Note 11: Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V.
Note 12: Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V or 2.0V.
Note 13: t
to remove the effects of charging or discharging the output capacitance. This means that t
Minimum CS Pulse Width 10 ns (min)
CS to SCLK Setup Time 10 ns (min)
Delay from CS Until SDATA TRI-STATE
®
Disabled (Note 11)
= +2.7V to +3.6V 40 ns (max)
Data Access Time after SCLK Falling Edge
(Note 12)
V
A
V
= +4.75V to +5.25V 20 ns (max)
A
SCLK Low Pulse Width 0.4xt
SCLK High Pulse Width 0.4xt
= +2.7V to +3.6V 7 ns (min)
V
SCLK to Data Valid Hold Time
SCLK Falling Edge to SDATA High
Impedance (Note 13)
A
V
= +4.75V to +5.25V 5 ns (min)
A
= +2.7V to +3.6V
V
A
V
= +4.75V to +5.25V
A
Power-Up Time from Full Power-Down 1 µs
<
GND or V
IN
pin. The current into the VApin is limited by the Analog Supply Voltage specification.
A
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
), and the ambient temperature (TA), and can be calculated using the formula PDmax=(TJmax − TA)/θJA. The values
JA
is derived from the time taken by the outputs to change by 0.5V with the timing test circuit shown in Figure 1. The measured number is then adjusted
DIS
J
= 4.0 MHz to 10.0 MHz, CL=25pF,
SCLK
to T
: all other limits TA= 25˚C.
MAX
20 ns (max)
SCLK
SCLK
25 ns (max)
6 ns (min)
25 ns (max)
5 ns (min)
>
VA), the current at that pin should be limited to 10 mA. The 20
IN
is the true bus relinquish time, independent of the bus loading.
DIS
ns (min)
ns (min)
ADC121S051
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Timing Diagrams
ADC121S051
20144608
FIGURE 1. Timing Test Circuit
FIGURE 2. ADC121S051 Serial Timing Diagram
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20144606
Specification Definitions
ACQUISITION TIME is the time required to acquire the input
voltage. That is, it is time required for the hold capacitor to
charge up to the input voltage.
APERTURE DELAY is the time between the fourth falling
SCLK edge of a conversion and the time when the input
signal is acquired or held for conversion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the
variation in aperture delay from sample to sample. Aperture
jitter manifests itself as noise in the output.
CONVERSION TIME is the time required, after the input
voltage is acquired, for the ADC to convert the input voltage
to a digital word.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital
waveform is high to the total time of one period. The specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion or SINAD. ENOB is defined as
(SINAD − 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
GAIN ERROR is the deviation of the last code transition
(111...110) to (111...111) from the ideal (V
after adjusting for offset error.
INTEGRAL NON-LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from
negative full scale (
through positive full scale (
1
⁄2LSB below the first code transition)
1
⁄2LSB above the last code
transition). The deviation of any given code from this straight
line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the second and third
order intermodulation products to the sum of the power in
both of the original frequencies. IMD is usually expressed in
dB.
− 1.5 LSB),
REF
MISSING CODES are those output codes that will never
appear at the ADC outputs. The ADC121S051 is guaranteed
not to have any missing codes.
OFFSET ERROR is the deviation of the first code transition
(000...000) to (000...001) from the ideal (i.e. GND + 0.5
LSB).
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)
Is the ratio, expressed in dB, of the rms value of the input
signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics
but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is any signal
present in the output spectrum that is not present at the input
and may or may not be a harmonic.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five
harmonic components at the output to the rms level of the
input signal frequency as seen at the output. THD is calculated as
where Af1is the RMS power of the input frequency at the
output and A
through Af6are the RMS power in the first 5
f2
harmonic frequencies.
THROUGHPUT TIME is the minimum time required between
the start of two successive conversion. It is the acquisition
time plus the conversion time.
ADC121S051
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Typical Performance Characteristics T
= 4 MHz to 10 MHz, fIN= 100 kHz unless otherwise stated.
f
SCLK
DNL
= 4 MHz
f
f
SCLK
SCLK
20144620 20144621
DNL
=10MHz
ADC121S051
= +25˚C, f
A
SAMPLE
= 200 ksps to 500 ksps,
INL
f
= 4 MHz
SCLK
INL
f
=10MHz
SCLK
20144660 20144661
DNL vs. Clock Frequency INL vs. Clock Frequency
20144665 20144666
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ADC121S051
Typical Performance Characteristics T
= 4 MHz to 10 MHz, fIN= 100 kHz unless otherwise stated. (Continued)
f
SCLK
= +25˚C, f
A
SNR vs. Clock Frequency SINAD vs. Clock Frequency
20144663 20144664
SFDR vs. Clock Frequency THD vs. Clock Frequency
= 200 ksps to 500 ksps,
SAMPLE
Spectral Response, VA= 5.25V
= 4 MHz
f
SCLK
20144667 20144668
Spectral Response, V
=10MHz
f
SCLK
20144669 20144670
= 5.25V
A
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Typical Performance Characteristics T
= 4 MHz to 10 MHz, fIN= 100 kHz unless otherwise stated. (Continued)
f
SCLK
= +25˚C, f
A
= 200 ksps to 500 ksps,
SAMPLE
ADC121S051
Power Consumption vs. Throughput,
f
=10MHz
SCLK
20144655
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Applications Information
1.0 ADC121S051 OPERATION
The ADC121S051 is a successive-approximation analog-todigital converters designed around a charge-redistribution
digital-to-analog converter core. Simplified schematics of the
ADC121S051 in both track and hold modes are shown in
Figure 3 and Figure 4, respectively. In Figure 3, the device is
in track mode: switch SW1 connects the sampling capacitor
to the input, and SW2 balances the comparator inputs. The
device is in this state until CS is brought low, at which point
the device moves to the hold mode.
ADC121S051
Figure 4 shows the device in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining the
sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-redistribution
DAC to add or subtract fixed amounts of charge from the
sampling capacitor until the comparator is balanced. When
the comparator is balanced, the digital word supplied to the
DAC is the digital representation of the analog input voltage.
The device moves from hold mode to track mode on the 13th
rising edge of SCLK.
20144609
FIGURE 3. ADC121S051 in Track Mode
FIGURE 4. ADC121S051 in Hold Mode
2.0 USING THE ADC121S051
The serial interface timing diagram for the ADC121S051 is
shown in Figure 2. CS is chip select, which initiates conversions on the ADC121S051 and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. SDATA is the serial data
out pin, where a conversion result is found as a serial data
stream.
Basic operation of the ADC121S051 begins with CS going
low, which initiates a conversion process and data transfer.
Subsequent rising and falling edges of SCLK will be labelled
with reference to the falling edge of CS; for example, "the
third falling edge of SCLK" shall refer to the third falling edge
of SCLK after CS goes low.
At the fall of CS, the SDATA pin comes out of TRI-STATE,
and the converter moves from track mode to hold mode. The
input signal is sampled and held for conversion on the falling
20144610
edge of CS. The converter moves from hold mode to track
mode on the 13th rising edge of SCLK (see Figure 2). The
SDATA pin will be placed back into TRI-STATE after the 16th
falling edge of SCLK, or at the rising edge of CS, whichever
occurs first. After a conversion is completed, the quiet time
) must be satisfied before bringing CS low again to
(t
QUIET
begin another conversion.
Sixteen SCLK cycles are required to read a complete
sample from the ADC121S051. The sample bits (including
leading zeroes) are clocked out on falling edges of SCLK,
and are intended to be clocked in by a receiver on subsequent falling edges of SCLK. The ADC121S051 will produce
three leading zero bits on SDATA, followed by twelve data
bits, most significant first.
If CS goes low before the rising edge of SCLK, an additional
(fourth) zero bit may be captured by the next falling edge of
SCLK.
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Applications Information (Continued)
3.0 ADC121S051 TRANSFER FUNCTION
The output format of the ADC121S051 is straight binary.
Code transitions occur midway between successive integer
ADC121S051
LSB values. The LSB width for the ADC121S051 is V
The ideal transfer characteristic is shown in Figure 5. The
transition from an output code of 0000 0000 0000 to a code
of 0000 0000 0001 is at 1/2 LSB, or a voltage of V
Other code transitions occur at steps of one LSB.
/4096.
A
/8192.
A
5.0 ANALOG INPUTS
An equivalent circuit for the ADC121S051’s input is shown in
Figure 7. Diodes D1 and D2 provide ESD protection for the
analog inputs. At no time should the analog input go beyond
+ 300 mV) or (GND − 300 mV), as these ESD diodes will
(V
A
begin conducting, which could result in erratic operation.
The capacitor C1 in Figure 7 has a typical value of 4 pF, and
is mainly the package pin capacitance. Resistor R1 is the on
resistance of the track / hold switch, and is typically 500
ohms. Capacitor C2 is the ADC121S051 sampling capacitor
and is typically 26 pF. The ADC121S051 will deliver best
performance when driven by a low-impedance source to
eliminate distortion caused by the charging of the sampling
capacitance. This is especially important when using the
ADC121S051 to sample AC signals. Also important when
sampling dynamic signals is an anti-aliasing filter.
20144611
FIGURE 5. Ideal Transfer Characteristic
4.0 TYPICAL APPLICATION CIRCUIT
A typical application of the ADC121S051 is shown in
Figure 6. Power is provided in this example by the National
Semiconductor LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages. The
power supply pin is bypassed with a capacitor network located close to the ADC121S051. Because the reference for
the ADC121S051 is the supply voltage, any noise on the
supply will degrade device noise performance. To keep noise
off the supply, use a dedicated linear regulator for this device, or provide sufficient decoupling from other circuitry to
keep noise off the ADC121S051 supply pin. Because of the
ADC121S051’s low power requirements, it is also possible to
use a precision reference as a power supply to maximize
performance. The three-wire interface is shown connected to
a microprocessor or DSP.
20144613
FIGURE 6. Typical Application Circuit
20144614
FIGURE 7. Equivalent Input Circuit
6.0 DIGITAL INPUTS AND OUTPUTS
The ADC121S051 digital inputs (SCLK and CS) are not
limited by the same maximum ratings as the analog inputs.
The digital input pins are instead limited to +5.25V with
respect to GND, regardless of V
, the supply voltage. This
A
allows the ADC121S051 to be interfaced with a wide range
of logic levels, independent of the supply voltage.
7.0 MODES OF OPERATION
The ADC121S051 has two possible modes of operation:
normal mode, and shutdown mode. The ADC121S051 enters normal mode (and a conversion process is begun) when
CS is pulled low. The device will enter shutdown mode if CS
is pulled high before the tenth falling edge of SCLK after CS
is pulled low, or will stay in normal mode if CS remains low.
Once in shutdown mode, the device will stay there until CS is
brought low again. By varying the ratio of time spent in the
normal and shutdown modes, a system may trade-off
throughput for power consumption, with a sample rate as low
as zero.
7.1 Normal Mode
The fastest possible throughput is obtained by leaving the
ADC121S051 in normal mode at all times, so there are no
power-up delays. To keep the device in normal mode continuously, CS must be kept low until after the 10th falling
edge of SCLK after the start of a conversion (remember that
a conversion is initiated by bringing CS low).
If CS is brought high after the 10th falling edge, but before
the 16th falling edge, the device will remain in normal mode,
but the current conversion will be aborted, and SDATA will
return to TRI-STATE (truncating the output word).
Sixteen SCLK cycles are required to read all of a conversion
word from the device. After sixteen SCLK cycles have
www.national.com 12
Applications Information (Continued)
elapsed, CS may be idled either high or low until the next
conversion. If CS is idled low, it must be brought high again
before the start of the next conversion, which begins when
CS is again brought low.
After sixteen SCLK cycles, SDATA returns to TRI-STATE.
Another conversion may be started, after t
elapsed, by bringing CS low again.
7.2 Shutdown Mode
Shutdown mode is appropriate for applications that either do
not sample continuously, or it is acceptable to trade throughput for power consumption. When the ADC121S051 is in
shutdown mode, all of the analog circuitry is turned off.
QUIET
has
ADC121S051
To enter shutdown mode, a conversion must be interrupted
by bringing CS high anytime between the second and tenth
falling edges of SCLK, as shown in Figure 8. Once CS has
been brought high in this manner, the device will enter
shutdown mode; the current conversion will be aborted and
SDATA will enter TRI-STATE. If CS is brought high before the
second falling edge of SCLK, the device will not change
mode; this is to avoid accidentally changing mode as a result
of noise on the CS line.
FIGURE 8. Entering Shutdown Mode
FIGURE 9. Entering Normal Mode
To exit shutdown mode, bring CS back low. Upon bringing
CS low, the ADC121S051 will begin powering up (power-up
time is specified in the Timing Specifications table). This
power-up delay results in the first conversion result being
unusable. The second conversion performed after power-up,
however, is valid, as shown in Figure 9.
If CS is brought back high before the 10th falling edge of
SCLK, the device will return to shutdown mode. This is done
to avoid accidentally entering normal mode as a result of
noise on the CS line. To exit shutdown mode and remain in
normal mode, CS must be kept low until after the 10th falling
edge of SCLK. The ADC121S051 will be fully powered-up
after 16 SCLK cycles.
8.0 POWER MANAGEMENT
The ADC121S051 takes time to power-up, either after first
applying V
, or after returning to normal mode from shut-
A
down mode. This corresponds to one "dummy" conversion
for any SCLK frequency within the specifications in this
document. After this first dummy conversion, the
ADC121S051 will perform conversions properly. Note that
the t
time must still be included between the first
QUIET
dummy conversion and the second valid conversion.
20144616
20144617
When the V
supply is first applied, the ADC121S051 may
A
power up in either of the two modes: normal or shutdown. As
such, one dummy conversion should be performed after
start-up, as described in the previous paragraph. The part
may then be placed into either normal mode or the shutdown
mode, as described in Sections 7.1 and 7.2.
When the ADC121S051 is operated continuously in normal
mode, the maximum throughput is f
may be traded for power consumption by running f
/ 20. Throughput
SCLK
SCLK
at its
maximum specified rate and performing fewer conversions
per unit time, raising the ADC121S051 CS line after the 10th
and before the 15th fall of SCLK of each conversion. A plot of
typical power consumption versus throughput is shown in
the Typical Performance Curves section. To calculate the
power consumption for a given throughput, multiply the fraction of time spent in the normal mode by the normal mode
power consumption and add the fraction of time spent in
shutdown mode multiplied by the shutdown mode power
consumption. Note that the curve of power consumption vs.
throughput is essentially linear. This is because the power
consumption in the shutdown mode is so small that it can be
ignored for all practical purposes.
www.national.com13
Applications Information (Continued)
9.0 POWER SUPPLY NOISE CONSIDERATIONS
The charging of any output load capacitance requires current from the power supply, V
ADC121S051
from the supply to charge the output capacitance will cause
voltage variations on the supply. If these variations are large
enough, they could degrade SNR and SINAD performance
of the ADC. Furthermore, discharging the output capacitance when the digital output goes from a logic high to a logic
low will dump current into the die substrate, which is resistive. Load discharge currents will cause "ground bounce"
. The current pulses required
A
noise in the substrate that will degrade noise performance if
that current is large enough. The larger the output capacitance, the more current flows through the die substrate and
the greater is the noise coupled into the analog channel,
degrading noise performance.
To keep noise out of the power supply, keep the output load
capacitance as small as practical. It is good practice to use a
100 Ω series resistor at the ADC output, located as close to
the ADC output pin as practical. This will limit the charge and
discharge current of the output capacitance and improve
noise performance.
www.national.com 14
Physical Dimensions inches (millimeters) unless otherwise noted
ADC121S051
6-Lead LLP
Order Number ADC121S051CISD or ADC121S051CISDX
NS Package Number SDB06A
6-Lead SOT-23
Order Number ADC121S051CIMF, ADC121S051CIMFX
NS Package Number MF06A
www.national.com15
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
ADC121S051 Single Channel, 200 to 500 ksps, 12-Bit A/D Converter
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