National Semiconductor ADC121S051 Technical data

February 2006

ADC121S051
Single Channel, 200 to 500 ksps, 12-Bit A/D Converter

ADC121S051 Single Channel, 200 to 500 ksps, 12-Bit A/D Converter

General Description

The ADC121S051 is a low-power, single channel CMOS
12-bit analog-to-digital converter with a high-speed serial
interface. Unlike the conventional practice of specifying per­formance at a single sample rate only, the ADC121S051 is
fully specified over a sample rate range of 200 ksps to
500 ksps. The converter is based upon a successive­approximation register architecture with an internal track­and-hold circuit.

The output serial data is straight binary, and is compatible
with several standards, such as SPI
MICROWIRE, and many common DSP serial interfaces.

The ADC121S051 operates with a single supply that can
range from +2.7V to +5.25V. Normal power consumption
using a +3.6V or +5.25V supply is 1.7 mW and 8.7 mW,
respectively. The power-down feature reduces the power
consumption to as low as 2.6 µW using a +5.25V supply.

The ADC121S051 is packaged in 6-lead LLP and SOT-23
packages. Operation over the industrial temperature range
of −40˚C to +85˚C is guaranteed.

™

, QSPI™,

Features

n Specified over a range of sample rates.
n 6-lead LLP and SOT-23 packages
n Variable power management
n Single power supply with 2.7V - 5.25V range

™

n SPI

/QSPI™/MICROWIRE/DSP compatible

Key Specifications

n DNL +0.5/-0.25 LSB (typ)
n INL +0.45/-0.40 LSB (typ)
n SNR 72.0 dB (typ)
n Power Consumption

— 3.6V Supply 1.7 mW (typ)
— 5.25V Supply 8.7 mW (typ)

Applications

n Portable Systems
n Remote Data Acquisition
n Instrumentation and Control Systems

Pin-Compatible Alternatives by Resolution and Speed

All devices are fully pin and function compatible.

Resolution Specified for Sample Rate Range of:

50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps

12-bit ADC121S021 ADC121S051 ADC121S101

10-bit ADC101S021 ADC101S051 ADC101S101

8-bit ADC081S021 ADC081S051 ADC081S101

Connection Diagram

20144605

Ordering Information

Order Code Temperature Range Description Top Mark

ADC121S051CISD −40˚C to +85˚C 6-Lead LLP Package X4C

ADC121S051CISDX −40˚C to +85˚C 6-Lead LLP Package, Tape and Reel X4C

ADC121S051CIMF −40˚C to +85˚C 6-Lead SOT-23 Package X13C

ADC121S051CIMFX −40˚C to +85˚C 6-Lead SOT-23 Package, Tape & Reel X13C

ADC121S051EVAL SOT-23 Evaluation Board

TRI-STATE®is a trademark of National Semiconductor Corporation

™

QSPI

and SPI™are trademarks of Motorola, Inc.

© 2006 National Semiconductor Corporation DS201446 www.national.com

Block Diagram

ADC121S051

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Description

ANALOG I/O

3V

DIGITAL I/O

4 SCLK Digital clock input. This clock directly controls the conversion and readout processes.

5 SDATA

6CS

POWER SUPPLY

1V

2 GND The ground return for the supply and signals.

PAD GND

IN

A

Analog input. This signal can range from 0V to VA.

Digital data output. The output samples are clocked out of this pin on falling edges of
the SCLK pin.

Chip select. On the falling edge of CS, a conversion process begins.

Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source
and bypassed to GND witha1µFcapacitor and a 0.1 µF monolithic capacitor located
within 1 cm of the power pin.

For package suffix CISD(X) only, it is recommended that the center pad should be
connected to ground.

20144607

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ADC121S051

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Analog Supply Voltage V

A

Voltage on Any Digital Pin to GND −0.3V to 6.5V

Voltage on Any Analog Pin to GND −0.3V to (V

Input Current at Any Pin (Note 3)

Package Input Current (Note 3)

Power Consumption at T

= 25˚C See (Note 4)

A

ESD Susceptibility (Note 5)

Human Body Model
Machine Model

Junction Temperature +150˚C

Storage Temperature −65˚C to +150˚C

−0.3V to 6.5V

+0.3V)

A

±

10 mA

±

20 mA

3500V

300V

Operating Ratings (Notes 1, 2)

Operating Temperature Range −40˚C ≤ T

V

Supply Voltage +2.7V to +5.25V

A

Digital Input Pins Voltage Range

(regardless of supply voltage)

Analog Input Pins Voltage Range 0V to V

Clock Frequency 1 MHz to 10 MHz

Sample Rate up to 500 ksps

Package Thermal Resistance

Package θ

6-lead LLP 94˚C / W

6-lead SOT-23 265˚C / W

Soldering process must comply with National Semiconduc­tor’s Reflow Temperature Profile specifications. Refer to
www.national.com/packaging. (Note 6)

ADC121S051 Converter Electrical Characteristics (Notes 7, 9)

The following specifications apply for VA= +2.7V to 5.25V, f

= 15 pF, unless otherwise noted. Boldface limits apply for TA=T

C

L

Symbol Parameter Conditions Typical

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 12 Bits

= +2.7V to +3.6V

V

A

INL Integral Non-Linearity

V

= +4.75 to +5.25V

A

= +2.7V to +3.6V

V

A

DNL Differential Non-Linearity

V

= +4.75 to +5.25V

A

= +2.7V to +3.6V −0.18

V

V

OFF

Offset Error

GE Gain Error

A

V

= +4.75 to +5.25V +1.9

A

V

= +2.7V to +3.6V −0.62

A

V

= +4.75 to +5.25V −1.50

A

DYNAMIC CONVERTER CHARACTERISTICS

V

= +2.7V to 5.25V

SINAD Signal-to-Noise Plus Distortion Ratio

SNR Signal-to-Noise Ratio

THD Total Harmonic Distortion

SFDR Spurious-Free Dynamic Range

ENOB Effective Number of Bits

Intermodulation Distortion, Second

IMD

Order Terms

Intermodulation Distortion, Third
Order Terms

A

= 100 kHz, −0.02 dBFS

f

IN

V

= +2.7V to 5.25V

A

= 100 kHz, −0.02 dBFS

f

IN

V

= +2.7V to 5.25V

A

= 100 kHz, −0.02 dBFS

f

IN

V

= +2.7V to 5.25V

A

= 100 kHz, −0.02 dBFS

f

IN

V

= +2.7V to 5.25V

A

= 100 kHz, −0.02 dBFS

f

IN

V

= +5.25V

A

= 103.5 kHz, fb= 113.5 kHz

f

a

V

= +5.25V

A

= 103.5 kHz, fb= 113.5 kHz

f

a

= 4 MHz to 10 MHz, f

SCLK

MIN

to T

SAMPLE

: all other limits TA= 25˚C.

MAX

+0.45

−0.40 LSB (min)

+0.75 LSB (max)

−0.45 LSB (min)

+0.50 +1.0 LSB (max)

−0.25 −0.9 LSB (min)

+0.80 LSB (max)

−0.50 LSB (min)

72 70 dB (min)

72 70.8 dB (min)

−83 dB

84 dB

11.7 11.3 Bits (min)

−83 dB

−82 dB

A

−0.3V to +5.25V

JA

= 200 ksps to 500 ksps,

Limits

(Note 9)

±

1.0

±

1.2

±

1.5

LSB (max)

LSB (max)

LSB (max)

≤ +85˚C

A

Units

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ADC121S051 Converter Electrical Characteristics (Notes 7, 9) (Continued)

The following specifications apply for VA= +2.7V to 5.25V, f

= 15 pF, unless otherwise noted. Boldface limits apply for TA=T

C

L

Symbol Parameter Conditions Typical

ADC121S051

DYNAMIC CONVERTER CHARACTERISTICS

V

= +5V 11 MHz

FPBW -3 dB Full Power Bandwidth

A

V

= +3V 8 MHz

A

ANALOG INPUT CHARACTERISTICS

V

I

C

IN

DCL

INA

Input Range 0 to V

DC Leakage Current

Input Capacitance

Track Mode 30 pF

Hold Mode 4 pF

DIGITAL INPUT CHARACTERISTICS

= +5.25V 2.4 V (min)

V

V

IH

V

IL

I

IN

C

IND

Input High Voltage

Input Low Voltage

Input Current VIN=0VorV

Digital Input Capacitance 2 4 pF (max)

A

V

= +3.6V 2.1 V (min)

A

= +5V 0.8 V (max)

V

A

V

= +3V 0.4 V (max)

A

DIGITAL OUTPUT CHARACTERISTICS

I

V

V

I
I

C

OZH

OZL

OH

OL

OUT

Output High Voltage

Output Low Voltage

,

TRI-STATE®Leakage Current

TRI-STATE®Output Capacitance 2 4 pF (max)

SOURCE

I

SOURCE

= 200 µA 0.03 0.4 V (max)

I

SINK

I

= 1 mA 0.1 V

SINK

Output Coding Straight (Natural) Binary

POWER SUPPLY CHARACTERISTICS

V

A

Supply Voltage

VA= +5.25V,
Supply Current, Normal Mode
(Operational, CS low)

I

A

Supply Current, Shutdown (CS high)

f

V

f

VA= +5.25V, f

f

V

f

Power Consumption, Normal Mode
(Operational, CS low)

P

D

Power Consumption, Shutdown (CS
high)

VA= +5.25V 8.7 15.8 mW (max)

V

V

f

V

f

= 200 ksps

SAMPLE

= +3.6V,

A

= 200 ksps

SAMPLE

= 0 ksps

SAMPLE

= +5.25V, f

A

= 0 ksps

SAMPLE

= +3.6V 1.7 4.7 mW (max)

A

= +5.25V, f

A

= 0 ksps

SAMPLE

= +5.25V, f

A

= 0 ksps

SAMPLE

AC ELECTRICAL CHARACTERISTICS

f

SCLK

f

S

t

CONV

Clock Frequency (Note 8)

Sample Rate (Note 8)

Conversion Time 16 SCLK cycles

= 4 MHz to 10 MHz, f

SCLK

MIN

A

to T

: all other limits TA= 25˚C.

MAX

= 200 ksps to 500 ksps,

SAMPLE

A

±

0.1

= 200 µA VA− 0.07 VA− 0.2 V (min)

=1mA VA− 0.1 V

±

0.1

1.66 3.0 mA (max)

0.46 1.3 mA (max)

= 0 MHz,

SCLK

SCLK

SCLK

SCLK

= 10 MHz,

= 0 MHz,

= 10 MHz,

500 nA

60 µA

2.6 µW

315 µW

Limits

(Note 9)

±

1 µA (max)

±

1 µA (max)

±

10 µA (max)

Units

2.7 V (min)

5.25 V (max)

4 MHz (min)

10 MHz (max)

200 ksps (min)

500 ksps (max)

V

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ADC121S051 Converter Electrical Characteristics (Notes 7, 9) (Continued)

The following specifications apply for VA= +2.7V to 5.25V, f

= 15 pF, unless otherwise noted. Boldface limits apply for TA=T

C

L

Symbol Parameter Conditions Typical

AC ELECTRICAL CHARACTERISTICS

DC SCLK Duty Cycle f

t

ACQ

Track/Hold Acquisition Time 400 ns (max)

= 10 MHz 50

SCLK

Throughput Time Acquisition Time + Conversion Time 20 SCLK cycles

t

QUIET

t

AD

t

AJ

(Note 10) 50 ns (min)

Aperture Delay 3 ns

Aperture Jitter 30 ps

= 4 MHz to 10 MHz, f

SCLK

MIN

to T

= 200 ksps to 500 ksps,

SAMPLE

: all other limits TA= 25˚C.

MAX

Limits

(Note 9)

40 % (min)

60 % (max)

Units

ADC121S051 Timing Specifications

The following specifications apply for VA= +2.7V to 5.25V, GND = 0V, f
f

= 200 ksps to 500 ksps, Boldface limits apply for TA=T

SAMPLE

MIN

Symbol Parameter Conditions Typical Limits Units

t

CS

t

SU

t

EN

t

ACC

t

CL

t

CH

t

H

t

DIS

t

POWER-UP

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.

Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supply (that is, V

mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute
Maximum Rating specification does not apply to the V

Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms.

Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages.

Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 8: This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under

Operating Ratings.

Note 9: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Note 10: Minimum Quiet Time required by bus relinquish and the start of the next conversion.

Note 11: Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V.

Note 12: Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V or 2.0V.

Note 13: t

to remove the effects of charging or discharging the output capacitance. This means that t

Minimum CS Pulse Width 10 ns (min)

CS to SCLK Setup Time 10 ns (min)

Delay from CS Until SDATA TRI-STATE

®

Disabled (Note 11)

= +2.7V to +3.6V 40 ns (max)

Data Access Time after SCLK Falling Edge
(Note 12)

V

A

V

= +4.75V to +5.25V 20 ns (max)

A

SCLK Low Pulse Width 0.4xt

SCLK High Pulse Width 0.4xt

= +2.7V to +3.6V 7 ns (min)

V

SCLK to Data Valid Hold Time

SCLK Falling Edge to SDATA High
Impedance (Note 13)

A

V

= +4.75V to +5.25V 5 ns (min)

A

= +2.7V to +3.6V

V

A

V

= +4.75V to +5.25V

A

Power-Up Time from Full Power-Down 1 µs

<

GND or V

IN

pin. The current into the VApin is limited by the Analog Supply Voltage specification.

A

max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the

), and the ambient temperature (TA), and can be calculated using the formula PDmax=(TJmax − TA)/θJA. The values

JA

is derived from the time taken by the outputs to change by 0.5V with the timing test circuit shown in Figure 1. The measured number is then adjusted

DIS

J

= 4.0 MHz to 10.0 MHz, CL=25pF,

SCLK

to T

: all other limits TA= 25˚C.

MAX

20 ns (max)

SCLK

SCLK

25 ns (max)

6 ns (min)

25 ns (max)

5 ns (min)

>

VA), the current at that pin should be limited to 10 mA. The 20

IN

is the true bus relinquish time, independent of the bus loading.

DIS

ns (min)

ns (min)

ADC121S051

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