National Semiconductor ADC12048 Technical data

ADC12048
12-Bit Plus Sign 216 kHz 8-Channel Sampling
Analog-to-Digital Converter

General Description

Operating from a single 5V power supply, the ADC12048 is a
12 bit + sign, parallel I/O, self-calibrating, sampling
analog-to-digital converter (ADC) with an eight input fully
differential analog multiplexer. The maximum sampling rate
is 216 kHz. On request, the ADC goes through a
self-calibration process that adjusts linearity, zero and
full-scale errors.

The ADC12048’s 8-channel multiplexer is software program­mable to operate in a variety of combinations of
single-ended, differential, or pseudo-differential modes. The
fully differential MUX and the 12-bit + sign ADC allows for the
difference between two signals to be digitized.

The ADC12048 can be configured to work with many popular
microprocessors/microcontrollers and DSPs including Na­tional’s HPC family, Intel386 and 8051, TMS320C25, Mo­torola MC68HC11/16, Hitachi 64180 and Analog Devices
ADSP21xx.

For complementary voltage references see the LM4040,
LM4041 or LM9140.

Features

n 8-channel programmable Differential or Single-Ended

multiplexer

n Programmable Acquisition Times and user-controllable

Throughput Rates

n Programmable data bus width (8/13 bits)
n Built-in Sample-and-Hold
n Programmable Auto-Calibration and Auto-Zero cycles
n Low power standby mode
n No missing codes

Key Specifications

(f

= 12 MHz)

CLK

n Resolution 12-bits + sign
n 13-bit conversion time 3.6 µs, max
n 13-bit throughput rate 216 ksamples/s, min
n Integral Linearity Error (ILE)
n Single Supply +5V
n V

Range GND to VA+

IN

n Power consumption

— Normal operation 34 mW, max
— Stand-by mode 75 µw, max

Applications

n Medical instrumentation
n Process control systems
n Test equipment
n Data logging
n Inertial guidance

August 2002

±

1 LSB, max

±

10%

ADC12048 12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter

Block Diagram

01238701

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

© 2002 National Semiconductor Corporation DS012387 www.national.com

Connection Diagrams

ADC12048

PLCC Package PQFP Package

Order Number ADC12048CIV

See NS Package Number V44A

01238702

Order Number ADC12048CIVF

01238703

See NS Package Number VGZ44A

Ordering Information

Industrial Temperature Range Package

−40˚C ≤ T

≤ +85˚C

A

ADC12048CIV PLCC

ADC12048CIVF PQFP

Pin Description

PLCC Pkg. PQFP Pkg. Pin Name Description

Pin Number Pin Number

6 44 CH0 The eight analog inputs to the Multiplexer. Active channels are selected

7 1 CH1

8 2 CH2

9 3 CH3

15 9 CH4

16 10 CH5

17 11 CH6

18 12 CH7

14 8 COM This pin is another analog input pin used as a pseudo ground when the

13 7 V

+ Positive reference input. The operating voltage range for this input is

REF

based on the contents of bits b3–b0 of the Configuration register. Refer
to section titled MUX for more details.

multiplexer is configured in single-ended mode.

1V ≤ V

+ ≤ VA+ (see Figure 3 and 4). This pin should be bypassed to

REF

AGND at least with a parallel combination of a 10 µF and a 0.1 µF
(ceramic) capacitors. The capacitors should be placed as close to the
part as possible.

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Pin Description (Continued)

PLCC Pkg. PQFP Pkg. Pin Name Description

Pin Number Pin Number

12 6 V

19 13 MUX OUT− The inverting (negative) and non-inverting (positive) outputs of the

21 15 MUX OUT+

20 14 ADCIN− ADC inputs. The inverting (negative) and non-inverting (positive) inputs

22 16 ADCIN+

24 18 WMODE The logic state of this pin at power-up determines which edge of the

25 19 SYNC The SYNC pin can be programmed as an input or an output. The

26–31 20–25 D0–D5 13-bit Data bus of the ADC12048. D12 is the most significant bit and D0

34–40 29–34 D6–D12

43 37 CLK The clock input pin used to drive the ADC12048. The operating range is

44 38 WR

139RDRD is the active low read control input pin. A logic low on this pin and

240CSCS is the active low Chip Select input pin. Used in conjunction with the

3 41 RDY

4 42 STDBY This is the standby active low output pin. This pin is low when the

10 4 V

− Negative reference input. The operating voltage range for this input is

REF

0V ≤ V

REF

− ≤ V

+ −1 (see Figure 3 and 4). This pin should be

REF

bypassed to AGND at least with a parallel combination of a 10 µF and a

0.1 µF (ceramic) capacitor. The capacitors should be placed as close to
the part as possible.

multiplexer. The analog inputs to the MUX selected by bits b3–b0 of the
Configuration register appear at these pins.

into the ADC.

write signal (WR) will latch in data from the data bus. If tied low, the
ADC12048 will latch in data on the rising edge of the WR signal. If tied
to a logic high, data will he latched in on the falling edge of the WR
signal. The state of this pin should not be changed after power-up.

Configuration register’s bit b8 controls the function of this pin. When
programmed as an input pin (b8 = 1), a rising edge on this pin causes
the ADC’s sample-and-hold to hold the analog input signal and begin
conversion. When programmed as an output pin (b8 = 0), the SYNC pin
goes high when a conversion begins and returns low when completed.

is the least significant. The BW (bus width) bit of the Configuration
register (b12) selects between an 8-bit or 13-bit data bus width. When
the BW bit is cleared (BW = 0), D7–D0 are active and D12–D8 are
always in TRI-STATE. When the BW bit is set (BW = 1), D12–D0 are
active.

0.05 MHz to 12 MHz.

WR is the active low WRITE control input pin. A logic low on this pin and
the CS will enable the input buffers of the data pins D12–D0. The signal
at this pin is used by the ADC12048 to latch in data on D12–D0. The
sense of the WMODE pin at power-up will determine which edge of the
WR signal the ADC12048 will latch in data. See WMODE pin description.

CS will enable the active output buffers to drive the data bus.

WR and RD signals to control the active data bus input/output buffers of
the data bus.

RDY is an active low output pin. The signal at this pin indicates when a
requested function has begun or ended. Refer to section Functional
Description and the digital timing diagrams for more detail.

ADC12048 is in the standby mode and high when the ADC12048 is out
of the standby mode or has been requested to leave the standby mode.

+ Analog supply input pin. The device operating supply voltage range is

A

±

10%. Accuracy is guaranteed only if the VA+ and VD+ are

+5V
connected to the same potential. This pin should be bypassed to AGND
with a parallel combination of a 10 µF and a 0.1 µF (ceramic) capacitor.
The capacitors should be placed as close to the supply pins of the part
as possible.

ADC12048

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Pin Description (Continued)

PLCC Pkg. PQFP Pkg. Pin Name Description

Pin Number Pin Number

ADC12048

11 5 AGND Analog ground pin. This is the device’s analog supply ground connection.

It should be connected through a low resistance and low inductance
ground return to the system power supply.

32 and 41 26 and 35 V

33 and 42 27 and 36 DGND Digital ground pin. This is the device’s digital supply ground connection.

+ Digital supply input pins. The device operating supply voltage range is

D

±

10%. Accuracy is guaranteed only if the VA+ and VD+ are

+5V
connected to the same potential. This pin should be bypassed to DGND
with a parallel combination of a 10 µF and a 0.1 µF (ceramic) capacitor.
The capacitors should be placed as close to the supply pins of the part
as possible.

It should be connected through a low resistance and low inductance
ground return to the system power supply.

www.national.com 4

ADC12048

Absolute Maximum Ratings (Notes 1,

ESD Susceptibility (Note 5) 3.0 kV

2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V

Voltage at all Inputs −0.3V to V

|V

+−VD+| 300 mV

A

+ and VD+) 6.0V

A

+

+ 0.3V

|AGND − DGND| 300 mV

Input Current at Any Pin (Note 3)

Package Input Current (Note 3)

±

30 mA

±

120 mA

Power Dissipation (Note 4)

at T

= 25˚C 875 mW

A

Storage Temperature −65˚C to +150˚C

Lead Temperature

VF Package

Vapor Phase (60 sec.) 210˚C

Operating Ratings (Notes 1, 2, 6, 7, 8, 9)

Temperature Range

(T

≤ TA≤ T

min

Supply Voltage

V

+, VD+ 4.5V to 5.5V

A

|V

+−VD+| ≤100 mV

A

|AGND − DGND| ≤100 mV

V

Voltage Range

IN

at all Inputs GND ≤ V

V

+ Input Voltage 1V ≤ V

REF

V

− Input Voltage 0 ≤ V

REF

V

+−V

REF

V

REF

REF

Common Mode

(Note 16)

) −40˚C ≤ TA≤ 85˚C

max

− ≤ V

REF

−1V≤ V

0.1 VA+ ≤ V

REF

REF

REF

REFCM

≤ VA+

IN

+ ≤ VA+

+−1V

≤ VA+

≤ 0.6

Infared (15 sec.) 220˚C

V Package, Infared (15 sec.) 300˚C

Converter DC Characteristics

The following specifications apply to the ADC12048 for VA+=VD+ = 5V, V
sion mode, f

= 12.0 MHz, RS=25Ω, source impedance for V

CLK

common-mode voltage (V

=T

MIN

to T

; all other limits TA=TJ= 25˚C

MAX

), and minimum acquisition time, unless otherwise specified. Boldface limits apply for TA=T

INCM

REF

+ and V

Symbol Parameter Conditions Typical Limits Unit

Resolution with No Missing Codes After Auto-Cal 13 Bits (max)

ILE Integral Linearity Error After Auto-Cal

(Notes 12, 17)

+ = 4.096V, V

REF

− ≤ 1Ω, fully differential input with fixed 2.048V

REF

− = 0.0V, 12-bit + sign conver-

REF

(Note 10) (Note 11) (Limit)

±

0.6

±

1 LSB (max)

+

V

A

J

DNL Differential Non-Linearity After Auto-Cal

±

1 LSB (max)

Zero Error After Auto-Cal (Notes 13, 17)

V

= 5.0V

INCM

V

= 2.048V

INCM

V

=0V

INCM

Positive Full-Scale Error After Auto-Cal (Notes 12, 17)

Negative Full-Scale Error After Auto-Cal (Notes 12, 17)

DC Common Mode Error After Auto-Cal (Note 14)

TUE Total Unadjusted Error After Auto-Cal (Note 18)

±

1.0

±

1.0

±

2

±

1 LSB

±

5.5 LSB (max)

±

2.5 LSB (max)

±

5.5 LSB (max)

±

2.5 LSB (max)

±

2.5 LSB (max)

±

5.5 LSB (max)

Power Supply Characteristics

The following specifications apply to the ADC12048 for VA+=VD+ = 5V, V
sion mode, f

= 12.0 MHz, RS=25Ω, source impedance for V

CLK

REF

+ and V

common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T

to T

; all other limits TA=TJ= 25˚C

MAX

Symbol Parameter Conditions Typical Limits Unit

PSS Power Supply Sensitivity V

Zero Error V

Full-Scale Error V

+=VA+ = 5.0V±10% (Note 15)

D

+ = 4.096V

REF

−=0V

REF

Linearity Error

+ = 4.096V, V

REF

− ≤ 1Ω, fully differential input with fixed 2.048V

REF

− = 0.0V, 12-bit + sign conver-

REF

A=TJ=TMIN

(Note 10) (Note 11) (Limit)

±

0.1 LSB

±

0.5 LSB

±

0.1 LSB

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Power Supply Characteristics (Continued)

The following specifications apply to the ADC12048 for VA+=VD+ = 5V, V
sion mode, f

ADC12048

common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T
to T

; all other limits TA=TJ= 25˚C

MAX

= 12.0 MHz, RS=25Ω, source impedance for V

CLK

REF

+ and V

Symbol Parameter Conditions Typical Limits Unit

I

+V

D

+ Digital Supply Current Start Command (Performing a

D

conversion) with SYNC configured as an
input and driven with a 214 kHz signal.
Bus width set to 13.

= 12.0 MHz, Reset Mode 850 µA

f

CLK

f

= 12.0 MHz, Conversion 2.45 2.8 mA (max)

CLK

I

+V

A

+ Analog Supply Current Start Command (Performing a

A

conversion) with SYNC configured as an
input and driven with a 214 kHz signal.
Bus width set to 13.

= 12.0 MHz, Reset Mode 2.3 mA

f

CLK

f

= 12.0 MHz, Conversion 2.3 4.0 mA (max)

CLK

I

ST

Standby Supply Current Standby Mode

(I

++IA+) f

D

= Stopped 5 15 µA (max)

CLK

f

= 12.0 MHz 100 120 µA (max)

CLK

+ = 4.096V, V

REF

− ≤ 1Ω, fully differential input with fixed 2.048V

REF

− = 0.0V, 12-bit + sign conver-

REF

A=TJ=TMIN

(Note 10) (Note 11) (Limit)

Analog MUX Inputs Characteristics

The following specifications apply to the ADC12048 for VA+=VD+= 5V, V
sion mode, f

= 12.0 MHz, RS=25Ω, source impedance for V

CLK

REF

+ and V

common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T

to T

; all other limits TA=TJ= 25˚C

MAX

Symbol Parameter Conditions Typical Limits Unit

I

ON

I

OFF

I

ADCIN

R

C

ON

MUX

MUX ON Channel Leakage
Current

MUX OFF Channel Leakage
Current

ON Channel = 5V, OFF Channel = 0V 0.05 1.0 µA (min)

ON Channel = 0V, OFF Channel = 5V −0.05 −1.0 µA (max)

ON Channel = 5V, OFF Channel = 0V 0.05 1.0 µA (min)

ON Channel = 0V, OFF Channel = 5V −0.05 −1.0 µA (max)

ADCIN Input Leakage Current 0.05 2.0 µA (max)

MUX On Resistance VIN= 2.5V 310 500 Ω (max)

MUX Channel-to-Channel R
Matching

ON

V

IN

= 2.5V

MUX Channel and COM Input
Capacitance

C

ADC

C

MUXOUT

ADCIN Input Capacitance 70 pF

MUX Output Capacitance 20 pF

+ = 4.096V, V

REF

+ ≤ 1Ω, fully differential input with fixed 2.048V

REF

− = 0.0V, 12-Bit + sign conver-

REF

A=TJ=TMIN

(Note 10) (Note 11) (Limit)

±

20% Ω

10 pF

Reference Inputs

The following specifications apply to the ADC12048 for VA+=VD+ = 5V, V
sion mode, f

= 12.0 MHz, RS=25Ω, source impedance for V

CLK

REF

+ and V

common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T

to T

; all other limits TA=TJ= 25˚C

MAX

Symbol Parameter Conditions Typical Limits Unit

I

REF

Reference Input Current V

+ 4.096V, V

REF

REF−

=0V

Analog Input Signal: 1 kHz 145 µA

(Note 20) 80 kHz 136 µA

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+ = 4.096V, V

REF

− ≤ 1Ω, fully differential input with fixed 2.048V

REF

− = 0.0V, 12-bit + sign conver-

REF

A=TJ=TMIN

(Note 10) (Note 11) (Limit)

Reference Inputs (Continued)

The following specifications apply to the ADC12048 for VA+=VD+ = 5V, V
sion mode, f

= 12.0 MHz, RS=25Ω, source impedance for V

CLK

REF

+ and V

common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T

to T

; all other limits TA=TJ= 25˚C

MAX

Symbol Parameter Conditions Typical Limits Unit

C

REF

Reference Input
Capacitance

+ = 4.096V, V

REF

− ≤ 1Ω, fully differential input with fixed 2.048V

REF

− = 0.0V, 12-bit + sign conver-

REF

A=TJ=TMIN

(Note 10) (Note 11) (Limit)

85 pF

Digital Logic Input/Output Characteristics

The following specifications apply to the ADC12048 for VA+=VD+ = 5V, V
sion mode, f

= 12.0 MHz, RS=25Ω, source impedance for V

CLK

REF

+ and V

common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T

to T

; all other limits TA=TJ= 25˚C

MAX

Symbol Parameter Conditions Typical Limits Unit

V

V

I

I

V

V

I

C

IH

IL

IH

IL

OH

OL

OFF

IN

Logic High Input Voltage VA+=VD+ = 5.5V 2.0 V (min)

Logic Low Input Voltage VA+=VD+ = 4.5V 0.8 V (max)

Logic High Input Current VIN= 5V 0.035 2.0 µA (max)

Logic Low Input Current VIN= 0V −0.035 −2.0 µA (max)

Logic High Output Voltage VA+=VD+ = 4.5V

I

= −1.6 mA

OUT

Logic Low Output Voltage VA+=VD+ = 4.5V

I

= 1.6 mA

OUT

TRI-STATE®Output
Leakage Current

V

=0V

OUT

=5V

V

OUT

D12–D0 Input Capacitance 10 pF

+ = 4.096V, V

REF

− ≤ 1Ω, fully differential input with fixed 2.048V

REF

− = 0.0V, 12-bit + sign conver-

REF

A=TJ=TMIN

(Note 10) (Note 11) (Limit)

2.4 V (min)

0.4 V (max)

±

2.0 µA (max)

ADC12048

Converter AC Characteristics

The following specifications apply to the ADC12048 for VS+=VD+ = 5V, V
sion mode, f

= 12.0 MHz, RS=25Ω, source impedance for V

CLK

REF

+ and V

common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T

to T

; all other limits TA=TJ= 25˚C

MAX

Symbol Parameter Conditions Typical Limits Unit

t

t

Z

CAL

Auto Zero Time 78 78 clks + 120 ns clks (max)

Full Calibration Time 4946 4946 clks + 120 ns clks (max)

CLK Duty Cycle 50 %

t

CONV

t

AcqSYNCOUT

Conversion Time Sync-Out Mode 44 44 clks (max)

Acquisition Time
(Programmable)

Minimum for 13 Bits 9 9 clks + 120 ns clks (max)

Maximum for 13 Bits 79 79 clks + 120 ns clks (max)

+ = 4.096V, V

REF

− ≤ 1Ω, fully differential input with fixed 2.048V

REF

− = 0.0V, 12-bit + sign conver-

REF

A=TJ=TMIN

(Note 10) (Note 11) (Limit)

40 % (min)

60 % (max)

Digital Timing Characteristics

The following specifications apply to the ADC12048, 13-bit data bus width, VA+=VD+ = 5V, f
= 50 pF on data I/O lines

Symbol Parameter Conditions Typical Limits Units

t

TPR

Throughput Rate Sync-Out Mode (SYNC Bit =

“0”) 9 Clock Cycles of
Acquisition Time

= 12 MHz, tf= 3 ns and C

CLK

(Note 10) (Note 11) (Limit)

222 kHz

L

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Digital Timing Characteristics (Continued)

The following specifications apply to the ADC12048, 13-bit data bus width, VA+=VD+ = 5V, f
= 50 pF on data I/O lines

ADC12048

Symbol Parameter Conditions Typical Limits Units

t

CSWR

t

WRCS

t

WR

t

WRSETFalling

t

WRHOLDFalling

t

WRSETRising

t

WRHOLDRising

t

CSRD

t

RDCS

t

RDDATA

t

RDDATA

t

RDHOLD

t

RDRDY

t

WRRDY

t

STNDBY

Falling Edge of CS to Falling Edge of WR 0ns

Active Edge of WR to Rising Edge of CS 0ns

WR Pulse Width 20 30 ns (min)

Write Setup Time WMODE = “1” 20 ns (min)

Write Hold Time WMODE = “1” 5 ns (min)

Write Setup Time WMODE = “0” 20 ns (min)

Write Hold Time WMODE = “0” 5 ns (min)

Falling Edge of CS to Falling Edge of RD 0ns

Rising Edge of RD to Rising Edge of CS 0ns

Falling Edge of RD to Valid Data 8-Bit Mode (BW Bit = “0”) 40 58 ns (max)

Falling Edge of RD to Valid Data 13-Bit Mode (BW Bit = “1”) 26 44 ns (max)

Read Hold Time 23 32 ns (max)

Rising Edge of RD to Rising Edge of RDY 24 38 ns (max)

Active Edge of WR to Rising Edge of RDY WMODE = “1” 42 65 ns (max)

Active Edge of WR to Falling Edge of
STDBY

WMODE = “0”. Writing the
Standby Command into the
Configuration Register

t

STDONE

Active Edge of WR to Rising Edge of
STDBY

WMODE = “0”. Writing the
RESET Command into the
Configuration Register

t

STDRDY

Active Edge of WR to Falling Edge of RDY WMODE = “0”. Writing the

RESET Command into the
Configuration Register

t

SYNC

Minimum SYNC Pulse Width 5 10 ns (min)

= 12 MHz, tf= 3 ns and C

CLK

(Note 10) (Note 11) (Limit)

200 230 ns (max)

30 45 ns (max)

1.4 2.5 ms (max)

L

Notes on Specifications

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified.

Note 3: When the input voltage (V

30 mA. The 120 mA maximum package input current limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.

Note 4: The maximum power dissipation must he derated at elevated temperatures and is dictated by T
junction to ambient thermal resistance), and T
or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T
in the V package, when board mounted, is 55˚C/W, and in the VF package, when board mounted, is 67.8˚C/W.

Note 5: Human body model, 100 pF discharged through 1.5 kΩ resistor.

Note 6: Each input and output is protected by a nominal 6.5V breakdown voltage zener diode to GND; as shown below, input voltage magnitude up to 0.3V above

V

+ or 0.3V below GND will not damage the ADC12048. There are parasitic diodes that exist between the inputs and the power supply rails and errors in the A/D

A

conversion can occur if these diodes are forward biased by more than 50 mV.As an example, if V
accurate conversions.

) at any pin exceeds the power supply rails (V

IN

(ambient temperature). The maximum allowable power dissipation at any temperature is P

A

IN

<

GND or V

Jmax

>

(VA+orVD+)), the current at that pin should be limited to

IN

, (maximum junction temperature), θJA(package

Jmax

= 150˚C, and the typical thermal resistance (θJA) of the ADC12048

+ is 4.50 VDC, full-scale input voltage must be ≤ 4.55 VDCto ensure

A

Dmax

=(T

Jmax−TA

)/θ

JA

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Notes on Specifications (Continued)

01238704

Note 7: VA+ and VD+ must be connected together to the same power supply voltage and bypassed with separate capacitors at each V+pin to assure
conversion/comparison accuracy. Refer to the Power Supply Considerations section for a detailed discussion.

Note 8: Accuracy is guaranteed when operating at f

Note 9: With the test condition for V

Note 10: Typicals are at T

Note 11: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive

full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero.

Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value of the code transitions
between −1 to 0 and 0 to +1 (see Figure 8).

Note 14: The DC common-mode error is measured with both inputs shorted together and driven from 0V to 5V. The measured value is referred to the resulting
output value when the inputs are driven with a 2.5V input.

Note 15: Power Supply Sensitivity is measured after an Auto-Zero and Auto Calibration cycle has been completed with V

Note 16: V

REFCM

= 25˚C and represent most likely parametric norm.

A

(Reference Voltage Common Mode Range) is defined as

REF(VREF

+−V

= 12 MHz.

CLK

−) given as +4.096V, the 12-bit LSB is 1.000 mV.

REF

+ and VD+ at the specified extremes.

A

ADC12048

Note 17: The ADC12048’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result in

a repeatability uncertainly of

Note 18: Total Unadjusted Error (TUE) includes offset, full scale linearity and MUX errors.

Note 19: The ADC12048 parts used to gather the information for these curves were auto-calibrated prior to taking the measurements at each test condition. The

auto-calibration cycle cancels any first order drifts due to test conditions. However, each measurement has a repeatability uncertainty error of 0.2 LSB. See (Note

17).

Note 20: The reference input current is a DC average current drawn by the reference input with a full-scale sinewave input. The ADC12048 is continuously
converting with a throughput rate of 206 kHz.

Note 21: These typical curves were measured during continuous conversions with a positive half-scale DC input. A 240 ns RD pulse was applied 25 ns after the
RDY signal went low. The data bus lines were loaded with 2 HC family CMOS inputs (CL∼ 20 pF).

Note 22: Any other values placed in the command field are meaningless. However, if a code of 101 or 110 is placed in the command field and the CS, RD and WR
go low at the same time, the ADC12048 will enter a test mode. These test modes are only to be used by the manufacturer of this device. A hardware power-off and
power-on reset must be done to get out of these test modes.

±

0.20 LSB.

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Electrical Characteristics

ADC12048

01238705

FIGURE 1. Output Digital Code vs the Operating Input Voltage Range (General Case)

FIGURE 2. Output Digital Code vs the Operating Input Voltage Range for V

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REF

01238706

= 4.096V

Electrical Characteristics (Continued)

ADC12048

FIGURE 3. V

Operating Range (General Case)

REF

01238707

FIGURE 4. V

Operating Range for VA=5V

REF

01238708

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Electrical Characteristics (Continued)

ADC12048

01238709

FIGURE 5. Transfer Characteristic

FIGURE 6. Simplified Error vs Output Code without Auto-Calibration or Auto-Zero Cycles

01238710

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Electrical Characteristics (Continued)

FIGURE 7. Simplified Error vs Output Code after Auto-Calibration Cycle

ADC12048

01238711

FIGURE 8. Offset or Zero Error Voltage (Note 13)

01238712

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Timing Diagrams

ADC12048

FIGURE 9. Sync-Out Write (WMODE = 1, BW = 1), Read and Convert Cycles

01238713

FIGURE 10. Sync-In Write (WMODE = 1, BW = 1), Read and Convert Cycles

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01238714

Timing Diagrams (Continued)

ADC12048

FIGURE 11. Sync-Out Write (WMODE = 0, BW = 1), Read and Convert Cycles

01238746

FIGURE 12. Sync-In Write (WMODE = 0, BW = 1), Read and Convert Cycles

01238747

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Timing Diagrams (Continued)

ADC12048

FIGURE 13. Sync-Out Read and Convert Cycles. The MUX channel

is the channel selected on the most recent write cycle.

01238748

FIGURE 14. Sync-In Read and Convert Cycles. The MUX channel

is the channel selected on the most recent write cycle.

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01238749

Timing Diagrams (Continued)

ADC12048

FIGURE 15. 8-Bit Bus Read Cycle (Sync-Out)

01238750

FIGURE 16. 8-Bit Bus Read Cycle (Sync-In)

01238751

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Timing Diagrams (Continued)

ADC12048

FIGURE 17. Write Signal Negates RDY (Writing the Standby, Auto-Cal or Auto-Zero Command)

01238715

FIGURE 18. Standby and Reset Timing (13-Bit Data Bus Width)

01238716

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Typical Performance Characteristics (See (Note 19), Electrical Characteristic Section)

Integral Linearity Error (INL) Change vs. Clock

Frequency Full-Scale Error Change vs. Clock Frequency

ADC12048

01238717

01238718

Zero Error Change vs. Clock Frequency Integral Linearity Error (INL) Change vs. Temperature

01238719

01238720

Full-Scale Error Change vs. Temperature Zero Error Change vs. Temperature

01238721 01238722

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Typical Performance Characteristics (See (Note 19), Electrical Characteristic Section) (Continued)

ADC12048

Integral Linearity Error (INL) Change vs. Reference

Voltage Full-Scale Error Change vs. Reference Voltage

01238723

01238724

Zero Error Change vs. Reference Voltage Integral Linearity Error (INL) Change vs. Supply Voltage

01238725 01238739

Full-Scale Error Change vs. Supply Voltage Zero Error Change vs. Supply Voltage

01238740

01238741

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Typical Performance Characteristics (See (Note 21), Electrical Characteristic Section)

Supply Currents vs. Clock Frequency Reference Currents vs. Clock Frequency

01238742 01238743

Analog Supply Current vs. Temperature Digital Supply Current vs. Temperature

ADC12048

01238744

Full Scale Differential 1,099 Hz

Sine Wave Input

01238726

01238745

Full Scale Differential 18,677 Hz

Sine Wave Input

01238727

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Typical Performance Characteristics (See (Note 21), Electrical Characteristic Section) (Continued)

ADC12048

Full Scale Differential 38,452 Hz

Sine Wave Input

Half Scale Differential 1 kHz

Sine Wave Input, f

= 153.6 kHz

S

Full Scale Differential 79,468 Hz

Sine Wave Input

01238728 01238729

Half Scale Differential 20 kHz

Sine Wave Input, fS= 153.6 kHz

Half Scale Differential 40 kHz

Sine Wave Input, f

= 153.6 kHz

S

01238730 01238731

Half Scale Differential 75 kHz

Sine Wave Input, fS= 153.6 kHz

01238732

01238733

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Register Bit Description

CONFIGURATION REGISTER (Write Only)

This is a 13-bit write-only register that is used to program the
functionality of the ADC12048. All data written to the
ADC12048 will always go to this register only. The contents

MSB LSB

b

12

b

11

b

10

b

b

9

b

8

7

BW COMMAND FIELD SYNC HB SE ACQ TIME MUX ADDRESS

of this register cannot be read.

b

b

6

5

b

4

b

3

b

b

2

ADC12048

b

1

0

Power on State: 0100Hex

: The MUX ADDRESS bits configure the analog input

b

3–b0

MUX. They select which input channels of the MUX will

TABLE 1. MUX Channel Assignment

b

3

b

2

b

1

0 0 0 0 CH0 CH1

0 0 0 1 CH1 CH0

0 0 1 0 CH2 CH3

0 0 1 1 CH3 CH2

0 1 0 0 CH4 CH5

0 1 0 1 CH5 CH4

0 1 1 0 CH6 CH7

0 1 1 1 CH7 CH6

1 0 0 0 CH0 COM

1 0 0 1 CH1 COM

1 0 1 0 CH2 COM

1 0 1 1 CH3 COM

1 1 0 0 CH4 COM

1 1 0 1 CH5 COM

1 1 1 0 CH6 COM

1 1 1 1 CH7 COM

b

: The ACQ TIME bits select one of four possible ac-

5–b4

quistion times in SYNC-OUT mode. (Refer to Selectable

connect to the MUXOUT+ and MUXOUT− pins. (Refer to the
MUX section for more details on the MUX.) Power-up value
is 0000.

b

0

MUXOUT+ MUXOUT−

Acquisition Time section.)

b

5

00 9

01 15

10 47

11 79

b

: When the Single-Ended bit (SE bit) is set, conversion

6

results will be limited to positive values only and any nega­tive conversion results will appear as a code of zero in the
Data register. The SE bit is cleared at power-up.

: The High Byte bit (HB) is meaningful only in 8-bit mode

b

7

(BW bit b
(BW bit b

= “0”) and is a don’t care condition in 13-bit mode

12

= “1”). This bit is used to access the upper byte

12

of the Configuration Register in 8-bit mode. When this bit is
set and bit b

= 0, the next byte written to the ADC12048

12

will program the upper byte of the Configuration register. The
HB bit will automatically be cleared when data is written to
the upper byte of the Configuration register, allowing the
lower byte to be accessed with the next write. The HB bit is
cleared at power-up.

b

Clocks

4

: The SYNC bit. When the SYNC bit is set, the SYNC pin

b

8

is programmed as an input and the converter is in synchro­nous mode. In this mode a rising edge on the SYNC pin
causes the ADC to hold the input signal and begin a conver­sion. When b

cleared, the SYNC pin is programmed as an

15

output and the converter is in an asynchronous mode. In this
mode the signal at the SYNC pin indicates the status of the
converter. The SYNC pin is high when a conversion is taking
place. The SYNC bit is set at power-up.

: The command field. These bits select the mode of

b

11–b9

operation of the ADC12048. Power-up value is 000. (See
(Note 22))

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Register Bit Description (Continued)

b

11

ADC12048

0 0 0 Standby command. This puts the ADC in a low power consumption mode

b

10

b

9

Command

0 0 1 Ful-Cal command. This will cause the ADC to perform a self-calibrating cycle that will correct

linearity and zero errors.

0 1 0 Auto-zero command. This will cause the ADC to perform an auto-zero cycle that corrects offset

errors.

0 1 1 Reset command. This puts the ADC in an idle mode.

1 0 0 Start command. This will put the converter in a start mode, preparing it to perform a conversion.

If in asynchronous mode (b
acquisition time has ended. In synchronous mode (b

= “0”), conversions will immediately begin after the programmed

8

= “1”), conversions will begin after a

8

rising edge appears on the SYNC pin.

: This is the Bus Width (BW) bit. When this bit is a ’0’ the

b

12

ADC12048 is configured to interface with an 8-bit data bus;
data pins D

are active and pins D12–D9are in

7–D0

register on the data bus. When reading the data register in
8-bit mode, the sign bit is extended (b

contain the sign bit).
TRI-STATE. When the BW bit is a ’1’, the ADC12048 is
configured to interface with a 16-bit data bus and data pins
D

are all active. The BW bit is a ’0’ at power-up.

13–D0

DATA REGISTER (Read Only)

This is a 13-bit read only register that holds the 12-bit +sign
conversion result in two’s compliment form. All reads per­formed from the ADC12048 will place the contents of this

MSB LSB

b

12b11b10

b

b

b

b

b

b

b

b

b

9

8

7

6

5

4

3

2

b

1

0

sign Conversion Data

through b8all

12

Power on State: 0000Hex
b

: b11is the most significant bit and b0is the least

11–b0

significant bit of the conversion result.

: This bit contains the sign of the conversion result: 0 for

b

12

positive results and 1 for negative.

Functional Description

The ADC12048 is programmed through a digital interface
that supports an 8-bit or 16-bit data bus. The digital interface
consists of a 13-bit data input/output bus (D

12–D0

), digital

control signals and two internal registers: a write only 13-bit
Configuration register and a read only 13-bit Data register.

The Configuration register programs the functionality of the
ADC12048. The 13 bits of the Configuration register are
divided into 7 fields. Each field controls a specific function of
the ADC12048: the channel selection of the MUX, the acqui­sition time, synchronous or asynchronous conversions,
mode of operation and the data bus size.

Features and Operating Modes

SELECTABLE BUS WIDTH

The ADC12048 can be programmed to interface with an 8-bit
or 16-bit data bus. The BW bit (b
register controls the bus size. The bus width is set to 8 bits
(D
bit is cleared or 13 bits (D

are active and D12–D8are in TRI-STATE) if the BW

7–D0

12–D0

set. At power-up the bus width defaults to 8 bits and any
initial programming of the ADC12048 should take this into
consideration.

In 8-bit mode the Configuration register is byte accessible.
The HB bit in the lower byte of the Configuration register is

) in the Configuration

12

are active) if the BW bit is

used to access the upper byte. If the HB bit is set with a write

to the lower byte, the next byte written to the ADC will be

placed in the upper byte of the Configuration register. After

data is written to the upper byte of the Configuration register,

the HB bit will automatically be cleared, causing the next

byte written to the ADC to go to the lower byte of the

Configuration register. When reading the ADC in 8-bit mode,

the first read cycle places the lower byte of the Data register

on the data bus followed by the upper byte during the next

read cycle.

In 13-bit mode the HB bit is a don’t care condition and all bits

of the data register and Configuration register are accessible

with a single read or write cycle. Since the bus width of the

ADC12048 defaults to 8 bits after power-up, the first action

when 13-bit mode is desired must be set to the bus width to

13 bits.

WMODE

The WMODE pin is used to determine the active edge of the

write pulse. The state of this pin determines which edge of

the WR signal will cause the ADC to latch in data. This is

processor dependent. If the processor has valid data on the

bus during the falling edge of the WR signal, the WMODE

pin must be tied to VD+. This will cause the ADC to latch the

data on the falling edge of the WR signal. If data is valid on

the rising edge of the WR signal, the WMODE pin must be

tied to DGND causing the ADC to latch in the data on the

rising edge of the WR signal.

INPUT MULTIPLEXER

The ADC12048 has an eight channel input multiplexer with a

COM input that can be used in a single-ended,

pseudo-differential or fully-differential mode. The MUX select

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Features and Operating Modes

(Continued)

bits (b
channels will appear at the MUXOUT+ and MUXOUT− mul­tiplexer output pins. (Refer to Register Bit Description Sec­tion.) Analog signal conditioning with fixed-gain amplifiers,
programmable-gain amplifiers, filters and other processing
circuits can be used at the output of the multiplexer before
being applied to the ADC inputs. The ADCIN+ and ADCIN−
are the fully differential non-inverting (positive) and inverting
(negative) inputs to the analog-to-digital converter (ADC) of
the ADC12048. If no external signal conditioning is required
on the signal output of the multiplexer, MUXOUT+ should be
connected to ADCIN+ and MUXOUT− should be connected
to ADCIN−.

The analog input multiplexer can be set up to operate in
either one of eight differential or eight single-ended (the
COM input as the zero reference) modes. In the differential
mode, the analog inputs are paired as follows: CH0 with
CH1, CH2 with CH3, CH4 with CH5 and CH6 with CH7. The
input channel pairs can be connected to the MUXOUT+ and
MUXOUT− pins in any order. In the single-ended mode, one
of the input channels, CH0 through CH7, can be assigned to
MUXOUT+ while the MUXOUT− is always assigned to the
COM input.

STANDBY MODE

The ADC12048 has a low power consumption mode (75 µW

@

5V). This mode is entered when a Standby command is
written in the command field of the Configuration register. A
logic low appearing on the STDBY output pin indicates that
the ADC12048 is in the Standby mode. Any command other
than the Standby command written to the Configuration
register will get the ADC12048 out of the Standby mode. The
STDBY pin will immediately switch to a logic “1” as soon as
the ADC12048 is requested to get out of the standby mode.
The RDY pin will then be asserted low when the ADC is
actually out of the Standby mode and ready for normal
operation. The ADC12048 defaults to the Standby mode
following a hardware power-up. This can be verified by
examining the logic low status of the STDBY pin.

SYNC/ASYNC MODE

The ADC12048 may be programmed to operate in synchro­nous (SYNC-IN) or asynchronous (SYNC-OUT) mode. To
enter synchronous mode, the SYNC bit in the Configuration
register must be set. The ADC12048 is in synchronous mode
after a hardware power-up. In this mode, the SYNC pin is
programmed as an input and conversions are synchronized
to the rising edges of the signal applied at the SYNC pin.
Acquisition time can also be controlled by the SYNC signal
when in synchronous mode. Refer to the sync-in timing
diagrams. When the SYNC bit is cleared, the ADC is in
asynchronous mode and the SYNC pin is programmed as an
output. In asynchronous mode, the signal at the SYNC pin
indicates the status of the converter. This pin is high when
the converter is performing a conversion. Refer to the
sync-out timing diagrams.

SELECTABLE ACQUISITION TIME

The ADC12048’s internal sample/hold circuitry samples an
input voltage by connecting the input to an internal sampling
capacitor (approximately 70 pF) through an effective resis­tance equal to the multiplexer “On” resistance (300Ω max)
plus the “On” resistance of the analog switch at the input to

) in the Configuration register determine which

3–b0

the sample/hold circuit (2500Ω typical) and the effective
output resistance of the source. For conversion results to be
accurate, the period during which the sampling capacitor is
connected to the source (the “acquisition time”) must be long
enough to charge the capacitor to within a small fraction of
an LSB of the input voltage. An acquisition time of 750 ns is
sufficient when the external source resistance is less than
1kΩ and any active or reactive source circuitry settles to
12 bits in less than 500 ns. When source resistance or
source settling time increase beyond these limits, the acqui­sition time must also be increased to preserve precision.

In asynchronous (SYNC-OUT) mode, the acquisition time is
controlled by an internal counter. The minimum acquisition
period is 9 clock cycles, which corresponds to the nominal
value of 750 ns when the clock frequency is 12 MHz. Bits b
and b5of the Configuration Register are used to select the
acquisition time from among four possible values (9, 15, 47,
or 79 clock cycles). Since acquisition time in the asynchro­nous mode is based on counting clock cycles, it is also
inversely proportional to clock frequency:

Note that the actual acquisition time will be longer than T

ACQ

because acquisition begins either when the multiplexer
channel is changed or when RDY goes low, if the multiplexer
channel is not changed. After a read is performed, RDY goes
high, which starts the T

In synchronous (SYNC-IN) mode, bits b

counter (see Figure 9).

ACQ

4

and b5are ignored,
and the acquisition time depends on the sync signal applied
at the SYNC pin. If a new MUX channel is selected at the
start of the conversion, the acquisition period begins on the
active edge of the WR signal that latches in the new MUX
channel. If no new MUX channel is selected, the acquisition
period begins on the falling edge of RDY, which occurs at the
end of the previous conversion (or at the end of an autozero
or autocalibration procedure). The acquisition period ends
when SYNC goes high.

To estimate the acquisition time necessary for accurate con­versions when the source resistance is greater than 1 kΩ,
use the following expression:

where RSis the source resistance, RMis the MUX “On”
resistance, and R

is the sample/hold “On” resistance.

S/H

If the settling time of the source is greater than 500 ns, the
acquisition time should be about 300 ns longer than the
settling time for a “well-behaved”, smooth settling character­istic.

FULL CALIBRATION CYCLE

A full calibration cycle compensates for the ADC’s linearity
and offset errors. The converter’s DC specifications are
guaranteed only after a full calibration has been performed.
A full calibration cycle is initated by writing a Ful-Cal com­mand to the ADC12048. During a full calibration, the offset

ADC12048

4

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Features and Operating Modes

(Continued)

error is measured eight times, averaged and a correction

ADC12048

coefficient is created. The offset correction coefficient is
stored in an internal offset correction register.

The overall Iinearity correction is achieved by correctng the
internal DAC’s capacitor mismatches. Each capacitor is
compared eight times against all remaining smaller value
capacitors. The errors are averaged and correction coeffi­cients are created.

Once the converter has been calibrated, an arithmetic logic
unit (ALU) uses the offset and linearity correction coefficients
to reduce the conversion offset and linearity errors to within
guaranteed limits.

AUTO-ZERO CYCLE

During an auto-zero cycle, the offset is measured only once
and a correction coefficient is created and stored in an
internal offset register. An auto-zero cycle is initiated by
writing an Auto-Zero command to the ADC12048.

DIGITAL INTERFACE

The digital control signals are CS, RD, WR, RDY and
STDBY. Specific timing relationships are associated with the
interaction of these signals. Refer to the Digital Timing Dia­grams section for detailed timing specifications. The active
low RDY signal indicates when a certain event begins and
ends. It is recommended that the ADC12048 should only be
accessed when the RDY signal is low. It is in this state that
the ADC12048 is ready to accept a new command. This will
minimize the effect of noise generated by a switching data
bus on the ADC. The only exception to this is when the
ADC12048 is in the standby mode at which time the RDY is
high and the STDBY signal is low. The ADC12048 is in the
standby mode at power up or when a STANDBY command is
issued. A Ful-Cal, Auto-Zero, Reset or Start command will
get the ADC12048 out of the standby mode. This may be
observed by monitoring the status of the RDY and STDBY
signals. The RDY signal will go low and the STDBY signal
high when the ADC12048 leaves the standby mode.

The following describes the state of the digital control signals
for each programmed event in both 8-bit and 13-bit mode.
RDY should be low before each command is issued except
for the case when the device is in standby mode.

FUL-CAL OR AUTO-ZERO COMMAND

8-bit mode: The first write to the ADC12048 will place the
data in the lower byte of the Configuration register. This byte
must set the HB bit (b
the Configuration register during the next write cycle. During
the second write cycle, the Ful-Cal or Auto-Zero command
must be issued. The edge of the second write pulse on the
WR pin will force the RDY signal high. At this time the
converter begins executing a full calibration or auto-zero
cycle. The RDY signal will automatically go low when the full
calibration or auto-zero cycle is done.

13-bit mode: In a single write cycle the Ful-Cal or Auto-Zero
command must be written to the ADC12048. The edge of the
WR signal will force the RDY high. At this time the converter
begins executing a full calibration or auto-zero cycle. The
RDY signal will automatically go low when the full calibration
or auto-zero cycle is done.

) to allow access to the upper byte of

7

STARTING A CONVERSION: START COMMAND

In order to completely describe the events associated with
the Start command, both the SYNC-OUT and SYNC-IN
modes must be considered.

SYNC-OUT/Asynchronous
8-bit mode: The first byte written to the ADC12048 should set

the MUX channel, the acquisition time and the HB bit. The
second byte should clear the SYNC bit, write the START
command and clear the BW bit. In order to initiate a conver­sion, two reads must be performed from the ADC12048. The
rising edge of the second read pulse will force the RDY pin
high and begin the programmed acquisition time selected by

and b4of the configuration register. The SYNC pin will

bits b

5

go high indicating that a conversion sequence has begun
following the end of the acquisition period. The RDY and
SYNC signal will fall low when the conversion is done.At this
time new information, such as a new MUX channel, acqui­sition time and operational command can be written into the
configuration register or it can remain unchanged. Assuming
that the START command is in the Configuration register, the
previous conversion can be read. The first read places the
lower byte of the conversion result contained in the Data
register on the data bus. The second read will place the
upper byte of the conversion result stored in the Data regis­ter on the data bus. The rising edge on the second read
pulse will begin another conversion sequence and raise the
RDY and SYNC signals appropriately.

13-bit mode: The MUX channel and the acquisition time
should be set, the SYNC bit cleared and the START com­mand issued with a single write to the ADC12048. In order to
initiate a conversion, a single read must be performed from
the ADC12048. The rising edge of the read signal will force
the RDY signal high and begin the programmed acquisition
time selected by bits b5and b4of the configuration register.
The SYNC pin will go high indicating that a conversion
sequence has begun following the end of the acquisition
period. The RDY and SYNC signal will fall low when the
conversion is done. At this time new information, such as a
new MUX channel, acquisition time and operational com­mand can be written into the configuration register or it can
remain unchanged. With the START command in the Con­figuration register, a read from the ADC12048 will place the
entire 13-bit conversion result stored in the data register on
the data bus. The rising edge of the read pulse will immedi­ately force the RDY output high. The SYNC will then go high
following the elapse of the programmed acquisition time in
the configuration register’s bits b

and b4.

5

SYNC-IN/Synchronous

For the SYNC-IN case, it is assumed that a series of SYNC
pulses at the desired sampling rate are applied at the SYNC
pin of the ADC12048.

8-bit mode: The first byte written to the ADC12048 should set
the MUX channel and the HB bit. The second byte should set
the SYNC bit, write the START command and clear the BW
bit.

A rising edge on the SYNC pin or the second rising edge of
two consecutive reads from the ADC12048 will force the
RDY signal high. It is recommended that the action of read­ing from the ADC12048 (not the rising edge of the SYNC
signal) be used to raise the RDY signal. In the SYNC-IN
mode, only the rising edge of the SYNC signal will begin a
conversion cycle. The rising edge of the SYNC also ends the
acquisition period. The acquisition period begins following a
write cycle containing MUX channel information. The se­lected MUX channel is sampled after the rising edge of the

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Features and Operating Modes

(Continued)

ADC12048

a conversion, full-calibration or auto-zero cycle. It can also
be used to get the ADC12048 out of the standby mode.

WR signal until the rising edge of the SYNC pulse, at which
time the signal will be held and conversion begins. The RDY
signal will go low when the conversion is done. A new MUX
channel and/or operational command may be written into the
Configuration register at this time, if needed. Two consecu­tive read cycles are required to retrieve the entire 13-bit
conversion result from the ADC12048’s data register. The
first read will place the lower byte of the conversion result
contained in the Data register on the data bus. The second
read will place the upper byte of the conversion result stored
in the Data register on the data bus. With the START com­mand in the configuration register, the rising edge of the
second read pulse will raise the RDY signal high and begin
a conversion cycle following a rising edge on the SYNC pin.

13-bit mode: The MUX channel should be selected, the
SYNC bit should be set and the START command issued
with a single write to the ADC12048. A rising edge on the
SYNC pin or on the RD pin will force the RDY signal high. It
is recommended that the action of reading from the
ADC12048 (not the rising edge of the SYNC signal) be used
to raise the RDY signal. This will ensure that the conversion
result is read during the acquisition period of the next con­version cycle, eliminating a read from the ADC12048 while it
is performing a conversion. Noise generated by accessing
the ADC12048 while it is converting may degrade the con­version result. In the SYNC-IN mode, only the rising edge of
the SYNC signal will begin a conversion cycle. The RDY
signal will go low when the conversion cycle is done. The
acquisition time is controlled by the SYNC signal. The acqui­sition period begins following a write cycle containing MUX
channel information. The selected MUX channel is sampled
after the rising edge of the WR signal until the rising edge of
the SYNC pulse, at which time the signal will be held and
conversion begins. A new MUX channel and/or operational
command may be written into the Configuration register at
this time, if needed. With the START command in the Con­figuration register, a read from the ADC12048 will place the
entire conversion result stored in the Data register on the
data bus and the rising edge of the read pulse will force the
RDY signal high. The selected MUX channel will be sampled
until a rising edge appears on the SYNC pin, at which the
time sampled signal will be held and a conversion cycle
started.

Analog Application Information

REFERENCE VOLTAGE

The ADC12048 has two reference inputs, V
They define the zero to full-scale range of the analog input
signals over which 4095 positive and 4096 negative codes
exist. The reference inputs can be connected to span the
entire supply voltage range (V

− = AGND, V

REF

or they can be connected to different voltages when other
input spans are required. The reference inputs of the
ADC12048 have transient capacitive switching currents. The
voltage sources driving V

REF

+ and V

REF

low output impedence and noise and must be adequately
bypassed. The circuit in Figure 20 is an example of a very
stable reference source.

The ADC12048 can be used in either ratiometric or absolute
reference appplications. In ratiometric systems, the analog
input voltage is proportional to the voltage used for the
ADC’s reference voltage. This technique relaxes the system
reference requirements because the analog input voltage
moves with the ADC’s reference. The system power supply
can be used as the reference voltage by connecting the

+ pin to VA+ and the V

V

REF

− pin to AGND. For absolute

REF

accuracy, where the analog input voltage varies between
very specific voltage limits, a time and temperature stable
voltage source can be connected to the reference inputs.
Typically, the reference voltage’s magnitude will require an
initial adjustment to null reference voltage induced full-scale
errors.

The reference voltage inputs are not fully differential. The
ADC12048 will not generate correct conversions if

+) – (V

(V

REF

able relationship between V

−) is below 1V. Figure 19 shows the allow-

REF

REF

+ and V

+ and V

REF

+=VA+)

REF

− must have very

−.

REF

REF

−.

STANDBY COMMAND

8-bit mode: The first byte written to the ADC12048 should set
the HB bit in the Configuration register (bit b
byte must issue the Standby command (bits b

). The second

7

11,b10,b9

=0,

0, 0).
13-bit mode: The Standby command must be issued to the

ADC12048 in single write (bits b

11,b10,b9

=0,0,0).

RESET

The RESET command places the ADC12048 into a ready
state and forces the RDY signal low. The RESET command
can be used to interrupt the ADC12048 while it is performing

FIGURE 19. V

Operating Range

REF

01238737

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Analog Application Information (Continued)

ADC12048

*

Tantalum

**

Ceramic

FIGURE 20. Low Drift Extremely Stable Reference Circuit

Part Number Output Voltage Temperature

LM4041CI-Adj

LM4040AI-4.1

LM4050

LM4121

LM9140BYZ-4.1

Circuit of Figure 20 Adjustable

OUTPUT DIGITAL CODE VERSUS ANALOG INPUT VOLTAGE

The ADC12048’s fully differential 12-bit + sign ADC gener­ates a two’s complement output that is found by using the
equation shown below:

Round off the result to the nearest integer value between

−4096 and 4095.

INPUT CURRENT

At the start of the acquisition window (t
ing current (due to capacitive switching) flows through the
analog input pins (CH0–CH7, ADCIN+ and ADCIN−, and the
COM). The peak value of this input current will depend on
the amplitude and frequency of the input voltage applied, the
source impedance and the input switch ON resistance. With
the MUXOUT+ connected to the ADCIN+ and the
MUXOUT− connected to the ADCIN− the on resistance is
typically 2800Ω. Bypassing the MUX and using just the
ADCIN+ and ADCIN− inputs the on resistance is typically
2500Ω.

For low impedance voltage sources (
operation), the input charging current will decay to a value
that will not introduce any conversion errors before the end
of the default sample-and-hold (S/H) acquisition time (9
clock cycles). For higher source impedances (
12 MHz operation), the S/H acquisition time should be in-

AcqSYNOUT

<

1000Ω for 12 MHz

) a charg-

>

1000Ω for

01238736

Tolerance Coefficient

±

0.5%

±

0.1%

±

0.2%

±

0.1%

±

0.5%

creased to allow the charging current to settle within speci­fied limits. In asynchronous mode, the acquisition time may
be increased to 15, 47 or 79 clock cycles. If different acqui­sition times are needed, the synchronous mode can be used
to fully control the acquisition time.

INPUT BYPASS CAPACITANCE

External capacitors (0.01 µF–0.1 µF) can be connected
between the analog input pins (CH0–CH7) and the analog
ground to filter any noise caused by inconductive pickup
associated with long leads.

POWER SUPPLY CONSIDERATIONS

Decoupling and bypassing the power supply on a high reso­lution ADC is an important design task. Noise spikes on the

+ (analog supply) or VD+ (digital supply) can cause con-

V

A

version errors. The analog comparator used in the ADC will
respond to power supply noise and will make erroneous
conversion decisions. The ADC is especially sensitive to
power supply spikes that occur during the auto-zero or lin­earity calibration cycles.

The ADC12048 is designed to operate from a single +5V
power supply. The separate supply and ground pins for the
analog and digital portions of the circuit allow separate ex­ternal bypassing. To minimize power supply noise and ripple,
adequate bypass capacitors should be placed directly be­tween power supply pins and their associated grounds. Both
supply pins should be connected to the same supply source.
In systems with separate analog and digital supplies, the
ADC should be powered from the analog supply. At least a

±

100ppm/˚C

±

100ppm/˚C

±

50ppm/˚C

±

50ppm/˚C

±

25ppm/˚C

±

2ppm/˚C

www.national.com 28

Analog Application Information

(Continued)

10 µF tantalum electrolytic capacitor in parallel with a 0.1 µF
monolithic ceramic capacitor is recommended for bypassing
each power supply. The key consideration for these capaci­tors is to have low series resistance and inductance. The
capacitors should be placed as close as physically possible
to the supply and ground pins with the smaller capacitor
closer to the device. The capacitors also should have the
shortest possible leads in order to minimize series lead
inductance. Surface mount chip capacitors are optimal in
this respect and should be used when possible.

When the power supply regulator is not local on the board,
adequate bypassing (a high value electrolytic capacitor)
should be placed at the power entry point. The value of the
capacitor depends on the total supply current of the circuits
on the PC board. All supply currents should be supplied by
the capacitor instead of being drawn from the external sup­ply lines, while the external supply charges the capacitor at a
steady rate.

The ADC has two V
that each of these V
DGND with a 0.1 µF plus a 10 µF capacitor. The layout
diagram of Figure 21 shows the recommended placement
for the supply bypass capacitors.

PC BOARD LAYOUT AND GROUNDING CONSIDERATlONS

To get the best possible performance from the ADC12048,
the printed circuit boards should have separate analog and
digital ground planes. The reason for using two ground
planes is to prevent digital and analog ground currents from
sharing the same path until they reach a very low impedance
power supply point. This will prevent noisy digital switching
currents from being injected into the analog ground.

Figure 21 illustrates a favorable layout for ground planes,
power supply and reference input bypass capacitors. It

+ and DGND pins. It is recommended

D

+ pins be separately bypassed to

D

shows a layout using a 44-pin PLCC socket and
through-hole assembly. A similar approach should be used
for the PQFP package.

The analog ground plane should encompass the area under
the analog pins and any other analog components such as
the reference circuit, input amplifiers, signal conditioning
circuits, and analog signal traces.

The digital ground plane should encompass the area under
the digital circuits and the digital input/output pins of the
ADC12048. Having a continuous digital ground plane under
the data and clock traces is very important. This reduces the
overshoot/undershoot and high frequency ringing on these
lines that can be capacitively coupled to analog circuitry
sections through stray capacitances.

The AGND and DGND in the ADC12048 are not internally
connected together. They should be connected together on
the PC board right at the chip. This will provide the shortest
return path for the signals being exchanged between the
internal analog and digital sections of the ADC.

It is also a good design practice to have power plane layers
in the PC board. This will improve the supply bypassing (an
effective distributed capacitance between power and ground
plane layers) and voltage drops on the supply lines. How­ever, power planes are not as essential as ground planes are
for satisfactory performance. If power planes are used, they
should be separated into two planes and the area and
connections should follow the same guidelines as mentioned
for the ground planes. Each power plane should be laid out
over its associated ground planes, avoiding any overlap
between power and ground planes of different types. When
the power planes are not used, it is recommended to use
separate supply traces for the V

+ and VD+ pins from a low

A

impedance supply point (the regulator output or the power
entry point to the PC board). This will help ensure that the
noisy digital supply does not corrupt the analog supply.

ADC12048

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Analog Application Information (Continued)

ADC12048

FIGURE 21. Top View of Printed Circuit Board for a 44-Pin PLCC ADC12048

When measuring AC input signals, any crosstalk between
analog input/output lines and the reference lines (CH0–CH7,
MUXOUT

±

, ADC IN±,V

±

) should be minimized.

REF

Crosstalk is minimized by reducing any stray capacitance
between the lines. This can be done by increasing the clear­ance between traces, keeping the traces as short as pos­sible, shielding traces from each other by placing them on
different sides of the AGND plane, or running AGND traces
between them.

Figure 21 also shows the reference input bypass capacitors.
Here the reference inputs are considered to be differential.

www.national.com 30

01238738

The performance improves by having a 0.1 µF capacitor
between the V

REF

+ and V

−, and by bypassing in a man-

REF

ner similar to that described for the supply pins. When a
single ended reference is used, V
AGND and only two capacitors are used between V

− (0.1 µF + 10 µF). It is recommended to directly

V

REF

connect the AGND side of these capacitors to the V
instead of connecting V

− and the ground sides of the

REF

− is connected to

REF

REF

+ and

REF

capacitors separately to the ground planes. This provides a
significantly lower-impedance connection when using sur­face mount technology.

−

Physical Dimensions inches (millimeters) unless otherwise noted

ADC12048

44-Lead Molded Plastic Leaded Chip Carrier

Order Number ADC12048CIV

NS Package Number V44A

44-Lead (10mm x 10mm) Molded Plastic Quad Flat Package

Order Number ADC12048CIVF

NS Package Number VGZ44A

www.national.com31

Notes

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in

ADC12048 12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter

accordance with instructions for use provided in the

2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.

labeling, can be reasonably expected to result in a
significant injury to the user.

National Semiconductor
Corporation

Americas
Email: [e-mail]

www.national.com

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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