National Semiconductor ADC088S022 Technical data

September 2005

ADC088S022 8-Channel, 50 kSPS to 200 kSPS, 8-Bit A/D Converter

General Description

The ADC088S022 is a low-power, eight-channel CMOS 8-bit analog-to-digital converter specified for conversion throughput rates of 50 kSPS to 200 kSPS. The converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. It can be configured to accept up to eight input signals at inputs IN0 through IN7.

The output serial data is straight binary and is compatible with several standards, such as SPI

™

, and many common DSP serial interfaces.

IRE The ADC088S022 may be operated with independent ana-

log and digital supplies. The analog supply (V from +2.7V to +5.25V, and the digital supply (V from +2.7V to V +5V supply is 0.9 mW and 5.5 mW, respectively. The powerdown feature reduces the power consumption to 0.03 µW using a +3V supply and 0.15 µW using a +5V supply.

The ADC088S022 is packaged in a 16-lead TSSOP package. Operation over the extended industrial temperature range of −40˚C to +105˚C is guaranteed.

. Normal power consumption using a +3V or

™

, QSPI™, MICROW-

) can range

Connection Diagram

Features

n Eight input channels n Variable power management n Independent analog and digital supplies n SPI/QSPI/MICROWIRE/DSP compatible n Packaged in 16-lead TSSOP

Key Specifications

n Conversion Rate 50 kSPS to 200 kSPS n DNL (V n INL (V n Power Consumption

A=VD

— 3V Supply 0.9 mW (typ) — 5V Supply 5.5 mW (typ)

= 2.7V to 5.25V)

A=VD

= 2.7V to 5.25V)

0.2 LSB (max)

Applications

n Automotive Navigation n Portable Systems n Medical Instruments n Mobile Communications n Instrumentation and Control Systems

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Ordering Information

Order Code Temperature Range Description

ADC088S022CIMT −40˚C to +105˚C 16-Lead TSSOP Package

ADC088S022CIMTX −40˚C to +105˚C 16-Lead TSSOP Package, Tape & Reel

ADC088S022EVAL Evaluation Board

TRI-STATE®is a trademark of National Semiconductor Corporation. MICROWIRE QSPI

™

is a trademark of National Semiconductor Corporation.

™

and SPI™are trademarks of Motorola, Inc.

Block Diagram

ADC088S022

Pin Descriptions

Pin No. Symbol Description

ANALOG I/O

4 - 11 IN0 to IN7 Analog inputs. These signals can range from 0V to V

DIGITAL I/O

16 SCLK

15 DOUT

14 DIN

1CS

POWER SUPPLY

13 V

3 AGND The ground return for the analog supply and signals.

12 DGND The ground return for the digital supply and signals.

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REF

Digital clock input. The guaranteed performance range of frequencies for this input is 8 MHz to 16 MHz. This clock directly controls the conversion and readout processes.

Digital data output. The output samples are clocked out of this pin on the falling edges of the SCLK pin.

Digital data input. The ADC088S022’s Control Register is loaded through this pin on rising edges of the SCLK pin.

Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as CS is held low.

Positive analog supply pin. This voltage is also used as the reference voltage. This pin should be connected to a quiet

+2.7V to +5.25V source and bypassed to GND with 1 µF and

0.1 µF monolithic ceramic capacitors located within 1 cm of the power pin.

Positive digital supply pin. This pin should be connected to a

+2.7V to V monolithic ceramic capacitor located within 1 cm of the power

supply, and bypassed to GND with a 0.1 µF

pin.

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ADC088S022

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Analog Supply Voltage V

Digital Supply Voltage V

Voltage on Any Pin to GND −0.3V to V

Input Current at Any Pin (Note 3)

Package Input Current(Note 3)

Power Dissipation at T

= 25˚C See (Note 4)

ESD Susceptibility (Note 5)

Human Body Model

Machine Model

Soldering Temperature, Infrared,

10 seconds (Note 6) 260˚C

Junction Temperature +150˚C

−0.3V to 6.5V

−0.3V to VA+ 0.3V, max 6.5V

+0.3V

10 mA

20 mA

2500V

250V

Operating Ratings (Notes 1, 2)

Operating Temperature

Supply Voltage +2.7V to +5.25V

Supply Voltage +2.7V to V

Digital Input Voltage 0V to V

Analog Input Voltage 0V to V

Clock Frequency 0.8 MHz to 3.2 MHz

−40˚C ≤ T +105˚C

Package Thermal Resistance

Package θ

16-lead TSSOP on

4-layer, 2 oz. PCB

Soldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6)

96˚C / W

Storage Temperature −65˚C to +150˚C

ADC088S022 Converter Electrical Characteristics (Note 8)

The following specifications apply for VA=VD= +2.7V to +5.25V, AGND = DGND = 0V, f = 50 kSPS to 200 kSPS, and CL= 50pF, unless otherwise noted. Boldface limits apply for TA=T

= 25˚C.

Symbol Parameter Conditions Typical

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 8 Bits

INL

Integral Non-Linearity (End Point Method)

DNL Differential Non-Linearity

OFF

Offset Error +0.6

OEM Offset Error Match

FSE Full Scale Error +0.5

FSEM Full Scale Error Match

DYNAMIC CONVERTER CHARACTERISTICS

FPBW Full Power Bandwidth (−3dB) 8 MHz

SINAD Signal-to-Noise Plus Distortion Ratio f

SNR Signal-to-Noise Ratio f

THD Total Harmonic Distortion f

SFDR Spurious-Free Dynamic Range f

ENOB Effective Number of Bits f

ISO Channel-to-Channel Isolation f

Intermodulation Distortion, Second

IMD

Order Terms

Intermodulation Distortion, Third Order Terms

= 39.9 kHz, −0.02 dBFS 49.5 49.2 dB (min)

= 39.9 kHz, −0.02 dBFS −70.1 −56.8 dB (max)

= 39.9 kHz, −0.02 dBFS 67.7 64.2 dB (min)

= 39.9 kHz 7.93 7.88 Bits (min)

= 20 kHz 65.3 dB

= 19.5 kHz, fb= 20.5 kHz −75.0 dB

= 19.5 kHz, fb= 20.5 kHz −71.9 dB

ANALOG INPUT CHARACTERISTICS

DCL

INA

Input Range 0 to V

DC Leakage Current

Input Capacitance

Track Mode 33 pF

Hold Mode 3 pF

= 0.8 MHz to 3.2 MHz, f

SCLK

MIN

to T

Limits

(Note 7)

0.04

0.02

0.2 LSB (max)

0.7 LSB (max)

0.2 LSB (max)

0.6 LSB (max)

0.2 LSB (max)

SAMPLE

: all other limits

MAX

Units

1 µA (max)

≤

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ADC088S022 Converter Electrical Characteristics (Note 8) (Continued)

The following specifications apply for VA=VD= +2.7V to +5.25V, AGND = DGND = 0V, f = 50 kSPS to 200 kSPS, and CL= 50pF, unless otherwise noted. Boldface limits apply for TA=T

= 25˚C.

ADC088S022

Symbol Parameter Conditions Typical

DIGITAL INPUT CHARACTERISTICS

IND

Input High Voltage

Input Low Voltage 0.8 V (max)

Input Current VIN=0VorV

Digital Input Capacitance 2 4 pF (max)

DIGITAL OUTPUT CHARACTERISTICS

OZH,IOZL

OUT

Output High Voltage I

Output Low Voltage I

Hi-Impedance Output Leakage Current

Hi-Impedance Output Capacitance (Note 8)

SOURCE

SINK

Output Coding Straight (Natural) Binary

POWER SUPPLY CHARACTERISTICS (C

A,VD

Analog and Digital Supply Voltages VA≥ V

=10pF)

VA=VD= +2.7V to +3.6V, f

SAMPLE

V f

SAMPLE

VA=VD= +2.7V to +3.6V, f

SCLK

V f

SCLK

A+ID

Total Supply Current Normal Mode ( CS low)

Total Supply Current Shutdown Mode (CS high)

VA=VD= +3.0V Power Consumption Normal Mode ( CS low)

Power Consumption Shutdown Mode (CS high)

SAMPLE

VA=VD= +3.0V

SCLK

AC ELECTRICAL CHARACTERISTICS

MIN Minimum Clock Frequency 0.8 MHz (min)

SCLK

CONVERT

Maximum Clock Frequency 16 3.2 MHz (max)

Sample Rate Continuous Mode

Conversion (Hold) Time 13 SCLK cycles

DC SCLK Duty Cycle

ACQ

Acquisition (Track) Time 3 SCLK cycles

Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles

Aperture Delay 4 ns

= +2.7V to +3.6V 2.1 V (min)

A=VD

= +4.75V to +5.25V 2.4 V (min)

A=VD

= 200 µA, VD− 0.5 V (min)

= 200 µA to 1.0 mA, 0.4 V (max)

= 1 MSPS, fIN=40kHz

= +4.75V to +5.25V,

A=VD

= 1 MSPS, fIN=40kHz

= 0 kSPS

= +4.75V to +5.25V,

A=VD

= 0 kSPS

= 1 MSPS, fIN=40kHz

= +5.0V

A=VD

= 1 MSPS, fIN=40kHz

= 0 kSPS

= +5.0V

A=VD

= 0 kSPS

SCLK

1000 200 kSPS (max)

= 0.8 MHz to 3.2 MHz, f

to T

MIN

MAX

Limits

(Note 7)

0.01

1 µA (max)

SAMPLE

: all other limits

Units

2 4 pF (max)

2.7 V (min)

5.25 V (max)

0.3 0.74 mA (max)

1.1 1.55 mA (max)

10 nA

30 nA

0.9 2.2 mW (max)

5.5 7.8 mW (max)

0.03 µW

0.15 µW

50 kSPS (min)

30 40 % (min)

70 60 % (max)

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ADC088S022 Timing Specifications

The following specifications apply for VA=VD= +2.7V to 5.25V, AGND = DGND = 0V, f 50 kSPS to 200 kSPS, and C

= 50pF. Boldface limits apply for TA=T

MIN

to T

MAX

Symbol Parameter Conditions Typical

CSH

CSS

DACC

DHLD

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (that is, V

The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.

Note 4: The absolute maximum junction temperature (T junction-to-ambient thermal resistance (θ TSSOP, θ of this device under normal operation is a maximum of 12 mW. The values for maximum power dissipation listed above will be reached only when theADC088S022 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO ohms

Note 6: Reflow temperature profiles are different for lead-free packages.

Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 8: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Note 9: Clock may be in any state (high or low) when CS goes high. Setup and hold restrictions apply only to CS going low.

CS Hold Time after SCLK Rising Edge

CS Setup Time prior to SCLK Rising Edge

CS Falling Edge to DOUT enabled 5 30 ns (max)

DOUT Access Time after SCLK Falling Edge

DOUT Hold Time after SCLK Falling Edge

DIN Setup Time prior to SCLK

Rising Edge

DIN Hold Time after SCLK Rising

Edge

SCLK High Time

SCLK Low Time

CS Rising Edge to DOUT

DIS

High-Impedance

), and the ambient temperature (TA), and can be calculated using the formula PDMAX=(TJmax − TA)/θJA. In the 16-pin

is 96˚C/W, so PDMAX = 1,200 mW at 25˚C and 625 mW at the maximum operating ambient temperature of 105˚C. Note that the power consumption

(Note 9) 0 10 ns (min)

(Note 9) 5 10 ns (min)

DOUT falling 2.4 20 ns (max)

DOUT rising 0.9 20 ns (max)

AGND or V

max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the

VAor VD), the current at that pin should be limited to 10 mA.

= 0.8 MHz to 3.2 MHz, f

SCLK

: all other limits TA= 25˚C.

Limits

(Note 7)

17 27 ns (max)

4 ns (typ)

3 10 ns (min)

0.4 x t

SCLK

0.4 x t

SCLK

SAMPLE

Units

ns (min)

ADC088S022

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Timing Diagrams

ADC088S022

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FIGURE 1. ADC088S022 Operational Timing Diagram

FIGURE 2. ADC088S022 Serial Timing Diagram

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FIGURE 3. SCLK and CS Timing Parameters

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