September 2005
ADC088S022
8-Channel, 50 kSPS to 200 kSPS, 8-Bit A/D Converter
ADC088S022 8-Channel, 50 kSPS to 200 kSPS, 8-Bit A/D Converter
General Description
The ADC088S022 is a low-power, eight-channel CMOS 8-bit
analog-to-digital converter specified for conversion throughput rates of 50 kSPS to 200 kSPS. The converter is based on
a successive-approximation register architecture with an internal track-and-hold circuit. It can be configured to accept
up to eight input signals at inputs IN0 through IN7.
The output serial data is straight binary and is compatible
with several standards, such as SPI
™
, and many common DSP serial interfaces.
IRE
The ADC088S022 may be operated with independent ana-
log and digital supplies. The analog supply (V
from +2.7V to +5.25V, and the digital supply (V
from +2.7V to V
+5V supply is 0.9 mW and 5.5 mW, respectively. The powerdown feature reduces the power consumption to 0.03 µW
using a +3V supply and 0.15 µW using a +5V supply.
The ADC088S022 is packaged in a 16-lead TSSOP package. Operation over the extended industrial temperature
range of −40˚C to +105˚C is guaranteed.
. Normal power consumption using a +3V or
A
™
, QSPI™, MICROW-
) can range
A
) can range
D
Connection Diagram
Features
n Eight input channels
n Variable power management
n Independent analog and digital supplies
n SPI/QSPI/MICROWIRE/DSP compatible
n Packaged in 16-lead TSSOP
Key Specifications
n Conversion Rate 50 kSPS to 200 kSPS
n DNL (V
n INL (V
n Power Consumption
A=VD
— 3V Supply 0.9 mW (typ)
— 5V Supply 5.5 mW (typ)
= 2.7V to 5.25V)
A=VD
= 2.7V to 5.25V)
±
0.2 LSB (max)
±
0.2 LSB (max)
Applications
n Automotive Navigation
n Portable Systems
n Medical Instruments
n Mobile Communications
n Instrumentation and Control Systems
20166705
Ordering Information
Order Code Temperature Range Description
ADC088S022CIMT −40˚C to +105˚C 16-Lead TSSOP Package
ADC088S022CIMTX −40˚C to +105˚C 16-Lead TSSOP Package, Tape & Reel
ADC088S022EVAL Evaluation Board
TRI-STATE®is a trademark of National Semiconductor Corporation.
MICROWIRE
QSPI
© 2005 National Semiconductor Corporation DS201667 www.national.com
™
is a trademark of National Semiconductor Corporation.
™
and SPI™are trademarks of Motorola, Inc.
Block Diagram
ADC088S022
Pin Descriptions
Pin No. Symbol Description
ANALOG I/O
4 - 11 IN0 to IN7 Analog inputs. These signals can range from 0V to V
DIGITAL I/O
16 SCLK
15 DOUT
14 DIN
1CS
POWER SUPPLY
2V
13 V
3 AGND The ground return for the analog supply and signals.
12 DGND The ground return for the digital supply and signals.
20166707
.
REF
Digital clock input. The guaranteed performance range of
frequencies for this input is 8 MHz to 16 MHz. This clock
directly controls the conversion and readout processes.
Digital data output. The output samples are clocked out of this
pin on the falling edges of the SCLK pin.
Digital data input. The ADC088S022’s Control Register is
loaded through this pin on rising edges of the SCLK pin.
Chip select. On the falling edge of CS, a conversion process
begins. Conversions continue as long as CS is held low.
Positive analog supply pin. This voltage is also used as the
reference voltage. This pin should be connected to a quiet
A
+2.7V to +5.25V source and bypassed to GND with 1 µF and
0.1 µF monolithic ceramic capacitors located within 1 cm of
the power pin.
Positive digital supply pin. This pin should be connected to a
D
+2.7V to V
monolithic ceramic capacitor located within 1 cm of the power
supply, and bypassed to GND with a 0.1 µF
A
pin.
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ADC088S022
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Analog Supply Voltage V
Digital Supply Voltage V
A
D
Voltage on Any Pin to GND −0.3V to V
Input Current at Any Pin (Note 3)
Package Input Current(Note 3)
Power Dissipation at T
= 25˚C See (Note 4)
A
ESD Susceptibility (Note 5)
Human Body Model
Machine Model
Soldering Temperature, Infrared,
10 seconds (Note 6) 260˚C
Junction Temperature +150˚C
−0.3V to 6.5V
−0.3V to VA+ 0.3V,
max 6.5V
+0.3V
A
±
10 mA
±
20 mA
2500V
250V
Operating Ratings (Notes 1, 2)
Operating Temperature
Supply Voltage +2.7V to +5.25V
V
A
V
Supply Voltage +2.7V to V
D
Digital Input Voltage 0V to V
Analog Input Voltage 0V to V
Clock Frequency 0.8 MHz to 3.2 MHz
−40˚C ≤ T
+105˚C
Package Thermal Resistance
Package θ
16-lead TSSOP on
4-layer, 2 oz. PCB
Soldering process must comply with National Semiconductor’s Reflow Temperature Profile specifications. Refer to
www.national.com/packaging. (Note 6)
JA
96˚C / W
Storage Temperature −65˚C to +150˚C
ADC088S022 Converter Electrical Characteristics (Note 8)
The following specifications apply for VA=VD= +2.7V to +5.25V, AGND = DGND = 0V, f
= 50 kSPS to 200 kSPS, and CL= 50pF, unless otherwise noted. Boldface limits apply for TA=T
= 25˚C.
T
A
Symbol Parameter Conditions Typical
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 8 Bits
INL
Integral Non-Linearity (End Point
Method)
DNL Differential Non-Linearity
V
OFF
Offset Error +0.6
OEM Offset Error Match
FSE Full Scale Error +0.5
FSEM Full Scale Error Match
DYNAMIC CONVERTER CHARACTERISTICS
FPBW Full Power Bandwidth (−3dB) 8 MHz
SINAD Signal-to-Noise Plus Distortion Ratio f
SNR Signal-to-Noise Ratio f
THD Total Harmonic Distortion f
SFDR Spurious-Free Dynamic Range f
ENOB Effective Number of Bits f
ISO Channel-to-Channel Isolation f
Intermodulation Distortion, Second
IMD
Order Terms
Intermodulation Distortion, Third
Order Terms
= 39.9 kHz, −0.02 dBFS 49.5 49.2 dB (min)
IN
= 39.9 kHz, −0.02 dBFS 49.5 49.2 dB (min)
IN
= 39.9 kHz, −0.02 dBFS −70.1 −56.8 dB (max)
IN
= 39.9 kHz, −0.02 dBFS 67.7 64.2 dB (min)
IN
= 39.9 kHz 7.93 7.88 Bits (min)
IN
= 20 kHz 65.3 dB
IN
f
= 19.5 kHz, fb= 20.5 kHz −75.0 dB
a
= 19.5 kHz, fb= 20.5 kHz −71.9 dB
f
a
ANALOG INPUT CHARACTERISTICS
V
I
C
IN
DCL
INA
Input Range 0 to V
DC Leakage Current
Input Capacitance
Track Mode 33 pF
Hold Mode 3 pF
= 0.8 MHz to 3.2 MHz, f
SCLK
MIN
to T
Limits
(Note 7)
±
±
±
±
0.04
0.04
0.02
0.02
±
0.2 LSB (max)
±
0.2 LSB (max)
±
0.7 LSB (max)
±
0.2 LSB (max)
±
0.6 LSB (max)
±
0.2 LSB (max)
A
±
SAMPLE
: all other limits
MAX
Units
V
1 µA (max)
≤
A
A
A
A
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ADC088S022 Converter Electrical Characteristics (Note 8) (Continued)
The following specifications apply for VA=VD= +2.7V to +5.25V, AGND = DGND = 0V, f
= 50 kSPS to 200 kSPS, and CL= 50pF, unless otherwise noted. Boldface limits apply for TA=T
= 25˚C.
T
A
ADC088S022
Symbol Parameter Conditions Typical
DIGITAL INPUT CHARACTERISTICS
V
IH
V
IL
I
IN
C
IND
Input High Voltage
Input Low Voltage 0.8 V (max)
Input Current VIN=0VorV
Digital Input Capacitance 2 4 pF (max)
V
V
DIGITAL OUTPUT CHARACTERISTICS
V
OH
V
OL
I
OZH,IOZL
C
OUT
Output High Voltage I
Output Low Voltage I
Hi-Impedance Output Leakage
Current
Hi-Impedance Output Capacitance
(Note 8)
SOURCE
SINK
Output Coding Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS (C
V
A,VD
Analog and Digital Supply Voltages VA≥ V
=10pF)
L
VA=VD= +2.7V to +3.6V,
f
SAMPLE
V
f
SAMPLE
VA=VD= +2.7V to +3.6V,
f
SCLK
V
f
SCLK
I
A+ID
Total Supply Current
Normal Mode ( CS low)
Total Supply Current
Shutdown Mode (CS high)
VA=VD= +3.0V
Power Consumption
Normal Mode ( CS low)
P
C
Power Consumption
Shutdown Mode (CS high)
f
SAMPLE
V
f
SAMPLE
VA=VD= +3.0V
f
SCLK
V
f
SCLK
AC ELECTRICAL CHARACTERISTICS
f
MIN Minimum Clock Frequency 0.8 MHz (min)
SCLK
f
SCLK
f
S
t
CONVERT
Maximum Clock Frequency 16 3.2 MHz (max)
Sample Rate
Continuous Mode
Conversion (Hold) Time 13 SCLK cycles
DC SCLK Duty Cycle
t
ACQ
Acquisition (Track) Time 3 SCLK cycles
Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles
t
AD
Aperture Delay 4 ns
= +2.7V to +3.6V 2.1 V (min)
A=VD
= +4.75V to +5.25V 2.4 V (min)
A=VD
D
= 200 µA, VD− 0.5 V (min)
= 200 µA to 1.0 mA, 0.4 V (max)
D
= 1 MSPS, fIN=40kHz
= +4.75V to +5.25V,
A=VD
= 1 MSPS, fIN=40kHz
= 0 kSPS
= +4.75V to +5.25V,
A=VD
= 0 kSPS
= 1 MSPS, fIN=40kHz
= +5.0V
A=VD
= 1 MSPS, fIN=40kHz
= 0 kSPS
= +5.0V
A=VD
= 0 kSPS
SCLK
±
1000 200 kSPS (max)
= 0.8 MHz to 3.2 MHz, f
to T
MIN
MAX
Limits
(Note 7)
0.01
±
1 µA (max)
±
1 µA (max)
SAMPLE
: all other limits
Units
2 4 pF (max)
2.7 V (min)
5.25 V (max)
0.3 0.74 mA (max)
1.1 1.55 mA (max)
10 nA
30 nA
0.9 2.2 mW (max)
5.5 7.8 mW (max)
0.03 µW
0.15 µW
50 kSPS (min)
30 40 % (min)
70 60 % (max)
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ADC088S022 Timing Specifications
The following specifications apply for VA=VD= +2.7V to 5.25V, AGND = DGND = 0V, f
50 kSPS to 200 kSPS, and C
= 50pF. Boldface limits apply for TA=T
L
MIN
to T
MAX
Symbol Parameter Conditions Typical
t
CSH
t
CSS
t
t
DACC
t
DHLD
t
t
t
t
t
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
TSSOP, θ
of this device under normal operation is a maximum of 12 mW. The values for maximum power dissipation listed above will be reached only when theADC088S022
is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).
Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO ohms
Note 6: Reflow temperature profiles are different for lead-free packages.
Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 9: Clock may be in any state (high or low) when CS goes high. Setup and hold restrictions apply only to CS going low.
CS Hold Time after SCLK Rising
Edge
CS Setup Time prior to SCLK Rising
Edge
CS Falling Edge to DOUT enabled 5 30 ns (max)
EN
DOUT Access Time after SCLK
Falling Edge
DOUT Hold Time after SCLK Falling
Edge
DIN Setup Time prior to SCLK
DS
Rising Edge
DIN Hold Time after SCLK Rising
DH
Edge
SCLK High Time
CH
SCLK Low Time
CL
CS Rising Edge to DOUT
DIS
High-Impedance
), and the ambient temperature (TA), and can be calculated using the formula PDMAX=(TJmax − TA)/θJA. In the 16-pin
is 96˚C/W, so PDMAX = 1,200 mW at 25˚C and 625 mW at the maximum operating ambient temperature of 105˚C. Note that the power consumption
JA
JA
(Note 9) 0 10 ns (min)
(Note 9) 5 10 ns (min)
DOUT falling 2.4 20 ns (max)
DOUT rising 0.9 20 ns (max)
<
AGND or V
IN
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
J
>
VAor VD), the current at that pin should be limited to 10 mA.
IN
= 0.8 MHz to 3.2 MHz, f
SCLK
: all other limits TA= 25˚C.
Limits
(Note 7)
17 27 ns (max)
4 ns (typ)
3 10 ns (min)
3 10 ns (min)
0.4 x
t
SCLK
0.4 x
t
SCLK
SAMPLE
Units
ns (min)
ns (min)
ADC088S022
=
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Timing Diagrams
ADC088S022
20166751
FIGURE 1. ADC088S022 Operational Timing Diagram
FIGURE 2. ADC088S022 Serial Timing Diagram
20166750
FIGURE 3. SCLK and CS Timing Parameters
20166706
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Specification Definitions
ACQUISITION TIME is the time required for the ADC to
acquire the input voltage. During this time, the hold capacitor
is charged by the input voltage.
APERTURE DELAY is the time between the fourth falling
edge of SCLK and the time when the input signal is internally
acquired or held for conversion.
CONVERSION TIME is the time required, after the input
voltage is acquired, for the ADC to convert the input voltage
to a digital word.
CHANNEL-TO-CHANNEL ISOLATION is resistance to coupling of energy from one channel into another channel.
CROSSTALK is the coupling of energy from one channel
into another channel. This is similar to Channel-to-Channel
Isolation, except for the sign of the data.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital
waveform is high to the total time of one period. The specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion or SINAD. ENOB is defined as (SINAD - 1.76) /
6.02 and says that the converter is equivalent to a perfect
ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
GAIN ERROR is the deviation of the last code transition
(111...110) to (111...111) from the ideal (V
after adjusting for offset error.
INTEGRAL NON-LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from
negative full scale (
through positive full scale (
1
⁄2LSB below the first code transition)
1
⁄2LSB above the last code
transition). The deviation of any given code from this straight
line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to an individual ADC input at the
same time. It is defined as the ratio of the power in either the
- 1.5 LSB),
REF
second or the third order intermodulation products to the
sum of the power in both of the original frequencies. Second
±
order products are f
wave input frequencies. Third order products are (2f
±
and (f
2fb). IMD is usually expressed in dB.
a
fb, where faand fbare the two sine
a
±
fb)
a
MISSING CODES are those output codes that will never
appear at the ADC outputs. The ADC088S022 is guaranteed
not to have any missing codes.
OFFSET ERROR is the deviation of the first code transition
(000...000) to (000...001) from the ideal (i.e. GND + 0.5
LSB).
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)
Is the ratio, expressed in dB, of the rms value of the input
signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics
but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input
signal and the peak spurious signal where a spurious signal
is any signal present in the output spectrum that is not
present at the input, including harmonics but excluding d.c.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first five harmonic
components at the output to the rms level of the input signal
frequency as seen at the output. THD is calculated as
where Af1is the RMS power of the input frequency at the
output and A
through Af6are the RMS power in the first 5
f2
harmonic frequencies.
THROUGHPUT TIME is the minimum time required between
the start of two successive conversions. It is the acquisition
time plus the conversion time.
ADC088S022
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Typical Performance Characteristics V
3.2 MHz, f
ADC088S022
= 39.9 kHz unless otherwise stated.
IN
DNL DNL
INL INL
20166740 20166741
= +5.0V, TA= +25˚C, f
A=VD
SAMPLE
= 200 kSPS, f
SCLK
=
20166742 20166743
DNL vs. Supply INL vs. Supply
20166721 20166720
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ADC088S022
Typical Performance Characteristics V
3.2 MHz, f
= 39.9 kHz unless otherwise stated. (Continued)
IN
SNR vs. Supply THD vs. Supply
20166722 20166732
ENOB vs. Supply DNL vs. VDwith VA= 5.0 V
= +5.0V, TA= +25˚C, f
A=VD
SAMPLE
= 200 kSPS, f
SCLK
=
20166733 20166730
INL vs. VDwith VA= 5.0 V DNL vs. SCLK Duty Cycle
20166731 20166755
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Typical Performance Characteristics V
3.2 MHz, f
= 39.9 kHz unless otherwise stated. (Continued)
IN
= +5.0V, TA= +25˚C, f
A=VD
SAMPLE
= 200 kSPS, f
SCLK
=
ADC088S022
INL vs. SCLK Duty Cycle SNR vs. SCLK Duty Cycle
20166758 20166761
THD vs. SCLK Duty Cycle ENOB vs. SCLK Duty Cycle
20166764 20166752
DNL vs. SCLK INL vs. SCLK
20166756 20166759
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ADC088S022
Typical Performance Characteristics V
3.2 MHz, f
= 39.9 kHz unless otherwise stated. (Continued)
IN
SNR vs. SCLK THD vs. SCLK
20166762 20166765
ENOB vs. SCLK DNL vs. Temperature
= +5.0V, TA= +25˚C, f
A=VD
SAMPLE
= 200 kSPS, f
SCLK
=
20166753 20166757
INL vs. Temperature SNR vs. Temperature
20166760 20166763
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Typical Performance Characteristics V
3.2 MHz, f
= 39.9 kHz unless otherwise stated. (Continued)
IN
= +5.0V, TA= +25˚C, f
A=VD
SAMPLE
= 200 kSPS, f
SCLK
=
ADC088S022
THD vs. Temperature ENOB vs. Temperature
20166766 20166754
SNR vs. Input Frequency THD vs. Input Frequency
20166723 20166724
ENOB vs. Input Frequency Power Consumption vs. SCLK
20166725 20166744
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1.0 Functional Description
The ADC088S022 is a successive-approximation analog-todigital converter designed around a charge-redistribution
digital-to-analog converter.
1.1 ADC088S022 OPERATION
Simplified schematics of the ADC088S022 in both track and
hold operation are shown in Figure 4 and Figure 5 respectively. In Figure 4, the ADC088S022 is in track mode: switch
SW1 connects the sampling capacitor to one of eight analog
input channels through the multiplexer, and SW2 balances
the comparator inputs. The ADC088S022 is in this state for
the first three SCLK cycles after CS is brought low.
ADC088S022
Figure 5 shows the ADC088S022 in hold mode: switch SW1
connects the sampling capacitor to ground, maintaining the
sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-redistribution
DAC to add or subtract fixed amounts of charge to or from
the sampling capacitor until the comparator is balanced.
When the comparator is balanced, the digital word supplied
to the DAC is the digital representation of the analog input
voltage. The ADC088S022 is in this state for the last thirteen
SCLK cycles after CS is brought low.
FIGURE 4. ADC088S022 in Track Mode
FIGURE 5. ADC088S022 in Hold Mode
1.2 SERIAL INTERFACE
An operational timing diagram and a serial interface timing
diagram for the ADC088S022 are shown in The Timing
Diagrams section. CS, chip select, initiates conversions and
frames the serial data transfers. SCLK (serial clock) controls
both the conversion process and the timing of serial data.
DOUT is the serial data output pin, where a conversion result
is sent as a serial data stream, MSB first. Data to be written
to the ADC088S022’s Control Register is placed on DIN, the
serial data input pin. New data is written to DIN with each
conversion.
A serial frame is initiated on the falling edge of CS and ends
on the rising edge of CS. Each frame must contain an integer
multiple of 16 rising SCLK edges. The ADC’s DOUT pin is in
a high impedance state when CS is high and is active when
CS is low. Thus, CS acts as an output enable. Similarly,
SCLK is internally gated off when CS is brought high.
20166709
20166710
During the first 3 cycles of SCLK, the ADC is in the track
mode, acquiring the input voltage. For the next 13 SCLK
cycles the conversion is accomplished and the data is
clocked out. SCLK falling edges 1 through 4 clock out leading zeros, falling edges 5 through 12 clock out the conversion result, MSB first, and falling edges 13 through 16 clock
out trailing zeros. If there is more than one conversion in a
frame (continuous conversion mode), the ADC will re-enter
the track mode on the falling edge of SCLK after the N*16th
rising edge of SCLK and re-enter the hold/convert mode on
the N*16+4th falling edge of SCLK. "N" is an integer value.
The ADC088S022 enters track mode under three different
conditions. In Figure 1, CS goes low with SCLK high and the
ADC enters track mode on the first falling edge of SCLK. In
the second condition, CS goes low with SCLK low. Under
this condition, the ADC automatically enters track mode and
the falling edge of CS is seen as the first falling edge of
SCLK. In the third condition, CS and SCLK go low simulta-
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1.0 Functional Description (Continued)
neously and the ADC enters track mode. While there is no
timing restriction with respect to the falling edges of CS and
SCLK, see Figure 3 for setup and hold time requirements for
ADC088S022
the falling edge of CS with respect to the rising edge of
SCLK.
During each conversion, data is clocked into a control register through the DIN pin on the first 8 rising edges of SCLK
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC
TABLE 2. Control Register Bit Descriptions
Bit #: Symbol: Description
7, 6, 2, 1, 0 DONTC Don’t care. The values of these bits do not affect the device.
5 ADD2 These three bits determine which input channel will be sampled and
4 ADD1
3 ADD0
converted at the next conversion cycle. The mapping between codes and
channels is shown in Table 3.
after the fall of CS. The control register is loaded with data
indicating the input channel to be converted on the subsequent conversion (see Tables 1, 2, 3).
The user does not need to incorporate a power-up delay or
dummy conversions as the ADC088S022 is able to acquire
the input signal to full resolution in the first conversion immediately following power-up. The first conversion result
after power-up will be that of IN0.
TABLE 1. Control Register Bits
TABLE 3. Input Channel Selection
ADD2 ADD1 ADD0 Input Channel
0 0 0 IN0 (Default)
0 0 1 IN1
0 1 0 IN2
0 1 1 IN3
1 0 0 IN4
1 0 1 IN5
1 1 0 IN6
1 1 1 IN7
1.3 ADC088S022 TRANSFER FUNCTION
The output format of the ADC088S022 is straight binary.
Code transitions occur midway between successive integer
LSB values. The LSB width for the ADC088S022 is V
/ 256.
A
The ideal transfer characteristic is shown in Figure 6. The
transition from an output code of 0000 0000 to a code of
0000 0001 is at 1/2 LSB, or a voltage of V
/ 512. Other code
A
transitions occur at steps of one LSB.
1.4 ANALOG INPUTS
An equivalent circuit for one of the ADC088S022’s input
channels is shown in Figure 7. Diodes D1 and D2 provide
ESD protection for the analog inputs. The operating range
for the analog inputs is 0V to V
. Going beyond this range
A
will cause the ESD diodes to conduct and result in erratic
operation.
The capacitor C1 in Figure 7 has a typical value of 3 pF and
is mainly the package pin capacitance. Resistor R1 is the on
resistance of the multiplexer and track / hold switch and is
typically 500 ohms. Capacitor C2 is the ADC088S022 sampling capacitor, and is typically 30 pF. The ADC088S022 will
deliver best performance when driven by a low-impedance
source (less than 100 ohms). This is especially important
when using the ADC088S022 to sample dynamic signals.
Also important when sampling dynamic signals is a bandpass or low-pass filter which reduces harmonics and noise in
the input. These filters are often referred to as anti-aliasing
filters.
20166711
FIGURE 6. Ideal Transfer Characteristic
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20166714
FIGURE 7. Equivalent Input Circuit
1.5 DIGITAL INPUTS AND OUTPUTS
The ADC088S022’s digital inputs (SCLK, CS, and DIN) have
an operating range of 0V to VA. They are not prone to
latch-up and may be asserted before the digital supply (V
without any risk. The digital output (DOUT) operating range
is controlled by V
. The output high voltage is VD- 0.5V
D
(min) while the output low voltage is 0.4V (max).
)
D
2.0 Applications Information
2.1 TYPICAL APPLICATION CIRCUIT
A typical application is shown in Figure 8. The split analog
and digital supply pins are both powered in this example by
the National LP2950 low-dropout voltage regulator. The analog supply is bypassed with a capacitor network located
close to the ADC088S022. The digital supply is separated
from the analog supply by an isolation resistor and bypassed
with additional capacitors. The ADC088S022 uses the analog supply (V
) as its reference voltage, so it is very impor-
A
tant that V
be kept as clean as possible. Due to the low
A
power requirements of the ADC088S022, it is also possible
to use a precision reference as a power supply.
To minimize the error caused by the changing input capacitance of the ADC088S022, a capacitor is connected from
each input pin to ground. The capacitor, which is much larger
than the input capacitance of the ADC088S022 when in track
mode, provides the current to quickly charge the sampling
capacitor of the ADC088S022. An isolation resistor is added
to isolate the load capacitance from the input source.
ADC088S022
FIGURE 8. Typical Application Circuit
2.2 POWER SUPPLY CONSIDERATIONS
There are three major power supply concerns with this product: power supply sequencing, power management, and the
effect of digital supply noise on the analog supply.
2.2.1 Power Supply Sequence
The ADC088S022 is a dual-supply device. The two supply
pins share ESD resources, so care must be exercised to
ensure that the power is applied in the correct sequence. To
avoid turning on the ESD diodes, the digital supply (V
cannot exceed the analog supply (V
not even on a transient basis. Therefore, V
before or concurrently with V
) by more than 300 mV,
A
.
D
must ramp up
A
2.2.2 Power Management
The ADC088S022 is fully powered-up whenever CS is low
and fully powered-down whenever CS is high, with one
exception. If operating in continuous conversion mode, the
ADC088S022 automatically enters power-down mode between SCLK’s 16th falling edge of a conversion and the
SCLK’s 1st falling edge of the subsequent conversion (see
Figure 1).
In continuous conversion mode, the ADC088S022 can perform multiple conversions back to back. Each conversion
requires 16 SCLK cycles and the ADC088S022 will perform
conversions continuously as long as CS is held low. Continuous mode offers maximum throughput.
In burst mode, the user may trade off throughput for power
consumption by performing fewer conversions per unit time.
This means spending more time in power-down mode and
less time in normal mode. By utilizing this technique, the
user can achieve very low sample rates while still utilizing an
SCLK frequency within the electrical specifications. The
20166713
Power Consumption vs. SCLK curve in the Typical Performance Curves section shows the typical power consumption
of the ADC088S022. To calculate the power consumption
), simply multiply the fraction of time spent in the normal
(P
C
mode (t
add the fraction of time spent in shutdown mode (t
plied by the shutdown mode power consumption (P
) by the normal mode power consumption (PN), and
N
) multi-
S
S
)as
shown in Figure 9.
)
D
20166715
FIGURE 9. Power Consumption Equation
2.2.3 Power Supply Noise Considerations
The charging of any output load capacitance requires current from the digital supply, V
. The current pulses required
D
from the supply to charge the output capacitance will cause
voltage variations on the digital supply. If these variations are
large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, if the analog and digital
supplies are tied directly together, the noise on the digital
supply will be coupled directly into the analog supply, causing greater performance degradation than would noise on
the digital supply alone. Similarly, discharging the output
capacitance when the digital output goes from a logic high to
a logic low will dump current into the die substrate, which is
resistive. Load discharge currents will cause "ground
bounce" noise in the substrate that will degrade noise performance if that current is large enough. The larger the
www.national.com15
2.0 Applications Information
(Continued)
output capacitance, the more current flows through the die
substrate and the greater the noise coupled into the analog
ADC088S022
channel.
The first solution to keeping digital noise out of the analog
supply is to decouple the analog and digital supplies from
each other or use separate supplies for them. To keep noise
out of the digital supply, keep the output load capacitance as
small as practical. If the load capacitance is greater than 50
pF, use a 100 Ω series resistor at the ADC output, located as
close to the ADC output pin as practical. This will limit the
charge and discharge current of the output capacitance and
improve noise performance. Since the series resistor and
the load capacitance form a low frequency pole, verify signal
integrity once the series resistor has been added.
2.3 LAYOUT AND GROUNDING
Capacitive coupling between the noisy digital circuitry and
the sensitive analog circuitry can lead to poor performance.
The solution is to keep the analog circuitry separated from
the digital circuitry and the clock line as short as possible.
Digital circuits create substantial supply and ground current
transients. The logic noise generated could have significant
impact upon system noise performance. To avoid perfor-
mance degradation of the ADC088S022 due to supply noise,
do not use the same supply for the ADC088S022 that is used
for digital logic.
Generally, analog and digital lines should cross each other at
90˚ to avoid crosstalk. However, to maximize accuracy in
high resolution systems, avoid crossing analog and digital
lines altogether. It is important to keep clock lines as short as
possible and isolated from ALL other lines, including other
digital lines. In addition, the clock line should also be treated
as a transmission line and be properly terminated.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any
external component (e.g., a filter capacitor) connected between the converter’s input pins and ground or to the reference input pin and ground should be connected to a very
clean point in the ground plane.
We recommend the use of a single, uniform ground plane
and the use of split power planes. The power planes should
be located within the same board layer. All analog circuitry
(input amplifiers, filters, reference components, etc.) should
be placed over the analog power plane. All digital circuitry
and I/O lines should be placed over the digital power plane.
Furthermore, all components in the reference circuitry and
the input signal chain that are connected to ground should
be connected together with short traces and enter the analog
ground plane at a single, quiet point.
www.national.com 16
Physical Dimensions inches (millimeters) unless otherwise noted
ADC088S022 8-Channel, 50 kSPS to 200 kSPS, 8-Bit A/D Converter
16-Lead TSSOP
Order Number ADC088S022CIMT, ADC088S022CIMTX
NS Package Number MTC16
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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