National Semiconductor ADC083000 Technical data

ADC083000
8-Bit, 3 GSPS, High Performance, Low Power A/D
Converter

ADC083000 8-Bit, 3 GSPS, High Performance, Low Power A/D Converter

May 2007

General Description

The ADC083000 is a single, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 3.4 GSPS. Consuming
a typical 1.9 Watts at 3 GSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and in­terpolating architecture, the fully differential comparator de­sign, the innovative design of the internal sample-and-hold
amplifier and the self-calibration scheme enable a very flat
response of all dynamic parameters up to Nyquist, producing
a high 7.0 Effective Number Of Bits, (ENOB) with a 748 MHz
input signal and a 3 GHz sample rate while providing a 10
Bit Error Rate, (BER). The ADC083000 achieves a 3 GSPS
sampling rate by utilizing both the rising and falling edge of a

1.5 GHz input clock. Output formatting is offset binary and the
LVDS digital outputs are compatible with IEEE 1596.3-1996,
with the exception of an adjustable common mode voltage
between 0.8V and 1.15V.

The ADC has a 1:4 demultiplexer that feeds four LVDS buses
and reduces the output data rate on each bus to a quarter of
the sampling rate.

The converter typically consumes less than 25 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the Indus­trial (-40°C ≤ TA ≤ +85°C) temperature range.

-18

Features

Internal Sample-and-Hold

■

Single +1.9V ±0.1V Operation

■

Choice of SDR or DDR output clocking

■

Guaranteed No Missing Codes

■

Serial Interface for Extended Control

■

Adjustment of Input Full-Scale Range and Offset

■

Duty Cycle Corrected Sample Clock

■

Test pattern

■

Key Specifications

Resolution 8 Bits

■

Max Conversion Rate 3 GSPS (min)

■

Bit Error Rate (BER) 10

■

ENOB @ 748 MHz Input 7.0 Bits (typ)

■

SNR @ 748 MHz 44.5 dB (typ)

■

Full Power Bandwidth 3 GHz (typ)

■

Power Consumption

■

Operating 1.9 W (typ)

—

Power Down Mode 25 mW (typ)

—

Applications

Direct RF Down Conversion

■

Digital Oscilloscopes

■

Satellite Set-top boxes

■

Communications Systems

■

Test Instrumentation

■

-18

(typ)

Ordering Information

Industrial Temperature Range

(-40°C < TA < +85°C)

ADC083000CIYB 128-Pin Exposed Pad LQFP

ADC08x3000EB Development Board

© 2007 National Semiconductor Corporation 201932 www.national.com

NS Package

Block Diagram

ADC083000

Pin Configuration

20193253

20193201

Note: The exposed pad on the bottom of the package must be soldered to a ground plane to ensure rated performance.

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Pin Descriptions and Equivalent Circuits

Pin Functions

Pin No. Symbol Equivalent Circuit Description

Output Voltage Amplitude / Serial Interface Clock
(Input):LVCMOS Tie this pin high for normal differential DCLK

and data amplitude. Ground this pin for a reduced differential

3 OutV / SCLK

OutEdge / DDR /

4

SDATA

output amplitude and reduced power consumption. See Section

1.1.6. When the extended control mode is enabled, this pin
functions as the SCLK input which clocks in the serial data. See
Section 1.2 for details on the extended control mode. See
Section 1.3 for description of the serial interface.

Edge Select / Double Data Rate / Serial Data
(Input):LVCMOS This input sets the output edge of DCLK+ at

which the output data transitions. (See Section 1.1.5.2). When
this pin is floating or connected to 1/2 the supply voltage, DDR
clocking is enabled. When the extended control mode is enabled,
this pin functions as the SDATA input. See Section 1.2 for details
on the extended control mode. See Section 1.3 for description of
the serial interface.

ADC083000

15 DCLK_RST

26 PD

30 CAL

14 FSR/ECE

DCLK Reset
(Input):LVCMOS A positive pulse on this pin is used to reset

and synchronize the DCLK outs of multiple converters. See
Section 1.5 for detailed description. When bit 14 in the
Configuration Register (address 1h) is set to 0b, this single­ended DCLK_RST pin is selected.

Power Down
(Input):LVCMOS A logic high on the PD pin puts the entire

device into the Power Down Mode.

Calibration Cycle Initiate
(Input):LVCMOS A minimum 80 input clock cycles logic low

followed by a minimum of 80 input clock cycles high on this pin
initiates the calibration sequence. See Section 2.4.2 for an
overview of self-calibration and Section 2.4.2.2 for a description
of on-command calibration.

Full Scale Range Select / Extended Control Enable
(Input):LVCMOS In non-extended control mode, a logic low on

this pin sets the full-scale differential input range to 600 mV
A logic high on this pin sets the full-scale differential input range
to 820 mV
mode, whereby the serial interface and control registers are
employed, allow this pin to float or connect it to a voltage equal
to VA/2. See Section 1.2 for information on the extended control
mode.

. See Section 1.1.4. To enable the extended control

P-P

P-P

.

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Pin Functions

Pin No. Symbol Equivalent Circuit Description

ADC083000

127 CalDly / SCS

10
11

18
19

CLK+

CLK-

VIN+
VIN−

Calibration Delay / Serial Interface Chip Select
(Input):LVCMOS With a logic high or low on pin 14, this pin

functions as Calibration Delay and sets the number of input clock
cycles after power up before calibration begins (See Section

1.1.1). With pin 14 floating, this pin acts as the enable pin for the
serial interface input and the CalDly value becomes "0" (short
delay with no provision for a long power-up calibration delay).

Sampling Clock Input
(Input):LVDS The differential clock signal must be a.c. coupled

to these pins. The input signal is sampled on the rising and falling
edge of CLK. See Section 1.1.2 for a description of acquiring the
input and Section 2.3 for an overview of the clock inputs.

Signal Input
(Input):Analog The differential full-scale input range is 600

mV

when the FSR pin is low, or 820 mV

P-P

when the FSR pin

P-P

is high.

22
23

7

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DCLK_RST+

DCLK_RST-

V

CMO

Sample Clock Reset
(Input):LVDS A positive pulse on this pin is used to reset and

synchronize the DCLK outs of multiple converters. See Section

1.5 for detailed description. When bit 14 in the Configuration
Register (address 1h) is set to 1b, these differential DCLK_RST
pins are selected.

Common Mode Voltage
(Output):Analog - The voltage output at this pin is required to

be the common mode input voltage at VIN+ and VIN− when d.c.
coupling is used. This pin should be grounded when a.c. coupling
is used at the analog input. This pin is capable of sourcing or
sinking 100μA and can drive a load up to 80 pF. See Section 2.2.

Pin Functions

Pin No. Symbol Equivalent Circuit Description

Bandgap Output Voltage

31

V

BG

(Output):Analog - Capable of 100 μA source/sink and can drive
a load up to 80 pF.

Calibration Running

126 CalRun

(Output):LVCMOS - This pin is at a logic high when calibration
is running.

External Bias Resistor Connection

32

R

EXT

Analog - Nominal value is 3.3k-Ohms (±0.1%) to ground. See
Section 1.1.1.

ADC083000

34
35

Tdiode_P
Tdiode_N

Temperature Diode
Analog - Positive (Anode) and Negative (Cathode) for die

temperature measurements. See Section 2.6.2.

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Pin Functions

Pin No. Symbol Equivalent Circuit Description

36 / 37
38 / 39

ADC083000

43 / 44
45 / 46
47 / 48
49 / 50
54 / 55
56 / 57
58 / 59
60 / 61
65 / 66
67 / 68
69 / 70
71 / 72
75 / 76
77 / 78

83 / 84
85 / 86
89 / 90
91 / 92
93 / 94

95 / 96
100 / 101
102 / 103
104 / 105
106 / 107
111 / 112
113 / 114
115 / 116
117 / 118
122 / 123
124 / 125

79
80

82
81

Da0+ / Da0­Da1+ / Da1-

Da2+ / Da2−

Da3+ / Da3-

Da4+ / Da4−

Da5+ / Da5-

Da6+ / Da6−

Da7+ / Da7-

Dc0+ / Dc0­Dc1+ / Dc1-

Dc2+ / Dc2−

Dc3+ / Dc3-

Dc4+ / Dc4−

Dc5+ / Dc5-

Dc6+ / Dc6−

Dc7+ / Dc7-

Dd7− / Dd7+

Dd6- / Dd6+

Dd5− / Dd5+

Dd4- / Dd4+
Dd3- / Dd3+
Dd2- / Dd2+

Dd1− / Dd1+

Dd0- / Dd0+
Db7- / Db7+
Db6- / Db6+

Db5− / Db5+

Db4- / Db4+

Db3− / Db3+

Db2- / Db2+

Db1− / Db1+

Db0- / Db0+

OR+
OR-

DCLK+

DCLK-

A and C Data
(Output):LVDS Data Outputs from the first internal converter.

The data should be extracted in the order ABCD These outputs
should always be terminated with a 100Ω differential resistor.

B and D Data
(Output):LVDS Data Outputs from the second internal

converter. The data should be extracted in the order ABCD
These outputs should always be terminated with a 100Ω
differential resistor.

Out Of Range
(Output):LVDS - A differential high at these pins indicates that

the differential input is out of range (outside the range ±325 mV
or ±435 mV as defined by the FSR pin). These outputs should
always be terminated with a 100Ω differential resistor.

Differential Clock
(Output):LVDS - The Differential Clock outputs are used to latch

the output data. Delayed and non-delayed data outputs are
supplied synchronous to this signal. DCLK is 1/2 the sample
clock rate in SDR mode and 1/4 the sample clock rate in the DDR
mode. These outputs should always be terminated with a 100Ω
differential resistor. The DCLK outputs are not active during the
calibration cycle depending on the setting of Configuration
Register (address 1h), bit- 14 (RTD). DCLK is continuously
present during the calibration cycle when bit-14 is set high (1b)
and is not active during the calibration cycle when set low (0b).

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Pin Functions

Pin No. Symbol Equivalent Circuit Description

2, 5, 8, 13,
16, 17, 20,
25, 28, 33,

V

A

Analog power supply pins
(Power) - Bypass these pins to ground.

128

40, 51 ,62,
73, 88, 99,

110, 121

1, 6, 9, 12,

21, 24, 27

V

DR

GND

Output Driver power supply pins
(Power) - Bypass these pins to DR GND.

(Gnd) - Ground return for VA.

42, 53, 64,
74, 87, 97,

DR GND

(Gnd) - Ground return for VDR.

108, 119

29,41,52,

63, 98, 109,

NC No Connection Make no connection to these pins

120

ADC083000

7 www.national.com

Absolute Maximum Ratings

(Notes 1, 2)

If Military/Aerospace specified devices are required,

ADC083000

please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (VA, VDR)

Supply Difference
VA - V

DR

Voltage on Any Input Pin −0.15V to (VA + 0.15V)

Ground Difference
|GND - DR GND| 0V to 100 mV

Input Current at Any Pin (Note 3) ±25 mA
Package Input Current (Note 3) ±50 mA

Power Dissipation at TA ≤ 85°C

ESD Susceptibility (Note 4)
Human Body Model
Machine Model

Storage Temperature −65°C to +150°C

0V to -100mV

2.2V

2.3 W

2500V

250V

Operating Ratings (Notes 1, 2)

Ambient Temperature Range

Supply Voltage (VA)

Driver Supply Voltage (VDR) +1.8V to V

Analog Input Common Mode Voltage V

VIN+, VIN- Voltage Range
(Maintaining Common Mode)

Ground Difference
(|GND - DR GND|) 0V

CLK Pins Voltage Range 0V to V

Differential CLK Amplitude 0.4V

−40°C ≤ TA ≤ +85°C

+1.8V to +2.0V

CMO

200mV to V

to 2.0V

P-P

Package Thermal Resistance

Package

128-Lead

Exposed Pad

LQFP

θ

θ

JA

JC (Top of

Package)

26°C / W 10°C / W 2.8°C / W

θ

(Thermal Pad)

Soldering process must comply with National
Semiconductor’s Reflow Temperature Profile specifications.
Refer to www.national.com/packaging. (Note 5)

Converter Electrical Characteristics

The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
820mV
Non-Extended Control Mode, SDR Mode, R

limits apply for TA = T

Symbol Parameter Conditions

STATIC CONVERTER CHARACTERISTICS

INL Integral Non-Linearity (Best fit)

DNL Differential Non-Linearity

V

OFF

V

OFF

PFSE Positive Full-Scale Error (Note 9) −1.6 ±25 mV (max)

NFSE

FS_ADJ Full-Scale Adjustment Range Extended Control Mode ±20 ±15 %FS

DYNAMIC CONVERTER CHARACTERISTICS

FPBW Full Power Bandwidth 3 GHz

B.E.R. Bit Error Rate

Gain Flatness

ENOB Effective Number of Bits

SINAD

, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, f

P-P

MIN

to T

. All other limits TA = 25°C, unless otherwise noted. (Notes 6, 7)

MAX

= 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface

EXT

DC Coupled, 1MHz Sine Wave Over
Ranged

DC Coupled, 1MHz Sine Wave Over
Ranged

Resolution with No Missing
Codes

8 Bits

Offset Error -0.20 LSB

_ADJ

Input Offset Adjustment Range Extended Control Mode ±45 mV

Negative Full-Scale Error (Note

9)

−1.00 ±25 mV (max)

d.c. to 750 MHz ±0.42 dBFS

d.c. to 1500 MHz ±0.83 dBFS

fIN = 373 MHz, VIN = FSR − 0.5 dB

fIN = 748 MHz, VIN = FSR − 0.5 dB

fIN = 1498 MHz, VIN = FSR − 0.5 dB

Signal-to-Noise Plus Distortion
Ratio

fIN = 373 MHz, VIN = FSR − 0.5 dB

fIN = 748 MHz, VIN = FSR − 0.5 dB

fIN = 1498 MHz, VIN = FSR − 0.5 dB

= 1.5GHz at 0.5V

CLK

with 50% duty cycle, VBG = Floating,

P-P

Typical

(Note 8)

Limits

(Note 8)

±0.35 ±0.9 LSB (max)

±0.20 ±0.6 LSB (max)

-18

10

Error/Sample

7.2 6.85 Bits (min)

7.0 6.6 Bits (min)

6.5 Bits

45 42.2 dB (min)

44.2 40.8 dB (min)

41.1 dB

A

±50mV

A

A

P-P

J-PAD

Units

(Limits)

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ADC083000

Symbol Parameter Conditions

fIN = 373 MHz, VIN = FSR − 0.5 dB

SNR Signal-to-Noise Ratio

fIN = 748 MHz, VIN = FSR − 0.5 dB

fIN = 1498 MHz, VIN = FSR − 0.5 dB

fIN = 373 MHz, VIN = FSR − 0.5 dB

THD Total Harmonic Distortion

fIN = 748 MHz, VIN = FSR − 0.5 dB

fIN = 1498 MHz, VIN = FSR − 0.5 dB

fIN = 373 MHz, VIN = FSR − 0.5 dB

2nd Harm Second Harmonic Distortion

fIN = 748 MHz, VIN = FSR − 0.5 dB

fIN = 1498 MHz, VIN = FSR − 0.5 dB

fIN = 373 MHz, VIN = FSR − 0.5 dB

3rd Harm Third Harmonic Distortion

fIN = 748 MHz, VIN = FSR − 0.5 dB

fIN = 1498 MHz, VIN = FSR − 0.5 dB

fIN = 373 MHz, VIN = FSR − 0.5 dB

SFDR Spurious-Free dynamic Range

fIN = 748 MHz, VIN = FSR − 0.5 dB

fIN = 1498 MHz, VIN = FSR − 0.5 dB

ANALOG INPUT AND REFERENCE CHARACTERISTICS

FSR pin 14 Low 600

V

IN

Full Scale Analog Differential
Input Range

FSR pin 14 High 820

V

CMI

C

IN

R

IN

Analog Input Common Mode
Voltage

Analog Input Capacitance (Notes
10, 11)

Differential Input Resistance 100

Differential 1.08 pF

Each input pin to ground 2.2 pF

ANALOG OUTPUT CHARACTERISTICS

V

CMO

V

CMO_LVL

TC V

CMO

C

LOAD VCMO

V

BG

TC V

BG

C

LOAD VBG

Common Mode Output Voltage

V

input threshold to set DC

CMO

Coupling mode

Common Mode Output Voltage
Temperature Coefficient

Maximum V

CMO

load

Capacitance

Bandgap Reference Output
Voltage

Bandgap Reference Voltage
Temperature Coefficient

Maximum Bandgap Reference
load Capacitance

I

= ±100 µA

CMO

VA = 1.8V

VA = 2.0V

TA = −40°C to +85°C

80 pF

IBG = ±100 µA

TA = −40°C to +85°C,
IBG = ±100 µA

80 pF

Typical

(Note 8)

Limits

(Note 8)

Units

(Limits)

45.3 43.2 dB (min)

44.5 41.7 dB (min)

41.8 dB

-57 -49 dB (max)

-56 -48 dB (max)

-49.5 dB

−68 dB

−66 dB

−56 dB

−64 dB

−58 dB

−52 dB

57 49 dB (min)

54.5 48 dB (min)

52.0 dB

mV

P-P

mV

P-P

mV

P-P

mV

P-P

mV (min)
mV (max)

Ω (min)

V

CMO

550

650

770

870

V

− 50

CMO

V

+ 50

CMO

95

1.26

105

0.95

1.45

Ω (max)

V (min)

V (max)

0.60 V

0.66 V

118 ppm/°C

1.26

1.20

1.33

V (min)

V (max)

28 ppm/°C

(min)

(max)

(min)

(max)

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Symbol Parameter Conditions

TEMPERATURE DIODE CHARACTERISTICS

ADC083000

ΔV

BE

Temperature Diode Voltage

192 µA vs. 12 µA,
TJ = 25°C

192 µA vs. 12 µA,
TJ = 85°C

LVDS INPUT CHARACTERISTICS

Sine Wave Clock 0.6

V

ID

Differential Clock Input Level

Square Wave Clock 0.6

I

I

C

IN

Input Current

Input Capacitance (Notes 10, 11)

VIN = 0 or VIN = V

Differential 0.02 pF

Each input to ground 1.5 pF

LVDS OUTPUT CHARACTERISTICS

Measured differentially, OutV = VA, V

V

OD

LVDS Differential Output Voltage

= Floating (Note 15)

Measured differentially, OutV = GND,
VBG = Floating (Note 15)

Δ V

V

V

Δ V

I

OS

Z

O

OS

OS

O DIFF

OS

Change in LVDS Output Swing
Between Logic Levels

Output Offset Voltage,
see Figure 1

Output Offset Voltage,
see Figure 1

Output Offset Voltage Change
Between Logic Levels

Output Short Circuit Current Output+ & Output- connected to 0.8V ±4 mA

Differential Output Impedance 100 Ohms

±1 mV

VBG = Floating

VBG = VA (Note 15)

±1 mV

LVCMOS INPUT CHARACTERISTICS

V

IH

V

IL

C

IN

Logic High Input Voltage (Note 12)

Logic Low Input Voltage (Note 12)

Input Capacitance (Notes 11, 13) Each input to ground 1.2 pF

LVCMOS OUTPUT CHARACTERISTICS

V

OH

V

OL

CMOS H level output

CMOS L level output

IOH = -400uA (Note 12)

IOH = 400uA (Note 12)

POWER SUPPLY CHARACTERISTICS

I

A

I

DR

P

D

Analog Supply Current PD = Low 734 810 mA (max)

Output Driver Supply Current PD = Low 300 410 mA (max)

Power Consumption

PD = Low 1.9 2.3 W (max)

PD = High 25 mW

Typical

(Note 8)

Limits

(Note 8)

Units

(Limits)

71.23 mV

85.54 mV

V

V

V

mV

mV

mV

mV

V

P-P

P-P

P-P

P-P

P-P

P-P

P-P

P-P

(min)

(max)

(min)

(max)

(min)

(max)

(min)

(max)

0.4

2.0

0.4

2.0

A

BG

±1 µA

680

520

470

920

380

720

800 mV

1150 mV

0.85 x V

0.15 x V

A

A

V (min)

V (max)

1.65 1.5 V

0.15 0.3 V

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ADC083000

Symbol Parameter Conditions

Typical

(Note 8)

Limits

(Note 8)

Units

(Limits)

AC ELECTRICAL CHARACTERISTICS - Sampling Clock

f

CLK1

f

CLK2

t

CYC

t

LC

t

HC

DCLK Duty Cycle (Note 11) 50

t

AD

t

AJ

t

OD

Maximum Input Clock Frequency Sampling rate is 2x clock input 1.7 1.5 GHz (min)

Minimum Input Clock Frequency Sampling rate is 2x clock input 500 MHz

Input Clock Duty Cycle

500MHz ≤ Input clock frequency ≤ 1.5
GHz (Note 12)

50

20
80

% (min)
% (max)

Input Clock Low Time (Note 11) 333 133 ps (min)

Input Clock High Time (Note 11) 333 133 ps (min)

Sampling (Aperture) Delay

Input CLK transition to Acquisition of
Data

45
55

1.4 ns

% (min)
% (max)

Aperture Jitter 0.55 ps rms

Input Clock to Data Output Delay
(in addition to Pipeline Delay)

50% of Input Clock transition to 50% of
Data transition

3.7 ns

Dd Outputs 13

Pipeline Delay (Latency)
(Notes 11, 14)

Db Outputs 14

Dc Outputs 13.5

Input Clock

Cycles

Da Outputs 14.5

AC ELECTRICAL CHARACTERISTICS - Output Clock and Data (Note 16)

t

t

LHT

HLT

LH Transition Time - Differential 10% to 90% 150 ps

HL Transition Time - Differential 10% to 90% 150 ps

50% of DCLK transition to 50% of Data

t

SKEWO

DCLK to Data Output Skew

transition, SDR Mode

±50 ps (max)

and DDR Mode, 0° DCLK (Note 11)

t

OSU

t

OH

Data to DCLK Set-Up Time DDR Mode, 90° DCLK (Note 12) 570 ps

DCLK to Data Hold Time DDR Mode, 90° DCLK (Note 12) 555 ps

AC ELECTRICAL CHARACTERISTICS - Serial Interface Clock

f

SCLK

t

SS

t

HS

Serial Clock Frequency (Note 11) 67 MHz

Data to Serial Clock Setup Time (Note 11) 2.5 ns (min)

Data to Serial Clock Hold Time (Note 11) 1 ns (min)

Serial Clock Low Time 6 ns (min)

Serial Clock High Time 6 ns (min)

AC ELECTRICAL CHARACTERISTICS - General Signals

t

SR

t

HR

t

PWR

t

WU

t

CAL

t

CAL_L

t

CAL_H

t

CalDly

t

CalDly

Setup Time DCLK_RST±

Hold Time DCLK_RST± 30 ps

(Note 12)

90 ps

Pulse Width DCLK_RST± (Note 11) 4 CLK± Cyc. (min)

PD low to Rated Accuracy
Conversion (Wake-Up Time)

Calibration Cycle Time

(Note 11) 1 µs

5

1.4 x 10

CLK± Cyc.

CAL Pin Low Time See Figure 8 (Note 11) 80 CLK± Cyc. (min)

CAL Pin High Time See Figure 8 (Note 11) 80 CLK± Cyc.(min)

Calibration delay determined by
pin 127

Calibration delay determined by
pin 127

See Section 1.1.1, Figure 8, (Note 11)

See Section 1.1.1, Figure 8, (Note 11)

25

2

2

31

CLK± Cyc.(min)

CLK± Cyc.(max)

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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum
Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.

Note 2: All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.

ADC083000

Note 3: When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than VA), the current at that pin should be limited to

25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to
two. This limit is not placed upon the power, ground and digital output pins.

Note 4: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.

Note 5: Reflow temperature profiles are different for lead-free and non-lead-free packages.

Note 6: The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.

20193204

Note 7: To guarantee accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally,
achieving rated performance requires that the backside exposed pad be well grounded.

Note 8: Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality
Level).

Note 9: Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,
therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 2. For relationship between Gain Error and Full-Scale Error, see
Specification Definitions for Gain Error.

Note 10: The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF each pin to
ground are isolated from the die capacitances by lead and bond wire inductances.

Note 11: This parameter is guaranteed by design and is not tested in production.

Note 12: This parameter is guaranteed by design and/or characterization and is not tested in production.

Note 13: The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die

capacitances by lead and bond wire inductances.

Note 14: Each of the two converters of the ADC083000 has two LVDS output buses, which each clock data out at one quarter the sample rate. Bus Db has a
pipeline latency that is one Input Clock cycle less than the latency of bus Dd. Likewise, bus Da has a pipeline latency that is one Input Clock cycle less than the
latency of bus Dc.

Note 15: Tying VBG to the supply rail will increase the output offset voltage (VOS) by 400mv (typical), as shown in the VOS specification above. Tying VBG to the
supply rail will also affect the differential LVDS output voltage (VOD), causing it to increase by 40mV (typical).

Note 16: All parameters are measured through a transmission line and 100Ω termination using a 0.33pF load oscilloscope probe.

Specification Definitions

APERTURE (SAMPLING) DELAY is the amount of delay,

measured from the sampling edge of the Clock input, after
which the signal present at the input pin is sampled inside the
device.

APERTURE JITTER (tAJ) is the variation in aperture delay
from sample to sample. Aperture jitter shows up as input
noise.

Bit Error Rate (B.E.R.) is the probability of error and is de­fined as the probable number of errors per unit of time divided
by the number of bits seen in that amount of time. A B.E.R. of

-18

10

corresponds to a statistical error in one bit about every

four (4) years.
CLOCK DUTY CYCLE is the ratio of the time that the clock

wave form is at a logic high to the total time of one clock pe­riod.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
Measured at 3 GSPS with a ramp input.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and

Distortion Ratio, or SINAD. ENOB is defined as (SINAD −

1.76) / 6.02 and says that the converter is equivalent to a per-

FULL POWER BANDWIDTH (FPBW) is a measure of the
frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.

GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated from Offset and Full­Scale Errors:

Positive Gain Error = Offset Error − Positive Full-Scale
Error

Negative Gain Error = −(Offset Error − Negative Full­Scale Error)

Gain Error = Negative Full-Scale Error − Positive Full­Scale Error = Positive Gain Error + Negative Gain Error

INTEGRAL NON-LINEARITY (INL) is a measure of the de­viation of each individual code from a straight line through the
input to output transfer function. The deviation of any given
code from this straight line is measured from the center of that
code value. The best fit method is used.

INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the second and third
order intermodulation products to the power in one of the
original frequencies. IMD is usually expressed in dBFS.

fect ADC of this (ENOB) number of bits.

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