National Semiconductor ADC08231, ADC08234, ADC08238 Technical data

查询ADC08231供应商查询ADC08231供应商

ADC08231/ADC08234/ADC08238 8-Bit 2 ms Serial I/O
A/D Converters with MUX, Reference, and Track/Hold

General Description

The ADC08231/ADC08234/ADC08238 are 8-bit succes­sive approximation A/D converters with serial I/O and con­figurable input multiplexers with up to 8 channels. The serial
I/O is configured to comply with the NSC MICROWIRE
serial data exchange standard for easy interface to the

TM

COPS

family of controllers, and can easily interface with

standard shift registers or microprocessors.

Designed for high-speed/low-power applications, the devic­es are capable of a fast 2 ms conversion when used with a
4 MHz clock.

All three devices provide a 2.5V band-gap derived reference
with guaranteed performance over temperature.

A track/hold function allows the analog voltage at the posi­tive input to vary during the actual A/D conversion.

The analog inputs can be configured to operate in various
combinations of single-ended, differential, or pseudo-differ­ential modes. In addition, input voltage spans as small as 1V
can be accommodated.

Applications

Y

High-speed data acquisition

Y

Digitizing automotive sensors

Y

Process control/monitoring

Y

Remote sensing in noisy environments

Y

Disk drives

Y

Portable instrumentation

Y

Test systems

Features

Y

Serial digital data link requires few I/O pins

Y

Analog input track/hold function

Y

4- or 8-channel input multiplexer options with address

TM

logic

Y

On-chip 2.5V band-gap reference (g2% over tempera­ture guaranteed)

Y

No zero or full scale adjustment required

Y

TTL/CMOS input/output compatible

Y

0V to 5V analog input range with single 5V power
supply

Y

Pin compatible with Industry-Standards ADC0831/4/8

Key Specifications

Y

Resolution 8 Bits

Y

Conversion time (f

Y

Power dissipation 20 mW (Max)

Y

Single supply 5 VDC(g5%)

Y

Total unadjusted error

Y

Linearity Error (V

Y

No missing codes (over temperature)

Y

On-board Reference

e

4 MHz) 2 ms (Max)

C

g

(/2 LSB andg1 LSB

a

REF

e

2.5V)

December 1994

g

(/2 LSB

2.5Vg1.5% (Max)

ADC08231/ADC08234/ADC08238 8-Bit 2 ms Serial I/O A/D Converters

with MUX, Reference, and Track/Hold

ADC08238 Simplified Block Diagram

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

TM

COPS

microcontrollers and MICROWIRETMare trademarks of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

TL/H/11015

TL/H/11015– 4

Ordering Information

Connection Diagrams

ADC08238

SO and DIP

b

(

40§CsT

Industrial

s

A

a

85§C)

Package

ADC08231BIN, ADC08231CIN N08E, DIP

ADC08234BIN, ADC08234CIN N14A, DIP

ADC08234CIMF MTB24, TSSOP

ADC08238BIN, ADC08238CIN N20A, DIP

ADC08231BIWM, ADC08231CIWM M14B, SO

ADC08234BIWM, ADC08234CIWM M14B, SO

ADC08238BIWM, ADC08238CIWM M20B, SO

ADC08234

SO and DIP

TL/H/11015– 2

ADC08231

DIP

ADC08231

SO

TL/H/11015– 1

TL/H/11015– 3

TL/H/11015– 26

ADC08234

TSSOP

TL/H/11015– 27

2

Absolute Maximum Ratings (Notes1&3)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (V

Voltage at Inputs and Outputs

Input Current at Any Pin (Note 4)

Package Input Current (Note 4)

Power Dissipation at T

ESD Susceptibility (Note 6) 1500V

Soldering Information

N Package (10 sec.) 260
TSSOP and SO Package (Note 7):

Vapor Phase (60 sec.) 215
Infrared (15 sec.) 220

Storage Temperature

) 6.5V

CC

e

25§C (Note 5) 800 mW

A

b

0.3V to V

b

65§Ctoa150§C

CC

g

a

0.3V

g

5mA

20 mA

§

§

§

Operating Ratings (Notes2&3)

Temperature Range T

ADC08231BIN, ADC08231CIN,

ADC08234BIN, ADC08234CIN,

ADC08238BIN, ADC08238CIN,

ADC08231BIWM, ADC08231CIWM,

ADC08234BIWM, ADC08238BIWM,

ADC08234CIWM, ADC08238CIWM,

ADC08234CIMF

Supply Voltage (V

C

C
C

) 4.5 VDCto 6.3 V

CC

b

40§CsT

MIN

s

s

T

T

A

MAX

s

a

85§C

A

DC

Electrical Characteristics

The following specifications apply for V
specified. Boldface limits apply for T

CC

ea

5VDC,V

e

e

T

A

T

J

MIN

REF

to T

ea

MAX

2.5 VDCand f

; all other limits T

CLK

e

e

A

4 MHz, R

T

J

ADC08231,

ADC08234 and

ADC08238 with BIN,

Symbol Parameter Conditions CIN, BIWM,

CIWM, or CIMF Suffixes

Typical Limits

(Note 8) (Note 9)

CONVERTER AND MULTIPLEXER CHARACTERISTICS

Linearity Error V

BIN, BIWM

REF

ea

2.5 V

DC

CIN, CIMF, CIWM

Gain Error V

BIN, BIWM

REF

ea

2.5 V

DC

CIN, CIMF, CIWM

Zero Error V

BIN, BIWM

REF

ea

2.5 V

DC

CIN, CIMF, CIWM

Total Unadjusted Error V

BIN, BIWM (Note 10)

REF

ea

5V

DC

CIN, CIMF, CIWM

Differential Linearity V

R

REF

V

IN

Reference Input Resistance (Note 11) 3.5 kX

Analog Input Voltage (Note 12) (V

REF

ea

2.5 V

DC

e

50X unless otherwise

Source

e

25§C.

g

(/2 LSB (max)

g

1 LSB (max)

g

1 LSB (max)

g

1 LSB (max)

g

1 LSB (max)

g

1 LSB (max)

g

1 LSB (max)

g

1 LSB (max)

8 Bits (min)

1.3 kX (min)

6.0 kX (max)

a

0.05) V (max)

CC

b

(GND

0.05) V (min)

Units

(Limits)

3

Electrical Characteristics (Continued)

The following specifications apply for V
specified. Boldface limits apply for T

CC

A

ea

e

T

J

5VDC,V

e

T

MIN

REF

to T

ea

MAX

2.5 VDCand f

; all other limits T

CLK

e

e

A

4 MHz, R

e

T

J

ADC08231,

ADC08234 and

ADC08238 with BIN,

Symbol Parameter Conditions CIN, BIWM,

CIWM, or CIMF Suffixes

Typical Limits

(Note 8) (Note 9)

CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued)

DC Common-Mode Error V

Power Supply Sensitivity V

ea

ea

ea

2.5 V

DC

5Vg5%,

2.5 V

DC

REF

CC

V

REF

On Channel Leakage On Channele5V, 0.2
Current (Note 13) Off Channel

e

0V 1

On Channele0V,
Off Channele5V

Off Channel Leakage On Channele5V,
Current (Note 13) Off Channel

e

0V

On Channele0V, 0.2
Off Channel

e

5V 1

DYNAMIC CHARACTERISTICS (see Typical Converter Performance Characteristics)

S

NaD

Signal-to- V

a

(Noise

Distortion) Sample Ratee286 kHz

Ratio V

ea

REF

IN

f

IN

f

IN

f

IN

5V

ea

5V

p-p

e

10 kHz 48.35 dB

e

50 kHz 48.00 dB

e

100 kHz 47.40 dB

DIGITAL AND DC CHARACTERISTICS

V

IN(1)

V

IN(0)

I

IN(1)

I

IN(0)

V

OUT(1)

V

OUT(0)

I

OUT

I

SOURCE

I

SINK

I

CC

Logical ‘‘1’’ Input Voltage V

Logical ‘‘0’’ Input Voltage V

Logical ‘‘1’’ Input Current V

Logical ‘‘0’’ Input Current V

Logical ‘‘1’’ Output Voltage V

Logical ‘‘0’’ Output Voltage V

TRI-STATEÉOutput Current V

Output Source Current V

Output Sink Current V

Supply Current CSeHIGH

ADC08234, ADC08238 3.0 mA (max)

e

5.25V 2.0 V (min)

CC

e

4.75V 0.8 V (max)

CC

e

5.0V 1 mA (max)

IN

e

0V

IN

e

4.75V:

CC

eb

I

OUT

I

OUT

I

OUT

V

360 mA 2.4 V (min)

eb

10 mA 4.5 V (min)

e

4.75V 0.4 V (max)

CC

e

1.6 mA

e

0V

OUT

e

5V 3.0 mA (max)

OUT

e

0V

OUT

e

V

OUT

CC

ADC08231 (Note 16) 6.0 mA (max)

e

source

25§C.

g

g

b

b

b

b

b

b

3.0 mA (max)

b

6.5 mA (min)

8.0 mA (min)

50X unless otherwise

Units

(Limits)

(/2 LSB (max)

(/4 LSB (max)

mA (max)

0.2

1

0.2

1

mA (max)

mA (max)

mA (max)

1 mA (max)

4

Electrical Characteristics (Continued)

The following specifications apply for V

e

T

e

T

T

to T

A

J

MIN

; all other limits T

MAX

CC

ea

A

5VDCand f

e

e

T

J

25§C.

e

4 MHz unless otherwise specified. Boldface limits apply for

CLK

ADC08234 and

ADC08238 with BIN,

Symbol Parameter Conditions CIN, BIWM,

CIWM, or CIMF Suffixes

Typical Limits

(Note 8) (Note 9)

REFERENCE CHARACTERISTICS

V

OUT Output Voltage BIN, BIJ, 2.5

REF

BIWM

g

2%

CIN, CIJ, 2.5

g

CIWM, CMJ

DV

/DT Temperature Coefficient 40 ppm/§C

REF

DV

REF

/DI

Load Regulation Sourcing

L

(Note 17) (0sI

s

L

ADC08234,

a

4 mA)

ADC08238

3.5%

0.003 0.1

Sourcing

s

s

(0
ADC08231 0.003 0.1

a

I

2 mA)

L

Sinking
(b1sI
ADC08234,
ADC08238

s

0 mA)

L

0.2 0.5

Sinking

s

b

(

1sI

0 mA)

L

ADC08231 0.2 0.5

e

0V

e

0V

100 mF

CC

s

5.25V

0.5 6

8 25

20 ms

Line Regulation 4.75VsV

I

SC

Short Circuit Current V

REF

ADC08234,
ADC08238

V

REF

ADC08231 8 25

T

SU

DV

/Dt Long Term Stability 200 ppm/1 kHr

REF

Start-Up Time VCC:0Vx5V

e

C

L

ADC08231,

2.5

2.5

g

g

Units

(Limits)

1.5%

V

3.0%

%/mA

(max)

mV

(max)

mA

(max)

5

Electrical Characteristics (Continued)

The following specifications apply for V

Boldface limits apply for T

Symbol Parameter Conditions

f

CLK

Clock Frequency 10 kHz (min)

e

T

A

ea

5VDC,V

CC

e

T

MIN

to T

MAX

J

ea

REF

; all other limits T

2.5 VDCand t

e

e

t

r

e

e

T

A

J

20 ns unless otherwise specified.

f

25§C.

Typical Limits Units
(Note 8) (Note 9) (Limits)

4 MHz (max)

Clock Duty Cycle 40 % (min)
(Note 14) 60 % (max)

T

C

t

CA

t

SELECT

t

SET-UP

t

HOLD

t

pd1,tpd0

Conversion Time (Not Including f
MUX Addressing Time) 2 ms (max)

Acquisition Time 1(/2 1/f

CLK High while CS is High 50 ns

CS Falling Edge or Data Input
Valid to CLK Rising Edge

Data Input Valid after CLK
Rising Edge

CLK Falling Edge to Output C
Data Valid (Note 15) Data MSB First 250 ns (max)

e

4 MHz 8 1/f

CLK

e

100 pF:

L

(max)

CLK

(max)

CLK

25 ns (min)

20 ns (min)

Data LSB First 200 ns (max)

t1H,t

C

IN

C

OUT

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed

specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.

Note 3: All voltages are measured with respect to AGND
Note 4: When the input voltage (V

5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four
pins.

Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
with suffixes BIN, CIN, BIJ, CIJ, BIWM, and CIWM T
parts when board mounted follow: ADC08231 with BIN and CIN suffixes 120
167

§

ADC08238 with BIWM and CIWM suffixes 91

Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kX resistor.
Note 7: See AN450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or

soldering surface mount devices.

Note 8: Typicals are at T
Note 9: Guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Total unadjusted error includes zero, full-scale, linearity, and multiplexer error. Total unadjusted error with V

and ADC08238. See Note 16.

Note 11: Cannot be tested for the ADC08231.
Note 12: For V

for analog input voltages one diode drop below ground or one diode drop greater than V
inputs (e.g., 5V) can cause an input diode to conduct, especially at elevated temperatures. This will cause errors for analog inputs near full-scale. The specification
allows 50 mV forward bias of either diode; this means that as long as the analog V
be correct. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 V
range will therefore require a minimum supply voltage of 4.950 V

Note 13: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following
two cases are considered: one, with the selected channel tied high (5 V
channels is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channels is again measured. The two
cases considered for determining on channel leakage current are the same except total current flow through the selected channel is measured.

Note 14: A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these
limits the minimum time the clock is high or low must be at least 120 ns. The maximum time the clock can be high or low is 100 m s.

Note 15: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to
allow for comparator response time.

Note 16: For the ADC08231 V
reference current (700 mA typical, 2 mA maximum).

Note 17: Load regulation test conditions and specifications for the ADC08231 differ from those of the ADC08234 and ADC08238 because the ADC08231 has the
on-board reference as a permanent load.

TRI-STATE Delay from Rising Edge C

0H

of CS

to Data Output and SARS Hi-Z (see TRI-STATE Test Circuits)

Capacitance of Logic Inputs 5 pF

Capacitance of Logic Outputs 5 pF

C/W,

e

e

(T

D

J

MAX

e

J

MAX

) at any pin exceeds the power supplies (V

IN

C/W, ADC08238 with BIN and CIN suffixes 80§C/W. ADC08231 with BIWM and CIWM suffixes 140§C/W, ADC08234 with BIWM and CIWM suffixes 140§C/W,

e

25§C and represent the most likely parametric norm.

J

t

V

IN(b)

the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct

IN(a)

REF

§

IN is internally tied to the on chip 2.5V band-gap reference output; therefore, the supply current is larger because it includes the

e

10 pF, R

L

e

C

100 pF, R

L

DGNDe0VDC, unless otherwise specified.

b

TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. For devices

125§C. For devices with suffix CMJ, T

over temperature variations, initial tolerance and loading.

DC

) and the remaining off channels tied low (0 VDC), total current flow through the off

DC

e

10 kX

L

e

2kX 180 ns (max)

L

k

(AGND or DGND) or V

IN

J

MAX

J

C/W, ADC08234 with BIN and CIN suffixes 95§C/W, ADC08234 with CIMF suffix

§

does not exceed the supply voltage by more than 50 mV, the output code will

IN

MAX

Linear Data Book

supply. During testing at low VCClevels (e.g., 4.5V), high level analog

CC

50 ns

l

AVCC,) the current at that pin should be limited to

IN

, iJAand the ambient temperature, TA. The maximum

e

150§C. The typical thermal resistances (iJA) of these

section ‘‘Surface Mount’’ for other methods of

ea

5V only applies to the ADC08234

REF

to5VDCinput voltage

DC

6

Typical Performance Characteristics

Linearity Error vs
Reference Voltage

Power Supply Current vs
Temperature (ADC08238,
ADC08234)

Note: For ADC08231 add I

Spectral Response with
10 kHz Sine Wave Input

Linearity Error vs
Temperature

Output Current vs
Temperature

(Note 16) TL/H/11015– 5

REF

Spectral Response with
50 kHz Sine Wave Input

Linearity Error vs
Clock Frequency

Power Supply Current
vs Clock Frequency

Spectral Response with
100 kHz Sine Wave Input

a

Signal-to-Noise

Distortion

Ratio vs Input Frequency

7

TL/H/11015– 6

Typical Reference Performance Characteristics

Line Regulation

Load Regulation (3 Typical Parts)

Available
Output Current
vs Supply Voltage

Output Drift
vs Temperature
(3 Typical Parts)

TL/H/11015– 7

8

TRI-STATE Test Circuits and Waveforms

t

1H

t

0H

t

1H

t

0H

TL/H/11015– 8

Timing Diagrams

Data Input Timing

*To reset these devices, CLK and CS must be simultaneously high for a period of t

Data Output Timing

ADC08231 Start Conversion Timing

SELECT

TL/H/11015– 9

TL/H/11015– 10

or greater.

TL/H/11015– 11

TL/H/11015– 12

9

Timing Diagrams (Continued)

ADC08231 Timing

*LSB first output not available on ADC08231.

LSB information is maintained for remainder of clock periods until CS

To reset the ADC08231, CLK and CS
the analog signal (t

). Otherwise it is compatible with the ADC0831.

ca

must be simultaneusly high for a period of t

goes high.

ADC08234 Timing

To reset the ADC08234, CLK and CS must be simultaneously high for a period of t
the analog signal (t

). Otherwise it is compatible with the ADC0834.

ca

or greater. The ADC08231 also has one extra clock period for sampling

SELECT

or greater. The ADC08234 also has one extra clock period for sampling

SELECT

TL/H/11015– 13

TL/H/11015– 14

10

Timing Diagrams (Continued)

TL/H/11015– 15

). Otherwise it is compatible with the ADC0838.

ca

ADC08238 Timing

or greater. The ADC08238 also has one extra clock period for sampling the analog signal (t

SELECT

must be simultaneously high for a period of t

19 clocks in the LSB before SE is taken low

Ý

To reset the ADC08238, CLK and CS

*Make sure clock edge

11

ADC08238 Functional Block Diagram

TL/H/11015– 16

are internally tied together.

REFIN

and V

REFOUT

*Some of these functions/pins are not available with other options.

Note 1: For the ADC08234, the ‘‘SEL 1’’ Flip-Flop is bypassed. For the ADC08231, V

12

Functional Description

1.0 MULTIPLEXER ADDRESSING

The design of these converters utilizes a comparator struc­ture with built-in sample-and-hold which provides for a dif­ferential analog input to be converted by a successive­approximation routine.

The actual voltage converted is always the difference be­tween an assigned ‘‘
minal. The polarity of each input terminal of the pair indi­cates which line the converter expects to be the most posi­tive. If the assigned ‘‘
input voltage the converter responds with an all zeros out­put code.

A unique input multiplexing scheme has been utilized to pro­vide multiple analog channels with software-configurable
single-ended, differential, or pseudo-differential (which will
convert the difference between the voltage at any analog
input and a common terminal) operation. The analog signal
conditioning required in transducer-based data acquisition
systems is significantly simplified with this type of input flexi­bility. One converter package can now handle ground refer­enced inputs and true differential inputs as well as signals
with some arbitrary reference voltage.

A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single-ended or differen­tial. Differential inputs are restricted to adjacent channel
pairs. For example, channel 0 and channel 1 may be select­ed as a differential pair but channel 0 or 1 cannot act

Single-Ended MUX Mode

START

11000

11001

11010

11011

11100

11101

11110

11111

a

’’ input terminal and a ‘‘b’’ input ter-

a

’’ input voltage is less than the ‘‘b’’

TABLE II. MUX Addressing: ADC08238

MUX Address Analog Single-Ended Channel

SGL/ ODD/ SELECT

DIF SIGN

10

01234567COM

a b

differentially with any other channel. In addition to selecting
differential mode the polarity may also be selected. Channel
0 may be selected as the positive input and channel 1 as
the negative input or vice versa. This programmability is
best illustrated by the MUX addressing codes shown in the
following tables for the various product options.

The MUX address is shifted into the converter via the DI
line. Because the ADC08231 contains only one differential
input channel with a fixed polarity assignment, it does not
require addressing.

The common input line (COM) on the ADC08238 can be
used as a pseudo-differential input. In this mode the voltage
on this pin is treated as the ‘‘

b

’’ input for any of the other
input channels. This voltage does not have to be analog
ground; it can be any reference potential which is common
to all of the inputs. This feature is most useful in single-sup­ply applications where the analog circuitry may be biased up
to a potential other than ground and the output signals are
all referred to this potential.

TABLE I. Multiplexer/Package Options

Part Number of Analog Channels Number of

Number

Single-Ended Differential

Package Pins

ADC08231 1 1 8

ADC08234 4 2 14

ADC08238 8 4 20

Ý

ab

ab

ab

ab

ab

ab

ab

13

Functional Description (Continued)

TABLE II. MUX Addressing: ADC08238 (Continued)

Differential MUX Mode

MUX Address Analog Differential Channel-Pair

START

10000

10001

10010

10011

10100

10101

10110

10111

SGL/ ODD/ SELECT 0 1 2 3

DIF SIGN

1001234567

TABLE III. MUX Addressing: ADC08234

Single-Ended MUX Mode

MUX Address Channel

START

SGL/ ODD/ SELECT

DIF SIGN

110 0

110 1

111 0

111 1

Ý

ab

ab

ab

ab

ba

ba

ba

ba

Ý

0123

1

a

a

a

a

COM is internally tied to AGND

Differential MUX Mode

MUX Address Channel

START

SGL/ ODD/ SELECT

DIF SIGN

100 0

100 1

101 0

101 1

14

Ý

0123

1

ab

ab

ba

ba

Functional Description (Continued)

Since the input configuration is under software control, it
can be modified as required before each conversion. A
channel can be treated as a single-ended, ground refer­enced input for one conversion; then it can be reconfigured
as part of a differential channel for another conversion.

ure 1

illustrates the input flexibility which can be achieved.

The analog input voltages for each channel can range from
50mV below ground to 50mV above V
out degrading conversion accuracy.

2.0 THE DIGITAL INTERFACE

A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system im­provements; it allows many functions to be included in a
small package and it can eliminate the transmission of low
level analog signals by locating the converter right at the
analog sensor; transmitting highly noise immune digital data
back to the host processor.

(typically 5V) with-

CC

8 Single-Ended 8 Pseudo-Differential

Fig-

To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate timing diagram is shown for each device.

1. A conversion is initiated by pulling the CS

line low. This line must be held low for the entire conver­sion. The converter is now waiting for a start bit and its
MUX assignment word.

2. On each rising edge of the clock the status of the data in

(DI) line is clocked into the MUX address shift register.
The start bit is the first logic ‘‘1’’ that appears on this line
(all leading zeros are ignored). Following the start bit the
converter expects the next 2 to 4 bits to be the MUX
assignment word.

(chip select)

4 Differential Mixed Mode

FIGURE 1. Analog Input Multiplexer Options for the ADC08238

15

TL/H/11015– 17

Functional Description (Continued)

3. When the start bit has been shifted into the start location
of the MUX register, the input channel has been assigned
and a conversion is about to begin. An interval of 1(/2
clock periods is automatically inserted to allow for sam­pling the analog input. The SARS line goes high at the
end of this time to signal that a conversion is now in prog­ress and the DI line is disabled (it no longer accepts
data).

4. The data out (DO) line now comes out of TRI-STATE and
provides a leading zero.

5. During the conversion the output of the SAR comparator
indicates whether the analog input is greater than (high)
or less than (low) a series of successive voltages gener­ated internally from a ratioed capacitor array (first 5 bits)
and a resistor ladder (last 3 bits). After each comparison
the comparator’s output is shipped to the DO line on the
falling edge of CLK. This data is the result of the conver­sion being shifted out (with the MSB first) and can be
read by the processor immediately.

6. After 8 clock periods the conversion is completed. The
SARS line returns low to indicate this (/2 clock cycle later.

7. The stored data in the successive approximation register
is loaded into an internal shift register. If the programmer
prefers, the data can be provided in an LSB first format

[

this makes use of the shift enable (SE

the ADC08238 the SE

line is brought out and if held high
the value of the LSB remains valid on the DO line. When
SE

is forced low the data is clocked out LSB first. On
devices which do not include the SE
data, LSB first, is automatically shifted out the DO line
after the MSB first data stream. The DO line then goes
low and stays low until CS
ADC08231 is an exception in that its data is only output in
MSB first format.

8. All internal registers are cleared when the CS
and the t
ing under Timing Diagrams. If another conversion is de­sired CS

requirement is met. See Data Input Tim-

SELECT

must make a high to low transition followed by

address information.

The DI and DO lines can be tied together and controlled
through a bidirectional processor I/O bit with one wire.

) control line].On

control line, the

is returned high. The

line is high

This is possible because the DI input is only ‘‘looked-at’’
during the MUX addressing interval while the DO line is
still in a high impedance state.

3.0 REFERENCE CONSIDERATIONS

The V
divider string and capacitor array used for the successive

IN pin on these converters is the top of a resistor

REF

approximation conversion. The voltage applied to this refer­ence input defines the voltage span of the analog input (the
difference between V
256 possible output codes apply). The reference source

IN(MAX)

and V

IN(MIN)

over which the

must be capable of driving the reference input resistance,
which can be as low as 1.3 kX.

For absolute accuracy, where the analog input varies be­tween specific voltage limits, the reference input must be
biased with a stable voltage source. The ADC08234 and the
ADC08238 provide the output of a 2.5V band-gap reference
at V

OUT. This voltage does not vary appreciably with

REF

temperature, supply voltage, or load current (see Reference
Characteristics in the Electrical Characteristics tables) and
can be tied directly to V
to 2.5V. This output can also be used to bias external cir-

IN for an analog input span of 0V

REF

cuits and can therefore be used as the reference in ratio­metric applications. Bypassing V
pacitor is recommended.

OUT with a 100 mF ca-

REF

For the ADC08231, the output of the on-board reference is
internally tied to the reference input. Consequently, the ana­log input span for this device is set at 0V to 2.5V. The pin
V

C is provided for bypassing purposes and biasing ex-

REF

ternal circuits as suggested above.

The maximum value of the reference is limited to the V
supply voltage. The minimum value, however, can be quite

CC

small (see Typical Performance Characteristics) to allow di­rect conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
noise pickup, circuit layout and system error voltage sourc­es when operating with a reduced span due to the in­creased sensitivity of the converter (1 LSB equals V

256).

REF/

a) Ratiometric

TL/H/11015– 18

FIGURE 2. Reference Examples

16

b) Absolute

TL/H/11015– 19

Functional Description (Continued)

4.0 THE ANALOG INPUTS

The most important feature of these converters is that they
can be located right at the analog signal source and through
just a few wires can communicate with a controlling proces­sor with a highly noise immune serial bit stream. This in itself
greatly minimizes circuitry to maintain analog signal accura­cy which otherwise is most susceptible to noise pickup.
However, a few words are in order with regard to the analog
inputs should the input be noisy to begin with or possibly
riding on a large common-mode voltage.

The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected ‘‘
(60 Hz is most typical). The time interval between sampling

a

the ‘‘

’’ input and then the ‘‘b’’ input is (/2 of a clock peri­od. The change in the common-mode voltage during this
short time interval can cause conversion errors. For a sinus­oidal common-mode signal this error is:

where fCMis the frequency of the common-mode signal,

V

PEAK

and f

CLK

For a 60Hz common-mode signal to generate a (/4 LSB er­ror (&5mV) with the converter running at 250kHz, its peak
value would have to be 6.63V which would be larger than
allowed as it exceeds the maximum analog input limits.

Source resistance limitation is important with regard to the
DC leakage currents of the input multiplexer. While operat­ing near or at maximum speed, bypass capacitors should
not be used if the source resistance is greater than 1kX.
The worst-case leakage current of
will create a 1mV input error with a 1kX source resistance.
An op amp RC active low pass filter can provide both im­pedance buffering and noise filtering should a high imped­ance signal source be required.

5.0 OPTIONAL ADJUSTMENTS

5.1 Zero Error

The zero of the A/D does not require adjustment. If the
minimum analog input voltage value, V
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing any V
utilizes the differential mode operation of the A/D.

a

’’ and ‘‘b’’ inputs for a conversion

V

(max)eV

error

is its peak voltage value

is the A/D clock frequency.

(b) input at this V

IN

PEAK

(2qfCM)

g

0.5

f

#

J

CLK

1mA over temperature

, is not ground

IN(MIN)

value. This

IN(MIN)

The zero error of the A/D converter relates to the location
of the first riser of the transfer function and can be mea­sured by grounding the V
magnitude positive voltage to the V
is the difference between the actual DC input voltage which
is necessary to just cause an output digital code transition
from 0000 0000 to 0000 0001 and the ideal (/2 LSB value

e

((/2 LSB

5.2 Full Scale

A full-scale adjustment can be made by applying a differen­tial input voltage which is 1(/2 LSB down from the desired
analog full-scale voltage range and then adjusting the mag­nitude of the V
just changing from 1111 1110 to 1111 1111 (See figure enti­tled ‘‘Span Adjust; 0V
with the ADC08234 and ADC08238. (The reference is inter­nally connected to V

5.3 Adjusting for an Arbitrary Analog Input
Voltage Range

If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input sig­nal which does not go to ground), this new zero reference
should be properly adjusted first. A V
equals this desired zero reference plus (/2 LSB (where the
LSB is calculated for the desired analog span, using 1 LSB

e

the zero reference voltage at the corresponding ‘‘
should then be adjusted to just obtain the 00
code transition.

The full-scale adjustment should be made[with the proper
V

IN

input which is given by:

where:

and

The V
code change from FE
justment procedure.

9.8mV for V

IN input for a digital output code which is

REF

analog span/256) is applied to selected ‘‘a’’ input and

(b) voltage applied]by forcing a voltage to the VIN(a)

V

(a)fsadjeV

IN

e

V

the high end of the analog input range

MAX

e

V

the low end (the offset zero) of the analog range.

MIN

(Both are ground referenced.)

IN (or VCC) voltage is then adjusted to provide a

REF

(b) input and applying a small

IN

e

REF

s

V

IN

IN of the ADC08231).

REF

b

1.5

MAX

to FF

HEX

(a) input. Zero error

IN

5.000VDC).

s

3V’’). This is possible only

(a) voltage which

IN

b

(V

MAX

256

Ð

. This completes the ad-

HEX

b

’’ input

to 01

HEX

V

MIN

HEX

)

(

17

Applications

A ‘‘Stand-Alone’’ Hook-Up for ADC08238 Evaluation

*Pinouts shown for ADC08238.

For all other products tie to pin functions as shown.

Low-Cost Remote Temperature Sensor

TL/H/11015– 21

18

Applications (Continued)

Protecting the Input

Diodes are 1N914

Operating with Ratiometric Transducers

*VIN(b)e0.15 V
15% of V

REF

s

REF

s

V

85% of V

XDR

REF

Span Adjust; 0VsV

TL/H/11015– 22

TL/H/11015– 23

s

3V

IN

TL/H/11015– 24

19

Applications (Continued)

Zero-Shift and Span Adjust: 2V

s

s

V

5V

IN

TL/H/11015– 25

20

Physical Dimensions inches (millimeters)

Order Number ADC08231BIWM, ADC08231CIWM,

ADC08234BIWM or ADC08234CIWM

NS Package Number M14B

Order Number ADC08238BIWM or ADC08238CIWM

NS Package Number M20B

21

Physical Dimensions inches (millimeters) (Continued)

TSSOP Molded Package

Order Number ADC08234CIMF

NS Package Number MTB24

Order Number ADC08231BIN or ADC08231CIN

NS Package Number N08E

22

Physical Dimensions inches (millimeters) (Continued)

Molded Dual-In-Line Package (N)

Order Number ADC08234BIN or ADC08234CIN

NS Package Number N14A

23

Physical Dimensions inches (millimeters) (Continued)

with MUX, Reference, and Track/Hold

Molded Dual-In-Line Package (N)

Order Number ADC08238CIN or ADC08238BIN

NS Package Number N20A

LIFE SUPPORT POLICY

ADC08231/ADC08234/ADC08238 8-Bit 2 ms Serial I/O A/D Converters

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

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Corporation GmbH Japan Ltd. Hong Kong Ltd. Do Brazil Ltda. (Australia) Pty, Ltd.

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