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ADC0820
8-Bit High Speed µP Compatible A/D Converter with
Track/Hold Function
ADC0820 8-Bit High Speed µP Compatible A/D Converter with Track/Hold Function
June 1999
General Description
By using a half-flash conversion technique, the 8-bit
ADC0820 CMOS A/D offers a 1.5 µs conversion time and
dissipates only 75 mW of power. The half-flash technique
consists of 32 comparators, a most significant 4-bitADCand
a least significant 4-bit ADC.
The input to the ADC0820 is tracked and held by the input
sampling circuitry eliminating the need for an external
sample-and-hold for signals moving at less than 100 mV/µs.
For ease of interface to microprocessors, the ADC0820 has
been designed to appear as a memory location or I/O port
without the need for external interfacing logic.
Key Specifications
n Resolution 8 Bits
n Conversion Time 2.5 µs Max (RD Mode)
1.5 µs Max (WR-RD Mode)
n Low Power 75 mW Max
n Total Unadjusted
Error
1
±
⁄2LSB and±1 LSB
Connection and Functional Diagrams
Dual-In-Line, Small Outline
and SSOP Packages
Features
n Built-in track-and-hold function
n No missing codes
n No external clocking
n Single supply —5 V
n Easy interface to all microprocessors, or operates
stand-alone
n Latched TRI-STATE
n Logic inputs and outputs meet both MOS and T
voltage level specifications
n Operates ratiometrically or with any reference value
equal to or less than V
n 0V to 5V analog input voltage range with single 5V
supply
n No zero or full-scale adjust required
n Overflow output available for cascading
n 0.3" standard width 20-pin DIP
n 20-pin molded chip carrier package
n 20-pin small outline package
n 20-pin shrink small outline package (SSOP)
DC
®
output
CC
Molded Chip Carrier
Package
2
L
DS005501-1
Top View
TRI-STATE®is a registeredtrademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS005501 www.national.com
DS005501-33
Connection and Functional Diagrams (Continued)
DS005501-2
FIGURE 1.
Ordering Information
Part Number Total Package Temperature
Unadjusted Error Range
ADC0820BCV V20A— Molded Chip Carrier 0˚C to +70˚C
ADC0820BCWM
ADC0820BCN N20A—Molded DIP 0˚C to +70˚C
ADC0820CCJ
ADC0820CCWM M20B— Wide Body Small Outline 0˚C to +70˚C
ADC0820CIWM M20B— Wide Body Small Outline −40˚C to +85˚C
ADC0820CCN N20A— Molded DIP 0˚C to +70˚C
1
±
⁄2LSB M20B— Wide Body Small Outline 0˚C to +70˚C
J20A— Cerdip −40˚C to +85˚C
±
1 LSB
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Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
Logic Control Inputs −0.2V to V
Voltage at Other Inputs and Output −0.2V to V
Storage Temperature Range −65˚C to +150˚C
Package Dissipation at T
Input Current at Any Pin (Note 5) 1 mA
Package Input Current (Note 5) 4 mA
ESD Susceptability (Note 9) 1200V
Lead Temp. (Soldering, 10 sec.)
Dual-In-Line Package (plastic) 260˚C
) 10V
CC
=
25˚C 875 mW
A
CC
CC
+0.2V
+0.2V
Dual-In-Line Package (ceramic) 300˚C
Surface Mount Package
Vapor Phase (60 sec.) 215˚C
Infrared (15 sec.) 220˚C
Operating Ratings (Notes 1, 2)
Temperature Range T
ADC0820CCJ −40˚C≤TA≤+85˚C
ADC0820CIWM −40˚C≤T
ADC0820BCN, ADC0820CCN 0˚C≤T
ADC0820BCV 0˚C≤T
ADC0820BCWM, ADC0820CCWM 0˚C≤T
Range 4.5V to 8V
V
CC
MIN≤TA≤TMAX
≤+85˚C
A
A
A
A
≤70˚C
≤70˚C
≤70˚C
Converter Characteristics
The following specifications apply for RD mode (pin 7=0), V
fied. Boldface limits apply from T
MIN
to T
MAX
; all other limits T
Parameter Conditions ADC0820BCN, ADC0820CCN Limit
(Note 6) Limit Limit (Note 6) Limit Limit
Resolution 8 8 8 Bits
Total Unadjusted ADC0820BCN, BCWM
Error ADC0820CCJ
(Note 3) ADC0820CCN, CCWM, CIWM,
ADC0820CCMSA
Minimum Reference 2.3 1.00 2.3 1.2 kΩ
Resistance
Maximum Reference 2.3 6 2.3 5.3 6 kΩ
Resistance
Maximum V
(+) V
REF
Input Voltage
Minimum V
(−) GND GND GND V
REF
Input Voltage
Minimum V
(+) V
REF
Input Voltage
Maximum V
(−) V
REF
Input Voltage
Maximum V
Input VCC+0.1 VCC+0.1 VCC+0.1 V
IN
Voltage
Minimum V
Input GND−0.1 GND−0.1 GND−0.1 V
IN
Voltage
Maximum Analog CS=V
Input Leakage V
Current V
Power Supply V
CC
=
V
IN
CC
=
GND −3 −0.3 −3 µA
IN
=
±
%
5
5V
CC
±
Sensitivity
=
CC
5V, V
=
A
REF
=
T
25˚C.
j
(+)=5V,and V
(−)=GND unless otherwise speci-
REF
ADC0820CCJ ADC0820BCV, ADC0820BCWM
ADC0820CCWM, ADC0820CIWM
Typ Tested Design Typ Tested Design
(Note 7) (Note 8) (Note 7) (Note 8)
1
±
⁄
±
1 LSB
CC
(−) V
REF
(+) V
REF
2
±
1
±
1
V
CC
(−) V
REF
(+) V
REF
1
±
⁄
±
1 LSB
±
1 LSB
V
CC
REF
REF
3 0.3 3 µA
1/16
1
±
⁄
4
±
1/16
1
±
⁄
4
1
±
⁄
Units
2
(−) V
(+) V
4
LSB
LSB
V
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DC Electrical Characteristics
The following specifications apply for V
=
limits T
V
IN(1)
Input Voltage Mode 3.5 3.5 3.5 V
V
IN(0)
Input Voltage Mode 1.5 1.5 1.5 V
, Logical “1” V
I
IN(1)
Input Current V
, Logical “0” V
I
IN(0)
Input Current Mode
V
OUT(1)
Output Voltage DB0–DB7, OFL , INT
V
OUT(0)
Output Voltage DB0–DB7, OFL , INT , RDY
I
, TRI-STATE V
OUT
Output Current V
I
SOURCE
Source Current INT
, Output Sink V
I
SINK
Current INT , RDY
ICC, Supply Current CS=WR=RD=0 7.5 15 7.5 13 15 mA
=
T
25˚C.
A
J
Parameter Conditions ADC0820BCN, ADC0820CCN Limit
=
, Logical “1” V
, Logical “0” V
, Logical “1” V
, Logical “0” V
, Output V
5.25V CS , WR , RD
CC
=
4.75V CS , WR , RD
CC
=
5V; CS , RD
IN(1)
=
5V; WR
IN(1)
=
5V; Mode 50 200 50 170 200 µA
V
IN(1)
=
0V;CS,RD,WR,
IN(0)
=
4.75V, I
CC
V
CC
DB0–DB7, OFL , INT
CC
OUT
OUT
OUT
OUT
OUT
=
4.75V, I
OUT
=
4.75V, I
OUT
=
5V; DB0–DB7, RDY 0.1 3 0.1 0.3 3 µA
=
0V; DB0–DB7, RDY −0.1 −3 −0.1 −0.3 −3 µA
=
0V; DB0–DB7, OFL
=
5V; DB0–DB7, OFL ,
=
5V, unless otherwise specified. Boldface limits apply from T
CC
ADC0820CCJ ADC0820BCV, ADC0820BCWM
Typ Tested Design Typ Tested Design
(Note 6) Limit Limit (Note 6) Limit Limit
0.005 1 0.005 1 µA
−0.005 −1 −0.005 −1 µA
=
−360 µA; 2.4 2.8 2.4 V
=
−10 µA; 4.5 4.6 4.5 V
=
1.6 mA; 0.4 0.34 0.4 V
(Note 7) (Note 8) (Note 7) (Note 8)
2.0 2.0 2.0 V
0.8 0.8 0.8 V
0.1 3 0.1 0.3 3 µA
−12 −6 −12 −7.2 −6 mA
−9 −4.0 −9 −5.3 −4.0 mA
14 7 14 8.4 7 mA
ADC0820CCWM, ADC0820CIWM
MIN
to T
MAX
; all other
Units
AC Electrical Characteristics
=
=
The following specifications apply for V
fied.
CC
Parameter Conditions (Note 6) Limit Limit Units
, Conversion Time for RD
t
CRD
Mode
t
, Access Time (Delay from Pin 7=0,
ACC0
Pin 7=0,
Falling Edge of RD to Output
Valid)
t
, Conversion Time for Pin 7=VCC;t
CWR-RD
WR-RD Mode t
RD
tWR, Write Time Min Pin 7=VCC;
Max (Note 4) See Graph 50 µs
t
, Read Time Min Pin 7=VCC;
RD
(Note 4) See Graph
t
, Access Time (Delay from Pin 7=VCC,t
ACC1
Falling Edge of RD to Output
Valid)
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C
L
C
L
=
5V, t
t
20 ns, V
r
f
Figure 2
Figure 2
=
600 ns, 1.52 µs
600 ns;
WR
Figures 3, 4
=
Figures 3, 4
Figures 3, 4
<
tI;
Figure 3
=
15 pF 190 280 ns
=
100 pF 210 320 ns
RD
(+)=5V, V
REF
(−)=0V and T
REF
=
25˚C unless otherwise speci-
A
Typ Tested Design
(Note 7) (Note 8)
1.6 2.5 µs
t
+20 t
CRD
CRD
600 ns
600 ns
+50 ns
AC Electrical Characteristics (Continued)
=
=
The following specifications apply for V
fied.
CC
5V, t
r
=
t
20 ns, V
f
REF
(+)=5V, V
(−)=0V and T
REF
Typ Tested Design
Parameter Conditions (Note 6) Limit Limit Units
, Access Time (Delay from
t
ACC2
Falling Edge of RD to Output
Valid)
t
, Access Time (Delay from
ACC3
Rising Edge of RDY to Output
Pin 7=V
=
C
15 pF 70 120 ns
L
=
C
100 pF 90 150 ns
L
R
PULLUP
CC,tRD
=
1k and C
>
tI;
Figure 4
=
15 pF 30 ns
L
Valid)
, Internal Comparison Time Pin 7=VCC;
t
I
t
, TRI-STATE Control R
1H,t0H
C
L
L
Figures 4, 5
=
50 pF
=
=
1k, C
10 pF 100 200 ns
L
800 1300 ns
(Delay from Rising Edge of RD to
Hi-Z State)
t
, Delay from Rising Edge of Pin 7=VCC,C
INTL
WR to Falling Edge of INT
t
, Delay from Rising Edge of
INTH
RD to Rising Edge of INT
t
, Delay from Rising Edge of
INTHWR
>
t
RD
<
t
RD
Figures 2, 3, 4
=
C
50 pFc
L
Figure 5
tI;
tI;
=
50 pF
L
Figure 4
Figure 3
tRD+200 tRD+290 ns
125 225 ns
=
,C
50 pF 175 270 ns
L
WR to Rising Edge of INT
t
, Delay from CS to RDY
RDY
t
, Delay from INT to Output Valid
ID
t
, Delay from RD to INT Pin 7=VCC,t
RI
Figure 2
Figure 5
=
,C
50 pF, Pin 7=0 50 100 ns
L
20 50 ns
<
t
RD
I
200 290 ns
Figure 3
tP, Delay from End of Conversion
Figures 2, 3, 4, 5
to Next Conversion (Note 4) See Graph
Slew Rate, Tracking 0.1 V/µs
C
, Analog Input Capacitance 45 pF
VIN
C
, Logic Output Capacitance 5 pF
OUT
C
, Logic Input Capacitance 5 pF
IN
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified.
Note 3: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 4: Accuracy may degrade if t
Note 5: When the input voltage (V
1 mA or less. The 4 mA package input current limits the number of pins that can exceed the power supply boundaries witha1mAcurrent limit to four.
Note 6: Typicals are at 25˚C and represent most likely parametric norm.
Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: Design limits are guaranteed but not 100%tested. These limits are not used to calculate outgoing quality levels.
Note 9: Human body model, 100 pF discharaged through a 1.5 kΩ resistor.
or tRDis shorter than the minimum value specified. See Accuracy vs tWRand Accuracy vs tRDgraphs.
WR
) at any pin exceeds the power supply rails (V
IN
<
>
V−or V
IN
V+) the absolute value of current at that pin should be limited to
IN
=
25˚C unless otherwise speci-
A
(Note 7) (Note 8)
t
I
500 ns
ns
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TRI-STATE Test Circuits and Waveforms
t
1H
Timing Diagrams
DS005501-3
t
0H
DS005501-5
=
t
20 ns
r
=
t
20 ns
r
DS005501-4
DS005501-6
Note: On power-up the state of INT can be high or low.
FIGURE 2. RD Mode (Pin 7 is Low)
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DS005501-7
Timing Diagrams (Continued)
FIGURE 3. WR-RD Mode (Pin 7 is High and t
DS005501-8
<
RD
tI)
FIGURE 4. WR-RD Mode (Pin 7 is High and t
FIGURE 5. WR-RD Mode (Pin 7 is High)
Stand-Alone Operation
DS005501-9
>
RD
DS005501-10
tI)
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