National Semiconductor ADC08061, ADC08062 Technical data
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ADC08061/ADC08062
500 ns A/D Converter with S/H Function and Input
Multiplexer
ADC08061/ADC08062 500 ns A/D Converter with S/H Function and Input Multiplexer
June 1999
General Description
Using a patented multi-step A/D conversion technique, the
8-bit ADC08061 and ADC08062 CMOS ADCs offer 500 ns
(typ) conversion time, internal sample-and-hold (S/H), and
dissipate only 125 mW of power. The ADC08062 has a
two-channel multiplexer. The ADC08061/2 family performs
an 8-bit conversion using a 2-bit voltage estimator that generates the 2 MSBs andtwo low-resolution (3-bit) flashes that
generate the 6 LSBs.
Input track-and-hold circuitry eliminates the need for an external sample-and-hold. The ADC08061/2 family performs
accurate conversions of full-scale input signals that have a
frequency range of DC to 300 kHz (full-power bandwidth)
without need of an external S/H.
The digital interface has been designed to ease connection
to microprocessors and allows theparts to be I/O or memory
mapped.
Block Diagram
Key Specifications
n Resolution 8 bits
n Conversion Time 560 ns max (WR-RD Mode)
n Full Power Bandwidth 300 kHz
n Throughput rate 1.5 MHz
n Power Dissipation 100 mW max
n Total Unadjusted Error
1
±
⁄2LSB and±1 LSB
Features
n 1 or 2 input channels
n No external clock required
n Analog input voltage range from GND to V
n Overflow output available for cascading (ADC08061)
n ADC08061 pin-compatible with the industry standard
ADC0820
+
Applications
n Mobile telecommunications
n Hard disk drives
n Instrumentation
n High-speed data acquisition systems
* ADC08061
*
ADC08062
*
TRI-STATE®is a registered trademark of NationalSemiconductor Corporation.
© 1999 National Semiconductor Corporation DS011086 www.national.com
DS011086-1
Connection Diagrams
DS011086-14
Dual-In-Line and Wide-Body
Small-Outline
Packages N20A or M20B
Ordering Information
Industrial (−40˚C ≤ TA≤ 85˚C) Package
ADC08061BIN, ADC08062BIN N20A
ADC08061CIWM, ADC08062CIWM M20B
Pin Description
VIN,
V
IN1–8
DB0–DB7 TRI-STATE data outputs— bit 0 (LSB) through
WR /RDY
: RD Mode (Logic low applied to MODE pin)
MODE Mode: Mode (RD or WR-RD) selection
RD
These are analog inputs. The input range is
GND–50 mV ≤ V
ADC08061 has a single input (V
ADC08062 has a two-channel multiplexer
(V
).
IN1–2
≤ V++50mV.The
INPUT
) and the
IN
bit 7 (MSB).
WR-RD Mode (Logic high appliedto MODEpin)
WR: With CS low, the conversion is started on
the falling edge of WR. The digital result will be
strobed into the output latch at the end of conversion (see
Figures 2, 3, 4
).
RDY: This is an open drain output (no internal
pull-up device). RDY will go low after the falling
edge of CS and return highat the endof conversion.
input— This pin is pulled to a logic low through
an internal 50 µA current sink when left unconnected.
RD Mode is selected if the MODE pin is left unconnected or externally forced low. A complete
conversion is accomplished by pulling RD low
until output data appears.
WR-RD Mode is selected when a high is applied
to the MODE pin. A conversion starts with the
WR signal’s rising edge and then using RD to
access the data.
WR-RD Mode (logic high on the MODE pin)
This is the active low Read input. With a logic
low applied to the CS pin, the TRI-STATE data
outputs (DB0–DB7) will be activated when RD
goes low (
Figures 2, 3, 4
).
RD Mode (logic low on the MODE pin)
DS011086-15
Dual-In-Line and Wide-Body
Small-Outline
Packages N20A or M20B
With CS low, a conversion starts on the falling
edge of RD. Output data appears on DB0–DB7
INT
at the end of conversion(see
This is an active low output that indicates that a
Figures 1, 5
).
conversion is complete and the data is in the
output latch. INT is reset by the rising edge of
RD.
GND This is the power supplyground pin. The ground
pin should be connectedto a “clean” ground reference point.
V
,
REF−
V
REF+
These are the reference voltage inputs. They
may be placed at any voltage between GND −
50 mV and V
greater than V
equal to V
and an input voltage greater than V
LSB produces an output code of 255.
For the ADC08062, an input voltage on any unselected input that exceeds V
+
+50mV,butV
. Ideally, an input voltage
REF−
produces an output code of 0,
REF−
REF+
+
by more than
must be
REF+
− 1.5
100 mV or is below GND by more than 100 mV
will create errors in a selected channel that is
operating within proper operating conditions.
CS
This is the active low Chip Select input. A logic
low signal applied to this input pin enables the
RD and WR inputs. Internally, the CS signal is
ORed with RD and WR signals.
OFL Overflow Output. If the analog input is higher
than V
of conversion. It can be used when cascading
−1⁄2LSB, OFL will be low at the end
REF+
two ADC08061s to achieve higher resolution (9
bits). This output is always active and does not
go into TRI-STATEas DB0–DB7 do. When OFL
is set, all data outputs remain high when the
ADC08061’s output data is read.
NC No connection.
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Pin Description (Continued)
A0 This logic input is used to select one of the
V+Positive power supply voltage input. Nominal operating
ADC08062’s input multiplexer channels. A channel is selected as shown in the table below.
ADC08062 Channel
A0
0V
1V
IN1
IN2
supply voltage is +5V. The supply pin should be bypassed with a 10 µFbead tantalumin parallelwith a0.1
ceramic capacitor. Lead length should be as short as
possible.
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Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
Logic Control Inputs −0.3V to V
Voltage at Other lInputs and Outputs −0.3V to V
Input Current at Any Pin (Note 3) 5 mA
Package Input Current (Note 3) 20 mA
Power Dissipation (Note 4)
J Package 875 mW
N Package 875 mW
WM Package 875 mW
Storage Temperature −65˚C to +150˚C
+
)6V
+
+ 0.3V
+
+ 0.3V
Lead Temperature (Note 5)
J Package (Soldering, 10 sec.) +300˚C
N Package (Soldering, 10 sec.) +260˚C
WM Package
(Vapor Phase, 60 sec.) +215˚C
WM Package (Infrared, 15 sec.) +220˚C
ESD Susceptibility (Note 6) 2 kV
Operating Ratings (Notes 1, 2)
Temperature Range T
ADC08061/2BIN,
ADC08061/2CIWM −40˚C ≤ T
Supply Voltage, (V
+
) 4.5V to 5.5V
MIN
≤ TA≤ T
≤ 85˚C
A
MAX
Converter Characteristics
The following specifications apply for RD Mode, V
face limits apply for T
Symbol Parameter Conditions Typical Limits Units
INL Integral Non Linearity ADC08061/2BIN
TUE Total Unadjusted Error ADC08061/2BIN
=
=
T
A
to T
T
J
MIN
+
=
5V, V
; all other limits T
MAX
ADC08061/2CIWM
ADC08061/2CIWM
REF+
=
5V, and V
=
T
A
=
GND unless otherwise specified. Bold-
REF−
=
25˚C.
J
(Note 7) (Note 8)
1
±
⁄
2
±
1 LSB (max)
1
±
⁄
2
±
1 LSB (max)
(Limit)
LSB (max)
LSB (max)
Missing Codes 0 Bits (max)
Reference Input Resistance 700 500 Ω(min)
700 1250 Ω (max)
V
REF+
V
REF−
V
IN
Positive Reference V
Input Voltage V
REF−
+
V (min)
V (max)
Negative Reference GND V (min)
Input Voltage V
REF+
V (max)
Analog (Note 10) GND − 0.1 V (min)
Input Voltage V
+
+ 0.1 V (max)
On Channel Input On Channel Input=5V, −0.4 −20 µA (max)
Current Off Channel Input=0V (Note 11)
On Channel Input=0V, −0.4 −20 µA (max)
Off Channel Input=5V (Note 11)
PSS Power Supply Sensitivity V
+
=
±
5%,V
5V
REF
=
4.75V
±
1/16
1
±
⁄
2
LSB (max)
All Codes Tested
Effective Bits 7.8 Bits
Full-Power Bandwidth 300 kHz
THD Total Harmonic Distortion 0.5
%
S/N Signal-to-Noise Ratio 50 dB
IMD Intermodulation Distortion 50 dB
AC Electrical Characteristics
The following specifications apply for V
face limits apply for T
Symbol Parameter Condition
t
WR
t
RD
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Write Time Mode Pin to V+; 100 100 ns (min)
Read Time (Time from Falling Edge Mode Pin to V+;(
of WR to Falling Edge of RD )
=
T
A
J
+
=
=
MIN
to T
5V, t
MAX
=
T
=
t
10 ns, V
r
f
; all other limits T
Figures 2, 3, 4
(
)
=
5V, V
REF+
=
=
T
A
J
Figure 2
) 350 350 ns (min)
25˚C.
=
0V unless otherwise specified. Bold-
REF−
Typical
(Note 7)
Limits
(Note 8)
Units
(Limit)
AC Electrical Characteristics (Continued)
+
=
=
The following specifications apply for V
face limits apply for T
=
=
T
A
T
J
MIN
to T
5V, t
MAX
Symbol Parameter Condition
t
RDW
t
CONV
t
CRD
t
ACCO
RD Width Mode Pin to GND; (
WR -RD Mode Conversion Time Mode Pin to V+;(
(t
WR+tRD+tACC1
)
RD Mode Conversion Time Mode Pin to GND; (
Access Time (Delay from Falling CL≤ 100 pF 640 900 ns (max)
Edge of RD to Output Valid)
t
ACC1
Access Time (Delay from CL≤ 10 pF 45 110 ns (max)
Falling Edge C
of RD to Output Valid)
t
ACC2
Access Time (Delay from CL≤ 10 pF 25 55 ns (max)
Falling Edge C
of RD to Output Valid)
t
0H
TRI-STATE®Control (Delay from R
Rising Edge of RD to HI-Z State)
t
1H
TRI-STATE Control (Delay from R
Rising Edge of RD to HI-Z State)
t
INTL
Delay from Rising Edge of (
WR to Falling Edge of INT
t
INTH
Delay from Rising Edge of C
RD to Rising Edge of INT
t
INTH
Delay from Rising Edge of C
WR to Rising Edge of INT
t
RDY
t
ID
t
RI
t
N
Delay from CS to RDY Mode Pin=0V, C
Delay from INT to Output Valid R
Delay from RD to INT Mode Pin=V+,tRD≤ t
Time between End of RD (
and Start of New Conversion
t
AH
t
AS
t
CSS
t
CSH
C
C
C
Channel Address Hold Time (
Channel Address Setup Time (
CS Setup Time (
CS Hold Time (
Analog Input Capacitance 25 pF
VIN
Logic Output Capacitance 5 pF
OUT
Logic Input Capacitance 5 pF
IN
=
t
10 ns, V
r
f
; all other limits T
Figure 2
Mode Pin to GND; (
=
100 pF 50
L
Mode Pin to V+,tRD≤ t
(
Figure 2
)
=
100 pF 30
L
>
t
t
;(
RD
L
L
Figures 3, 4
Mode Pin=V+,C
L
2b, and 4
L
R
L
L
Figure 4
(
Figure 3
(
Figures 3, 4
INTL
=
=
3kΩ,C
3kΩ,C
=
10 pF 30 60 ns (max)
L
=
10 pF 30 60 ns (max)
L
) 520 690 ns (max)
=
50 pF; (
L
Figures 1, 2, 3, 4
)
=
Figure 4
50 pF; (
=
3kΩ(
=
3kΩ,C
L
Figure 1
=
100 pF; 0 15 ns (max)
L
)
)
Figures 1, 2, 3, 4, 5
Figures 1, 2, 3, 4, 5
Figures 1, 2, 3, 4, 5
Figures 1, 2, 3, 4, 5
Figures 1, 2, 3, 4, 5
=
5V, V
REF+
=
=
T
A
J
Figure 5
) 200 250 ns (min)
25˚C.
=
0V unless otherwise specified. Bold-
REF−
Typical
(Note 7)
Limits
(Note 8)
Units
(Limit)
400 400 ns (max)
) 500 560 ns (max)
Figure 1
) 655 900 ns (max)
Figure 1
)
INTL
)
=
50 pF
)50 95 ns (max)
)4595 ns (max)
=
50 pF, 25 45 ns (max)
)
; 60 115 ns (max)
INTL
)5050 ns (min)
)1060 ns (min)
)00ns (max)
)00ns (max)
)00ns (min)
DC Electrical Characteristics
The following specifications apply for V
all other limits T
Symbol Parameter Conditions Typical Limits Units
V
IH
=
=
T
25˚C.
A
J
Logic “1” Input Voltage V
+
=
5V unless otherwise specified. Boldface limits apply for T
(Note 7) (Note 8)
+
=
5.5V
=
=
T
A
to T
T
J
MIN
(Limit)
Mode Pin 3.5 V (min)
ADC08062
CS, WR, RD, A0 Pins
2.2 V (min)
ADC08061
CS, WR, RD Pins
2.0 V (min)
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MAX
;
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