National Semiconductor ADC0806 Technical data

February 8, 2008

ADC08060
8-Bit, 20 MSPS to 60 MSPS, 1.3 mW/MSPS A/D Converter
with Internal Sample-and-Hold

ADC08060 8-Bit, 20 MSPS to 60 MSPS, 1.3 mW/MSPS A/D Converter with Internal

Sample-and-Hold

General Description

The ADC08060 is a low-power, 8-bit, monolithic analog-to­digital converter with an on-chip track-and-hold circuit. Opti­mized for low cost, low power, small size and ease of use, this
product operates at conversion rates of 20 MSPS to 70 MSPS
with outstanding dynamic performance over its full operating
range while consuming just 1.3 mW per MHz of clock fre­quency. That's just 78 mW of power at 60 MSPS. Raising the
PD pin puts the ADC08060 into a Power Down mode where
it consumes just 1 mW.

The unique architecture achieves 7.5 Effective Bits with
25 MHz input frequency. The excellent DC and AC charac­teristics of this device, together with its low power consump­tion and single +3V supply operation, make it ideally suited
for many imaging and communications applications, including
use in portable equipment. Furthermore, the ADC08060 is
resistant to latch-up and the outputs are short-circuit proof.
The top and bottom of the ADC08060's reference ladder are
available for connections, enabling a wide range of input pos­sibilities. The digital outputs are TTL/CMOS compatible with
a separate output power supply pin to support interfacing with
3V or 2.5V logic. The output coding is straight binary and the
digital inputs (CLK and PD) are TTL/CMOS compatible.

The ADC08060 is offered in a 24-lead plastic package
(TSSOP) and is specified over the industrial temperature
range of −40°C to +85°C.

Features

Single-ended input

■

Internal sample-and-hold function

■

Low voltage (single +3V) operation

■

Small package

■

Power-down feature

■

Key Specifications

Resolution 8 bits

■

Maximum sampling frequency 60 MSPS (min)

■

DNL 0.4 LSB (typ)

■

ENOB 7.5 bits (typ) at fIN = 25 MHz

■

THD −60 dB (typ)

■

No missing codes Guaranteed

■

Power Consumption

■

Operating 1.3 mW/MSPS (typ)

—

■

Power Down Mode 1 mW (typ)

—

Applications

Digital imaging systems

■

Communication systems

■

Portable instrumentation

■

Viterbi decoders

■

Set-top boxes

■

Pin Configuration

20006201

© 2008 National Semiconductor Corporation 200062 www.national.com

Ordering Information

Order Number Temperature Range Package

ADC08060

ADC08060CIMT

ADC08060CIMTX

Block Diagram

−40°C ≤ TA ≤ +85°C

−40°C ≤ TA ≤ +85°C

TSSOP

TSSOP (tape and reel)

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

10

6

3

9

V

IN

V

RT

V

RM

V

RB

Analog signal input. Conversion range is VRB to VRT.

Analog Input that is the high (top) side of the reference ladder
of the ADC. Nominal range is 1.0V to VA. Voltage on VRT and
VRB inputs define the VIN conversion range. Bypass well. See
Section 2.0 for more information.

Mid-point of the reference ladder. This pin should be
bypassed to a clean, quiet point in the analog ground plane
with a 0.1 µF capacitor.

Analog Input that is the low side (bottom) of the reference
ladder of the ADC. Nominal range is 0.0V to (VRT – 1.0V).
Voltage on VRT and VRB inputs define the VIN conversion
range. Bypass well. See Section 2.0 for more information.

20006202

www.national.com 2

Pin No. Symbol Equivalent Circuit Description

Power Down input. When this pin is high, the converter is in

23 PD

the Power Down mode and the data output pins hold the last
conversion result.

ADC08060

24 CLK

13 thru 16

and

19 thru 22

7

D0–D7

VIN GND

CMOS/TTL compatible digital clock Input. VIN is sampled on
the falling edge of CLK input.

Conversion data digital Output pins. D0 is the LSB, D7 is the
MSB. Valid data is output just after the rising edge of the CLK
input.

Reference ground for the single-ended analog input, VIN.

Positive analog supply pin. Connect to a clean, quiet voltage

1, 4, 12

V

A

source of +3V. VA should be bypassed with a 0.1 µF ceramic
chip capacitor for each pin, plus one 10 µF capacitor. See
Section 3.0 for more information.

18

DR V

D

Power supply for the output drivers. If connected to VA,
decouple well from VA.

17 DR GND The ground return for the output driver supply.

2, 5, 8, 11 AGND The ground return for the analog supply.

3 www.national.com

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/

ADC08060

Distributors for availability and specifications.

Supply Voltage (VA)

Driver Supply Voltage (DR VD) VA + 0.3V

Voltage on Any Input or Output Pin −0.3V to V

Reference Voltage (VRT, VRB) VA to AGND

CLK, OE Voltage Range −0.3V to

3.8V

A

Operating Ratings (Notes 1, 2)

Operating Temperature Range

Supply Voltage (VA)

Driver Supply Voltage (DR VD) +2.4V to V

Ground Difference |GND - DR GND| 0V to 300 mV
Upper Reference Voltage (VRT) 1.0V to (VA + 0.1V)

Lower Reference Voltage (VRB) 0V to (VRT − 1.0V)

VIN Voltage Range VRB to V

−40°C ≤ TA ≤ +85°C

+2.7V to +3.6V

(VA + 0.3V)

Digital Output Voltage (VOH, VOL) DR GND to DR V

D

Input Current at Any Pin (Note 3) ±25 mA
Package Input Current (Note 3) ±50 mA
Power Dissipation at TA = 25°C

ESD Susceptibility (Note 6)
Human Body Model
Machine Model

See (Note 5)

2500V

250V

Soldering Temperature, Infrared,
10 seconds (Note 7) 235°C

Storage Temperature −65°C to +150°C

Converter Electrical Characteristics

The following specifications apply for VA = DR VD = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, f
cycle. Boldface limits apply for TJ = T

Symbol Parameter Conditions

MIN

to T

: all other limits TA = 25°C (Notes 4, 8, 9)

MAX

Typical

(Note 10)

DC ACCURACY

INL Integral Non-Linearity ±0.5 ±1.3 LSB (max)

DNL Differential Non-Linearity ±0.4

Missing Codes 0 (max)

FSE Full Scale Error 18 ±28 mV (max)

ZSE Zero Scale Offset Error 26 ±35 mV (max)

ANALOG INPUT AND REFERENCE CHARACTERISTICS

V

IN

C

IN

R

IN

Input Voltage

VIN Input Capacitance VIN = 0.75V +0.5 Vrms

RIN Input Resistance

1.6

(CLK LOW) 3 pF

(CLK HIGH) 4 pF

>1

BW Full Power Bandwidth 200 MHz

V

RT

V

RB

VRT - V

R

REF

I

REF

Top Reference Voltage

Bottom Reference Voltage

Reference Delta

RB

Reference Ladder Resistance

Reference Ladder Current

VRT to V

RB

1.9

0.3

1.6

220

7.3

= 60 MHz at 50% duty

CLK

Limits

(Note 10)

+1.0

LSB (max)

−0.9

V

RB

V

RT

V

A

1.0 V (min)

VRT − 1.0

0 V (min)

1.0 V (min)

2.3 V (max)

150

300

5.3 mA (min)

10.6 mA (max)

(Limits)

LSB (min)

V (max)

V (max)

V (max)

Ω (max)

A

RT

Units

V (min)

MΩ

Ω (min)

www.national.com 4

ADC08060

Symbol Parameter Conditions

CLK, PD DIGITAL INPUT CHARACTERISTICS

V

IH

V

IL

I

IH

I

IL

C

IN

Logical High Input Voltage

Logical Low Input Voltage

Logical High Input Current

Logical Low Input Current

Logic Input Capacitance 3 pF

DR VD = VA = 3.3V

DR VD = VA = 2.7V

VIH = DR VD = VA = 3.3V

VIL = 0V, DR VD = VA = 2.7V

DIGITAL OUTPUT CHARACTERISTICS

V

OH

V

OL

High Level Output Voltage

Low Level Output Voltage

VA = DR VD = 2.7V, IOH = −400 µA

VA = DR VD = 2.7V, IOL = 1.0 mA

DYNAMIC PERFORMANCE

fIN = 4.4 MHz, VIN = −0.25 dBFS

ENOB Effective Number of Bits

fIN = 10 MHz, VIN = −0.25 dBFS

fIN = 25 MHz, VIN = −0.25 dBFS

fIN = 29 MHz, VIN = −0.25 dBFS

fIN = 4.4 MHz, VIN = −0.25 dBFS

SINAD Signal-to-Noise & Distortion

fIN = 10 MHz, VIN = −0.25 dBFS

fIN = 25 MHz, VIN = −0.25 dBFS

fIN = 29 MHz, VIN = −0.25 dBFS

fIN = 4.4 MHz, VIN = −0.25 dBFS

SNR Signal-to-Noise Ratio

fIN = 10 MHz, VIN = −0.25 dBFS

fIN = 25 MHz, VIN = −0.25 dBFS

fIN = 29 MHz, VIN = −0.25 dBFS

fIN = 4.4 MHz, VIN = −0.25 dBFS

SFDR Spurious Free Dynamic Range

fIN = 10 MHz, VIN = −0.25 dBFS

fIN = 25 MHz, VIN = −0.25 dBFS

fIN = 29 MHz, VIN = −0.25 dBFS

fIN = 4.4 MHz, VIN = −0.25 dBFS

THD Total Harmonic Distortion

fIN = 10 MHz, VIN = −0.25 dBFS

fIN = 25 MHz, VIN = −0.25 dBFS

fIN = 29 MHz, VIN = −0.25 dBFS

fIN = 4.4 MHz, VIN = −0.25 dBFS

HD2 2nd Harmonic Distortion

fIN = 10 MHz, VIN = −0.25 dBFS

fIN = 25 MHz, VIN = −0.25 dBFS

fIN = 29 MHz, VIN = −0.25 dBFS

fIN = 4.4 MHz, VIN = −0.25 dBFS

HD3 3rd Harmonic Distortion

fIN = 10 MHz, VIN = −0.25 dBFS

fIN = 25 MHz, VIN = −0.25 dBFS

fIN = 29 MHz, VIN = −0.25 dBFS

IMD Intermodulation Distortion

f1 = 11 MHz, VIN = −6.25 dBFS
f2 = 12 MHz, VIN = −6.25 dBFS

POWER SUPPLY CHARACTERISTICS

I

A

DR I

Analog Supply Current

Output Driver Supply Current

D

DC Input 25 31 mA (max)

fIN = 10 MHz, VIN = −3 dBFS

DC Input 0.3 1 mA (max)

fIN = 10 MHz, VIN = 3 dBFS (Note )

Typical

(Note 10)

Limits

(Note 10)

(Limits)

2.0 V (min)

0.8 V (max)

10 nA

−50 nA

2.6 2.4 V (min)

0.4 0.5 V (max)

7.6 Bits

7.6 7.1 Bits (min)

7.5 Bits

7.4 Bits

47 dB

47 44.5 dB (min)

47 dB

46 dB

47 dB

47 44.6 dB (min)

47 dB

46 dB

64 dBc

63 dBc

60

54 dBc

−64 dBc

−63 dBc

-57

−54 dBc

-70 dBc

−65 dBc

-64

−54 dBc

−72 dBc

−70 dBc

-68

−65 dBc

-55 dBc

25

4.4

Units

dBc

dBc

dBc

dBc

mA

mA

5 www.national.com

Symbol Parameter Conditions

Typical

(Note 10)

Limits

(Note 10)

(Limits)

DC Input 25.3 32 mA (max)

ADC08060

IA + DRI

Total Operating Current

D

fIN = 10 MHz, VIN = −3 dBFS, PD = Low

29.4

CLK Low, PD = Hi 0.2

mA (max)

DC Input 76 96 mW (max)

PC Power Consumption

fIN = 10 MHz, VIN = −3 dBFS, PD = Low

88

CLK Low, PD = Hi 0.6 mW

PSRR

PSRR

Power Supply Rejection Ratio

1

Power Supply Rejection Ratio

2

FSE change with 2.7V to 3.3V change in
V

A

SNR change with 200 mV at 200 kHz on
supply

54 dB

45 dB

AC ELECTRICAL CHARACTERISTICS

f

C1

f

C2

t

CL

t

CH

t

OH

t

OD

Maximum Conversion Rate 70 60 MHz (min)

Minimum Conversion Rate 20 MHz

Minimum Clock Low Time 6.7 ns (min)

Minimum Clock High Time 6.7 ns (min)

Output Hold Time CLK Rise to Data Invalid 4.4 ns

Output Delay CLK Rise to Data Valid 8.2 12 ns (max)

Pipeline Delay (Latency) 2.5 Clock Cycles

t

AD

t

AJ

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.

Note 2: All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AGND or DR GND, or greater than VA or DR VD), the current at that pin

should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input
current of 25 mA to two.

Note 4: The Electrical characteristics tables list guaranteed specifications under the listed Recommended Conditions except as otherwise modified or specified
by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations for room temperature only and are not guaranteed.

Note 5: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values
for maximum power dissipation will be reached only when this device is operated in a severe fault condition (e.g., when input or output pins are driven beyond
the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 6: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.

Note 7: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”.

Note 8: The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device.

However, errors in the A/D conversion can occur if the input goes above DR VD or below GND by more than 100 mV. For example, if VA is 2.7VDC the full-scale
input voltage must be ≤2.6VDC to ensure accurate conversions.

Sampling (Aperture) Delay CLK Fall to Acquisition of Data 1.5 ns

Aperture Jitter 2 ps rms

Units

mW

20006207

Note 9: To guarantee accuracy, it is required that VA and DR VD be well bypassed. Each supply pin must be decoupled with separate bypass capacitors.

Note 10: Typical figures are at TJ = 25°C, and represent most likely parametric norms at specific conditions at the time of product characterization and are not

guaranteed. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 11: IDR is the current consumed by the switching of the output drivers and is primarily determined by the load capacitance on the output pins, the supply
voltage, VDR, and the rate at which the outputs are switching (which is signal dependent), IDR = VDR (CO x fO + C1 x f1 + … + C71 x f7) where VDR is the output
driver power supply voltage, Cn is the total capacitance on any given output pin, and fn is the average frequency at which that pin is toggling.

www.national.com 6

ADC08060

Typical Performance Characteristics V

stated

INL

20006208

INL vs. Supply Voltage

= DR VD = 3V, f

A

= 60 MHz, fIN = 10 MHz, unless otherwise

CLK

INL vs. Temperature

20006214

INL vs. Sample Rate

DNL

20006215

20006209

20006210

DNL vs. Temperature

20006217

7 www.national.com

ADC08060

DNL vs. Supply Voltage

DNL vs. Sample Rate

SNR vs. Temperature

SNR vs. Sample Rate

20006218

20006220

20006211

SNR vs. Supply Voltage

20006221

SNR vs. Input Frequency

20006212

www.national.com 8

20006223

ADC08060

SNR vs. Clock Duty Cycle

Distortion vs. Supply Voltage

20006224

Distortion vs. Temperature

20006225

Distortion vs. Sample Rate

Distortion vs. Input Frequency

20006226

20006228

20006213

Distortion vs. Clock Duty Cycle

20006229

9 www.national.com

ADC08060

SINAD/ENOB vs. Temperature

SINAD/ENOB vs. Supply Voltage

SINAD/ENOB vs. Sample Rate

SINAD/ENOB vs. Input Frequency

20006230

20006216

20006238

SINAD/ENOB vs. Clock Duty Cycle

20006240

Power Consumption vs. Sample Rate

20006239

www.national.com 10

20006219

ADC08060

Spectral Response @ fIN = 10.1 MHz

Intermodulation Distortion (IMD)

20006244

Spectral Response @ fIN = 25 MHz

20006245

20006242

11 www.national.com

Specification Definitions

APERTURE (SAMPLING) DELAY is that time required after

the fall of the clock input for the sampling switch to open. The

ADC08060

Sample/Hold circuit effectively stops capturing the input sig­nal and goes into the “hold” mode tAD after the clock goes low.

APERTURE JITTER is the variation in aperture delay from
sample to sample. Aperture jitter shows up as noise at the
output.

CLOCK DUTY CYCLE is the ratio of the time that the clock
waveform is at a logic high to the total time of one clock period.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
Measured at 60 MSPS with a ramp input.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and

Distortion Ratio, or SINAD. ENOB is defined as (SINAD –

1.76) / 6.02 and says that the converter is equivalent to a per­fect ADC of this (ENOB) number of bits.

FULL-POWER BANDWIDTH is the frequency at which the
reconstructed output fundamental drops 3 dB below its low
frequency value for a full scale input.

FULL-SCALE ERROR is a measure of how far the last code
transition is from the ideal 1½ LSB below VRT and is defined
as:

V

+ 1.5 LSB – V

max

where V
mum (full scale) code occurs.

is the voltage at which the transition to the maxi-

max

INTEGRAL NON-LINEARITY (INL) is a measure of the de­viation of each individual code from a line drawn from zero
scale (½ LSB below the first code transition) through positive
full scale (½ LSB above the last code transition). The devia­tion of any given code from this straight line is measured from
the center of that code value. The end point test method is
used. Measured at 60 MSPS with a ramp input.

INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of the interaction
between two sinusoidal frequencies that are applied to the
ADC input at the same time. IMD is the ratio of the power in
the second and third order intermodulation products to the
total power in the original frequencies.

MISSING CODES are those output codes that are skipped
and will never appear at the ADC outputs. These codes can­not be reached with any input value.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure
of how well the ADC rejects a change in the power supply
voltage. For the ADC08060, PSRR1 is the ratio of the change
in d.c. power supply voltage to the resulting change in Full­Scale Error, expressed in dB. PSRR2 is a measure of how
well an a.c. signal riding upon the power supply is rejected
and is here defined as:

RT

where SNR0 is the SNR measured with no noise or signal on
the supply lines and SNR1 is the SNR measured with a 200
kHz, 200 mV

signal riding upon the supply lines.

P-P

OUTPUT DELAY is the time delay after the rising edge of the
input clock before the data changes at the output pins.

OUTPUT HOLD TIME is the length of time that the output data
is valid after the rise of the input clock.

PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is pre­sented to the output driver stage. New data is available at
every clock cycle, but the data lags the conversion by the
Pipeline Delay plus the Output Delay.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal frequency at the output
to the rms value of the sum of all other spectral components
below one-half the sampling frequency, not including har­monics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or
SINAD) is the ratio, expressed in dB, of the rms value of the

input signal frequency at the output to the rms value of all of
the other spectral components below half the clock frequency,
including harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ­ence, expressed in dB, between the rms values of the input
signal frequency at the output and the peak spurious signal,
where a spurious signal is any signal present in the output
spectrum that is not present at the input.

TOTAL HARMONIC DISTORTION (THD) is the ratio, ex­pressed in dB, of the total of the first nine harmonic levels at
the output to the level of the fundamental at the output. THD
is calculated as

where f1 is the RMS power of the fundamental (input) fre­quency and f2 through f10 is the power in the first 9 harmonics
in the output spectrum.

ZERO SCALE OFFSET ERROR is the error in the input volt­age required to cause the first code transition. It is defined as

V

= VZT − V

OFF

RB

where VZT is the first code transition input voltage.

www.national.com 12

Timing Diagram

ADC08060

20006231

FIGURE 1. ADC08060 Timing Diagram

Functional Description

The ADC08060 uses a new, unique architecture that
achieves over 7.4 effective bits at input frequencies up to
30 MHz.

The analog input signal that is within the voltage range set by
VRT and VRB is digitized to eight bits. Output format is straight
binary. Input voltages below VRB will cause the output word
to consist of all zeroes. Input voltages above VRB will cause
the output word to consist of all ones.

Incorporating a switched capacitor bandgap, the ADC08060
exhibits a power consumption that is proportional to frequen­cy, limiting power consumption to what is needed at the clock
rate that is used. This and its excellent performance over a
wide range of clock frequencies makes it an ideal choice as
a single ADC for many 8-bit needs.

Data is acquired at the falling edge of the clock and the digital
equivalent of that data is available at the digital outputs 2.5
clock cycles plus tOD later. The ADC08060 will convert as long
as the clock signal is present. The output coding is straight
binary.

The device is in the active state when the Power Down pin
(PD) is low. When the PD pin is high, the device is in the power
down mode, where the output pins hold the last conversion
before the PD pin went high and the device consumes just 1
mW.

Applications Information

1.0 REFERENCE INPUTS

The reference inputs VRT and VRB are the top and bottom of
the reference ladder, respectively. Input signals between
these two voltages will be digitized to 8 bits. External voltages
applied to the reference input pins should be within the range

specified in the Operating Ratings table (1.0V to (VA + 0.1V)
for VRT and 0V to (VRT − 1.0V) for VRB). Any device used to
drive the reference pins should be able to source sufficient
current into the VRT pin and sink sufficient current from the
VRB pin.

The reference bias circuit of Figure 2 is very simple and the
performance is adequate for many applications. However,
circuit tolerances will lead to a wide reference voltage range.
Superior performance can generally be achieved by driving
the reference pins with a low impedance source.

The circuit of Figure 3 will allow a more accurate setting of the
reference voltages. The upper amplifier must be able to
source the reference current as determined by the value of
the reference resistor and the value of (VRT - VRB). The lower
amplifier must be able to sink this reference current. Both
should be stable with a capacitive load. The LM8272 was
chosen because of its rail-to-rail input and output capability,
its high current output and its ability to drive large capacitance
loads. Of course, the divider resistors at the amplifier input
could be changed to suit your reference voltage needs, or the
divider can be replaced with potentiometers or DACs for pre­cise settings. The bottom of the ladder (VRB) may simply be
returned to ground if the minimum input signal excursion is
0V. Be sure that the driving sources can source sufficient cur­rent into the VRT pin and sink enough current from the VRB pin
to keep these pins stable.

VRT should always be more positive than VRB at least by the
minimum VRT - VRB difference in the Electrical Characteristics
table to minimize noise. Furthermore, the difference between
VRT and VRB should not exceed the maximum value specified
in the Electrical Characteristics table to avoid signal distortion.

VRM (pin 9) is the center of the reference ladder and should
be bypassed to a clean, quiet point in the analog ground plane
with a 0.1 µF capacitor. DO NOT allow this pin to float.

13 www.national.com

ADC08060

20006232

FIGURE 2. Simple, low component count reference biasing. Because of the ladder and external resistor tolerances, the

reference voltage can vary too much for some applications.

FIGURE 3. Driving the reference to force desired values requires driving with a low impedance source.

www.national.com 14

20006233

ADC08060

2.0 THE ANALOG INPUT

The analog input of the ADC08060 is a switch followed by an
integrator. The input capacitance changes with the clock lev­el, appearing as 3 pF when the clock is low, and 4 pF when
the clock is high. The sampling nature of the analog input
causes current spikes that result in voltage spikes at the ana­log input pin. Any circuit used to drive the analog input must
be able to drive that input and to settle within the clock high
time. The LMH6702 has been found to be a good amplifier to
drive the ADC08060.

Figure 4 shows an example of an input circuit using the
LMH6702. Any input amplifier should incorporate some gain
as operational amplifiers exhibit better phase margin and
transient response with gains above 2 or 3 than with unity
gain. If an overall gain of less than 3 is required, attenuate the
input and operate the amplifier at a higher gain, as shown in
Figure 4.

FIGURE 4. The input amplifier should incorporate some gain for best performance (see text).

The RC at the amplifier output filters the clock rate energy that
comes out of the analog input due to the input sampling circuit.
The optimum time constant for this circuit depends not only
upon the amplifier and ADC, but also on the circuit layout and
board material. A resistor value should be chosen between
18Ω and 47Ω and the capacitor value chose according to the
formula

This will provide optimum SNR performance. Best THD per­formance is realized when the capacitor and resistor values
are both zero. To optimize SINAD, reduce the capacitor or
resistor value until SINAD performance is optimized. That is,
until SNR = −THD. This value will usually be in the range of
40% to 65% of the value calculated with the above formula.
An accurate calculation is not possible because of the board
material and layout dependence.

The above is intended for oversampling or Nyquist applica­tions. There should be no resistor or capacitor between the
ADC input and any amplifier for undersampling applications.

The circuit of Figure 4 has both gain and offset adjustments.
If you eliminate these adjustments normal circuit tolerances
may cause signal clipping unless care is exercised in the

20006234

worst case analysis of component tolerances and the input
signal excursion is appropriately limited to account for the
worst case conditions. Of course, this means that the design­er will not be able to depend upon getting a full scale output
with maximum signal input.

3.0 POWER SUPPLY CONSIDERATIONS

A/D converters draw sufficient transient current to corrupt
their own power supplies if not adequately bypassed. A
10 µF tantalum or aluminum electrolytic capacitor should be
placed within an inch (2.5 cm) of the A/D power pins, with a

0.1 µF ceramic chip capacitor placed within one centimeter of
the converter's power supply pins. Leadless chip capacitors
are preferred because they have low lead inductance.

While a single voltage source is recommended for the VA and
DR VD supplies of the ADC08060, these supply pins should
be well isolated from each other to prevent any digital noise
from being coupled into the analog portions of the ADC. A
choke or 27Ω resistor is recommended between these supply
lines with adequate bypass capacitors close to the supply
pins.

As is the case with all high speed converters, the ADC08060
should be assumed to have little power supply rejection. None
of the supplies for the converter should be the supply that is
used for other digital circuitry in any system with a lot of digital

15 www.national.com

power being consumed. The ADC supplies should be the
same supply used for other analog circuitry.

No pin should ever have a voltage on it that is in excess of the
supply voltage or below ground by more than 300 mV, not

ADC08060

even on a transient basis. This can be a problem upon appli­cation of power and power shut-down. Be sure that the sup­plies to circuits driving any of the input pins, analog or digital,
do not come up any faster than does the voltage at the
ADC08060 power pins.

4.0 THE DIGITAL INPUT PINS

The ADC08060 has two digital input pins: The PD pin and the
Clock pin.

4.1 The PD Pin

The Power Down (PD) pin, when high, puts the ADC08060
into a low power mode where power consumption is reduced
to 1 mW. Output data is valid and accurate about 1 microsec­ond after the PD pin is brought low.

The digital output pins retain the last conversion output code
when either the clock is stopped or the PD pin is high.

4.2 The ADC08060 Clock

Although the ADC08060 is tested and its performance is
guaranteed with a 60 MHz clock, it typically will function well
with clock frequencies from 20 MHz to 70 MHz.

Halting the clock will provide nearly as much power saving as
raising the PD pin high. Typical power consumption with a
stopped clock is 3 mW, compared to 1 mW when PD is high.
The digital outputs will remain in the same state as they were
before the clock was halted.

Once the clock is restored (or the PD pin is brought low), there
is a time of about 1 µs before the output data is valid. How­ever, because of the linear relationship between total power
consumption and clock frequency, the part requires about 1
µs after the clock is restarted or substantially changed in fre­quency before the part returns to its specified accuracy.

The low and high times of the clock signal can affect the per­formance of any A/D Converter. Because achieving a precise
duty cycle is difficult, the ADC08060 is designed to maintain
performance over a range of duty cycles. While it is specified
and performance is guaranteed with a 50% clock duty cycle
and 60 Msps, ADC08060 performance is typically maintained
with clock high and low times of 3.3 ns, corresponding to a
clock duty cycle range of 40% to 50% with a 60 MHz clock.
Note that the clock minimum high and low times may not be
used simultaneously.

The CLOCK line should be series terminated at the clock
source in the characteristic impedance of that line. If the clock
line is longer than

where tPD is the signal propagation rate down the clock line,
"L" is the line length and ZO is the characteristic impedance
of the clock line. This termination should be located as close
as possible to, but within one centimeter of, the ADC08060
clock pin. Further, the termination should be beyond the
ADC08060 clock pin as seen from the clock source. Typical
tPD is about 150 ps/inch on FR-4 board material. For FR-4
board material, the value of C becomes

where L is the length of the clock line in inches.

5.0 LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are essen­tial to ensure accurate conversion. A combined analog and
digital ground plane should be used.

Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise
because of the skin effect. Total surface area is more impor­tant than is total ground plane volume. Capacitive coupling
between the typically noisy digital circuitry and the sensitive
analog circuitry can lead to poor performance that may seem
impossible to isolate and remedy. The solution is to keep the
analog circuitry well separated from the digital circuitry.

The DR GND connection to the ground plane should not use
the same feedthrough used by other ground connections.

High power digital components should not be located on or
near a straight line between the ADC (or any linear compo­nent) and the power supply area as the resulting common
return current path could cause fluctuation in the analog
“ground” return of the ADC.

Generally, analog and digital lines should cross each other at
90° to avoid getting digital noise into the analog path. In high
frequency systems, however, avoid crossing analog and dig­ital lines altogether. Clock lines should be isolated from ALL
other lines, analog AND digital. Even the generally accepted
90° crossing should be avoided as even a little coupling can
cause problems at high frequencies. Best performance at
high frequencies is obtained with a straight signal path.

The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any ex­ternal component (e.g., a filter capacitor) connected between
the converter's input and ground should be connected to a
very clean point in the analog ground plane.

Figure 5 gives an example of a suitable layout. All analog cir­cuitry (input amplifiers, filters, reference components, etc.)
should be placed together away from any digital components.

where tr is the clock rise time and tPD is the propagation rate
of the signal along the trace.

If the clock source is used to drive more than just the
ADD08060, the CLOCK pin should be a.c. terminated with a
series RC to ground such that the resistor value is equal to
the characteristic impedance of the clock line and the capac­itor value is

www.national.com 16

20006236

FIGURE 5. Layout Example

6.0 DYNAMIC PERFORMANCE

The ADC08060 is a.c. tested and its dynamic performance is
guaranteed. To meet the published specifications, the clock
source driving the CLK input must exhibit less than 10 ps
(rms) of jitter. For best a.c. performance, isolating the ADC
clock from any digital circuitry should be done with adequate
buffers, as with a clock tree. See Figure 6.

It is good practice to keep the ADC clock line as short as pos­sible and to keep it well away from any other signals. Other
signals can introduce jitter into the clock signal. The clock
signal can also introduce noise into the analog path.

ADC08060

7.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power

supply rails. For proper operation, all inputs should not go

more than 300 mV below the ground pins or 300 mV above
the supply pins. Exceeding these limits on even a transient
basis may cause faulty or erratic operation. It is not uncom­mon for high speed digital circuits (e.g., 74F and 74AC de­vices) to exhibit undershoot that goes more than a volt below
ground. A 51Ω resistor in series with the offending digital input
will usually eliminate the problem.

Care should be taken not to overdrive the inputs of the
ADC08060. Such practice may lead to conversion inaccura­cies and even to device damage.

Attempting to drive a high capacitance digital data bus.

The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current is re­quired from DR VD and DR GND. These large charging cur­rent spikes can couple into the analog section, degrading
dynamic performance. Buffering the digital data outputs (with
a 74F541, for example) may be necessary if the data bus ca­pacitance exceeds 10 pF. Dynamic performance can also be
improved by adding 100Ω series resistors at each digital out­put, reducing the energy coupled back into the converter input
pins.

Using an inadequate amplifier to drive the analog input.

As explained in Section 2.0, the capacitance seen at the input
alternates between 3 pF and 4 pF with the clock. This dynamic
capacitance is more difficult to drive than is a fixed capaci­tance, and should be considered when choosing a driving
device. The LMH6702 has been found to be a good device
for driving the ADC08060.

Driving the VRT pin or the VRB pin with devices that can
not source or sink the current required by the ladder.

As mentioned in Section 1.0, care should be taken to see that
any driving devices can source sufficient current into the
VRT pin and sink sufficient current from the VRB pin. If these
pins are not driven with devices than can handle the required
current, these reference pins will not be stable, resulting in a
reduction of dynamic performance.

Using a clock source with excessive jitter, using an ex­cessively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the sam-

pling interval to vary, causing excessive output noise and a
reduction in SNR performance. The use of simple gates with
RC timing is generally inadequate as a clock source.

20006237

FIGURE 6. Isolating the ADC Clock from Digital Circuitry

17 www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted

ADC08060

NOTES: UNLESS OTHERWISE SPECIFIED

REFERENCE JEDEC REGISTRATION mo-153, VARIATION AD, DATED 7/93.

24-Lead Package TC

Order Number ADC08060CIMT

NS Package Number MTC24

www.national.com 18

Notes

ADC08060

19 www.national.com

Notes

For more National Semiconductor product information and proven design tools, visit the following Web sites at:

Products Design Support

Amplifiers www.national.com/amplifiers WEBENCH www.national.com/webench

Audio www.national.com/audio Analog University www.national.com/AU

Sample-and-Hold

Clock Conditioners www.national.com/timing App Notes www.national.com/appnotes

Data Converters www.national.com/adc Distributors www.national.com/contacts

Displays www.national.com/displays Green Compliance www.national.com/quality/green

Ethernet www.national.com/ethernet Packaging www.national.com/packaging

Interface www.national.com/interface Quality and Reliability www.national.com/quality

LVDS www.national.com/lvds Reference Designs www.national.com/refdesigns

Power Management www.national.com/power Feedback www.national.com/feedback

Switching Regulators www.national.com/switchers

LDOs www.national.com/ldo

LED Lighting www.national.com/led

PowerWise www.national.com/powerwise

Serial Digital Interface (SDI) www.national.com/sdi

Temperature Sensors www.national.com/tempsensors

Wireless (PLL/VCO) www.national.com/wireless

THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION
(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY
OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO
SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,
IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS
DOCUMENT.

TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT
NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL
PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR
APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND
APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE
NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.

EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO
LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE
AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY
RIGHT.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and
whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected
to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

ADC08060 8-Bit, 20 MSPS to 60 MSPS, 1.3 mW/MSPS A/D Converter with Internal

National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other
brand or product names may be trademarks or registered trademarks of their respective holders.

Copyright© 2008 National Semiconductor Corporation

For the most current product information visit us at www.national.com

www.national.com

National Semiconductor
Americas Technical
Support Center

Email:
[e-mail]
Tel: [phone]

National Semiconductor Europe
Technical Support Center

Email: [e-mail]
German Tel: [phone]
English Tel: [phone]

National Semiconductor Asia
Pacific Technical Support Center

Email: [e-mail]

National Semiconductor Japan
Technical Support Center

Email: [e-mail]