National Semiconductor ADC0806 Technical data

February 8, 2008

ADC08060
8-Bit, 20 MSPS to 60 MSPS, 1.3 mW/MSPS A/D Converter
with Internal Sample-and-Hold

ADC08060 8-Bit, 20 MSPS to 60 MSPS, 1.3 mW/MSPS A/D Converter with Internal

Sample-and-Hold

General Description

The ADC08060 is a low-power, 8-bit, monolithic analog-to­digital converter with an on-chip track-and-hold circuit. Opti­mized for low cost, low power, small size and ease of use, this
product operates at conversion rates of 20 MSPS to 70 MSPS
with outstanding dynamic performance over its full operating
range while consuming just 1.3 mW per MHz of clock fre­quency. That's just 78 mW of power at 60 MSPS. Raising the
PD pin puts the ADC08060 into a Power Down mode where
it consumes just 1 mW.

The unique architecture achieves 7.5 Effective Bits with
25 MHz input frequency. The excellent DC and AC charac­teristics of this device, together with its low power consump­tion and single +3V supply operation, make it ideally suited
for many imaging and communications applications, including
use in portable equipment. Furthermore, the ADC08060 is
resistant to latch-up and the outputs are short-circuit proof.
The top and bottom of the ADC08060's reference ladder are
available for connections, enabling a wide range of input pos­sibilities. The digital outputs are TTL/CMOS compatible with
a separate output power supply pin to support interfacing with
3V or 2.5V logic. The output coding is straight binary and the
digital inputs (CLK and PD) are TTL/CMOS compatible.

The ADC08060 is offered in a 24-lead plastic package
(TSSOP) and is specified over the industrial temperature
range of −40°C to +85°C.

Features

Single-ended input

■

Internal sample-and-hold function

■

Low voltage (single +3V) operation

■

Small package

■

Power-down feature

■

Key Specifications

Resolution 8 bits

■

Maximum sampling frequency 60 MSPS (min)

■

DNL 0.4 LSB (typ)

■

ENOB 7.5 bits (typ) at fIN = 25 MHz

■

THD −60 dB (typ)

■

No missing codes Guaranteed

■

Power Consumption

■

Operating 1.3 mW/MSPS (typ)

—

■

Power Down Mode 1 mW (typ)

—

Applications

Digital imaging systems

■

Communication systems

■

Portable instrumentation

■

Viterbi decoders

■

Set-top boxes

■

Pin Configuration

20006201

© 2008 National Semiconductor Corporation 200062 www.national.com

Ordering Information

Order Number Temperature Range Package

ADC08060

ADC08060CIMT

ADC08060CIMTX

Block Diagram

−40°C ≤ TA ≤ +85°C

−40°C ≤ TA ≤ +85°C

TSSOP

TSSOP (tape and reel)

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

10

6

3

9

V

IN

V

RT

V

RM

V

RB

Analog signal input. Conversion range is VRB to VRT.

Analog Input that is the high (top) side of the reference ladder
of the ADC. Nominal range is 1.0V to VA. Voltage on VRT and
VRB inputs define the VIN conversion range. Bypass well. See
Section 2.0 for more information.

Mid-point of the reference ladder. This pin should be
bypassed to a clean, quiet point in the analog ground plane
with a 0.1 µF capacitor.

Analog Input that is the low side (bottom) of the reference
ladder of the ADC. Nominal range is 0.0V to (VRT – 1.0V).
Voltage on VRT and VRB inputs define the VIN conversion
range. Bypass well. See Section 2.0 for more information.

20006202

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Pin No. Symbol Equivalent Circuit Description

Power Down input. When this pin is high, the converter is in

23 PD

the Power Down mode and the data output pins hold the last
conversion result.

ADC08060

24 CLK

13 thru 16

and

19 thru 22

7

D0–D7

VIN GND

CMOS/TTL compatible digital clock Input. VIN is sampled on
the falling edge of CLK input.

Conversion data digital Output pins. D0 is the LSB, D7 is the
MSB. Valid data is output just after the rising edge of the CLK
input.

Reference ground for the single-ended analog input, VIN.

Positive analog supply pin. Connect to a clean, quiet voltage

1, 4, 12

V

A

source of +3V. VA should be bypassed with a 0.1 µF ceramic
chip capacitor for each pin, plus one 10 µF capacitor. See
Section 3.0 for more information.

18

DR V

D

Power supply for the output drivers. If connected to VA,
decouple well from VA.

17 DR GND The ground return for the output driver supply.

2, 5, 8, 11 AGND The ground return for the analog supply.

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Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/

ADC08060

Distributors for availability and specifications.

Supply Voltage (VA)

Driver Supply Voltage (DR VD) VA + 0.3V

Voltage on Any Input or Output Pin −0.3V to V

Reference Voltage (VRT, VRB) VA to AGND

CLK, OE Voltage Range −0.3V to

3.8V

A

Operating Ratings (Notes 1, 2)

Operating Temperature Range

Supply Voltage (VA)

Driver Supply Voltage (DR VD) +2.4V to V

Ground Difference |GND - DR GND| 0V to 300 mV
Upper Reference Voltage (VRT) 1.0V to (VA + 0.1V)

Lower Reference Voltage (VRB) 0V to (VRT − 1.0V)

VIN Voltage Range VRB to V

−40°C ≤ TA ≤ +85°C

+2.7V to +3.6V

(VA + 0.3V)

Digital Output Voltage (VOH, VOL) DR GND to DR V

D

Input Current at Any Pin (Note 3) ±25 mA
Package Input Current (Note 3) ±50 mA
Power Dissipation at TA = 25°C

ESD Susceptibility (Note 6)
Human Body Model
Machine Model

See (Note 5)

2500V

250V

Soldering Temperature, Infrared,
10 seconds (Note 7) 235°C

Storage Temperature −65°C to +150°C

Converter Electrical Characteristics

The following specifications apply for VA = DR VD = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, f
cycle. Boldface limits apply for TJ = T

Symbol Parameter Conditions

MIN

to T

: all other limits TA = 25°C (Notes 4, 8, 9)

MAX

Typical

(Note 10)

DC ACCURACY

INL Integral Non-Linearity ±0.5 ±1.3 LSB (max)

DNL Differential Non-Linearity ±0.4

Missing Codes 0 (max)

FSE Full Scale Error 18 ±28 mV (max)

ZSE Zero Scale Offset Error 26 ±35 mV (max)

ANALOG INPUT AND REFERENCE CHARACTERISTICS

V

IN

C

IN

R

IN

Input Voltage

VIN Input Capacitance VIN = 0.75V +0.5 Vrms

RIN Input Resistance

1.6

(CLK LOW) 3 pF

(CLK HIGH) 4 pF

>1

BW Full Power Bandwidth 200 MHz

V

RT

V

RB

VRT - V

R

REF

I

REF

Top Reference Voltage

Bottom Reference Voltage

Reference Delta

RB

Reference Ladder Resistance

Reference Ladder Current

VRT to V

RB

1.9

0.3

1.6

220

7.3

= 60 MHz at 50% duty

CLK

Limits

(Note 10)

+1.0

LSB (max)

−0.9

V

RB

V

RT

V

A

1.0 V (min)

VRT − 1.0

0 V (min)

1.0 V (min)

2.3 V (max)

150

300

5.3 mA (min)

10.6 mA (max)

(Limits)

LSB (min)

V (max)

V (max)

V (max)

Ω (max)

A

RT

Units

V (min)

MΩ

Ω (min)

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ADC08060

Symbol Parameter Conditions

CLK, PD DIGITAL INPUT CHARACTERISTICS

V

IH

V

IL

I

IH

I

IL

C

IN

Logical High Input Voltage

Logical Low Input Voltage

Logical High Input Current

Logical Low Input Current

Logic Input Capacitance 3 pF

DR VD = VA = 3.3V

DR VD = VA = 2.7V

VIH = DR VD = VA = 3.3V

VIL = 0V, DR VD = VA = 2.7V

DIGITAL OUTPUT CHARACTERISTICS

V

OH

V

OL

High Level Output Voltage

Low Level Output Voltage

VA = DR VD = 2.7V, IOH = −400 µA

VA = DR VD = 2.7V, IOL = 1.0 mA

DYNAMIC PERFORMANCE

fIN = 4.4 MHz, VIN = −0.25 dBFS

ENOB Effective Number of Bits

fIN = 10 MHz, VIN = −0.25 dBFS

fIN = 25 MHz, VIN = −0.25 dBFS

fIN = 29 MHz, VIN = −0.25 dBFS

fIN = 4.4 MHz, VIN = −0.25 dBFS

SINAD Signal-to-Noise & Distortion

fIN = 10 MHz, VIN = −0.25 dBFS

fIN = 25 MHz, VIN = −0.25 dBFS

fIN = 29 MHz, VIN = −0.25 dBFS

fIN = 4.4 MHz, VIN = −0.25 dBFS

SNR Signal-to-Noise Ratio

fIN = 10 MHz, VIN = −0.25 dBFS

fIN = 25 MHz, VIN = −0.25 dBFS

fIN = 29 MHz, VIN = −0.25 dBFS

fIN = 4.4 MHz, VIN = −0.25 dBFS

SFDR Spurious Free Dynamic Range

fIN = 10 MHz, VIN = −0.25 dBFS

fIN = 25 MHz, VIN = −0.25 dBFS

fIN = 29 MHz, VIN = −0.25 dBFS

fIN = 4.4 MHz, VIN = −0.25 dBFS

THD Total Harmonic Distortion

fIN = 10 MHz, VIN = −0.25 dBFS

fIN = 25 MHz, VIN = −0.25 dBFS

fIN = 29 MHz, VIN = −0.25 dBFS

fIN = 4.4 MHz, VIN = −0.25 dBFS

HD2 2nd Harmonic Distortion

fIN = 10 MHz, VIN = −0.25 dBFS

fIN = 25 MHz, VIN = −0.25 dBFS

fIN = 29 MHz, VIN = −0.25 dBFS

fIN = 4.4 MHz, VIN = −0.25 dBFS

HD3 3rd Harmonic Distortion

fIN = 10 MHz, VIN = −0.25 dBFS

fIN = 25 MHz, VIN = −0.25 dBFS

fIN = 29 MHz, VIN = −0.25 dBFS

IMD Intermodulation Distortion

f1 = 11 MHz, VIN = −6.25 dBFS
f2 = 12 MHz, VIN = −6.25 dBFS

POWER SUPPLY CHARACTERISTICS

I

A

DR I

Analog Supply Current

Output Driver Supply Current

D

DC Input 25 31 mA (max)

fIN = 10 MHz, VIN = −3 dBFS

DC Input 0.3 1 mA (max)

fIN = 10 MHz, VIN = 3 dBFS (Note )

Typical

(Note 10)

Limits

(Note 10)

(Limits)

2.0 V (min)

0.8 V (max)

10 nA

−50 nA

2.6 2.4 V (min)

0.4 0.5 V (max)

7.6 Bits

7.6 7.1 Bits (min)

7.5 Bits

7.4 Bits

47 dB

47 44.5 dB (min)

47 dB

46 dB

47 dB

47 44.6 dB (min)

47 dB

46 dB

64 dBc

63 dBc

60

54 dBc

−64 dBc

−63 dBc

-57

−54 dBc

-70 dBc

−65 dBc

-64

−54 dBc

−72 dBc

−70 dBc

-68

−65 dBc

-55 dBc

25

4.4

Units

dBc

dBc

dBc

dBc

mA

mA

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Symbol Parameter Conditions

Typical

(Note 10)

Limits

(Note 10)

(Limits)

DC Input 25.3 32 mA (max)

ADC08060

IA + DRI

Total Operating Current

D

fIN = 10 MHz, VIN = −3 dBFS, PD = Low

29.4

CLK Low, PD = Hi 0.2

mA (max)

DC Input 76 96 mW (max)

PC Power Consumption

fIN = 10 MHz, VIN = −3 dBFS, PD = Low

88

CLK Low, PD = Hi 0.6 mW

PSRR

PSRR

Power Supply Rejection Ratio

1

Power Supply Rejection Ratio

2

FSE change with 2.7V to 3.3V change in
V

A

SNR change with 200 mV at 200 kHz on
supply

54 dB

45 dB

AC ELECTRICAL CHARACTERISTICS

f

C1

f

C2

t

CL

t

CH

t

OH

t

OD

Maximum Conversion Rate 70 60 MHz (min)

Minimum Conversion Rate 20 MHz

Minimum Clock Low Time 6.7 ns (min)

Minimum Clock High Time 6.7 ns (min)

Output Hold Time CLK Rise to Data Invalid 4.4 ns

Output Delay CLK Rise to Data Valid 8.2 12 ns (max)

Pipeline Delay (Latency) 2.5 Clock Cycles

t

AD

t

AJ

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.

Note 2: All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AGND or DR GND, or greater than VA or DR VD), the current at that pin

should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input
current of 25 mA to two.

Note 4: The Electrical characteristics tables list guaranteed specifications under the listed Recommended Conditions except as otherwise modified or specified
by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations for room temperature only and are not guaranteed.

Note 5: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the
junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values
for maximum power dissipation will be reached only when this device is operated in a severe fault condition (e.g., when input or output pins are driven beyond
the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 6: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.

Note 7: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”.

Note 8: The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device.

However, errors in the A/D conversion can occur if the input goes above DR VD or below GND by more than 100 mV. For example, if VA is 2.7VDC the full-scale
input voltage must be ≤2.6VDC to ensure accurate conversions.

Sampling (Aperture) Delay CLK Fall to Acquisition of Data 1.5 ns

Aperture Jitter 2 ps rms

Units

mW

20006207

Note 9: To guarantee accuracy, it is required that VA and DR VD be well bypassed. Each supply pin must be decoupled with separate bypass capacitors.

Note 10: Typical figures are at TJ = 25°C, and represent most likely parametric norms at specific conditions at the time of product characterization and are not

guaranteed. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 11: IDR is the current consumed by the switching of the output drivers and is primarily determined by the load capacitance on the output pins, the supply
voltage, VDR, and the rate at which the outputs are switching (which is signal dependent), IDR = VDR (CO x fO + C1 x f1 + … + C71 x f7) where VDR is the output
driver power supply voltage, Cn is the total capacitance on any given output pin, and fn is the average frequency at which that pin is toggling.

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