National Semiconductor ADC08031, ADC08032, ADC08034, ADC08038 Technical data

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ADC08031/ADC08032/ADC08034/ADC08038
8-Bit High-Speed Serial I/O A/D Converters with
Multiplexer Options, Voltage Reference, and Track/Hold
Function

June 2000

ADC08031/ADC08032/ADC08034/ADC08038 8-Bit High-Speed Serial I/O A/D Converters with

Multiplexer Options, Voltage Reference, and Track/Hold Function

General Description

The ADC08031/ADC08032/ADC08034/ADC08038 are 8-bit
successive approximationA/D converters with serial I/O and
configurable input multiplexers with up to 8 channels. The
serial I/O is configured to comply with the NSC MICROW-

™

IRE

serial data exchangestandard for easy interface tothe

™

COPS
standard shift registers or microprocessors.

TheADC08034 and ADC08038 provide a 2.6V band-gap de­rived reference. For devices offeringguaranteed voltage ref­erence performance over temperature see ADC08131,
ADC08134 and ADC08138.

Atrack/hold function allowsthe analog voltage at thepositive
input to vary during the actual A/D conversion.

The analog inputs can be configured to operate in various
combinations of single-ended, differential, or
pseudo-differential modes. In addition, input voltage spans
as small as 1V can be accommodated.

family of controllers, and can easily interface with

Applications

n Digitizing automotive sensors
n Process control monitoring
n Remote sensing in noisy environments
n Instrumentation

Ordering Information

n Test systems
n Embedded diagnostics

Features

n Serial digital data link requires few I/O pins
n Analog input track/hold function
n 2-, 4-, or 8-channel input multiplexer options with

address logic

n 0V to 5V analog input range with single 5V power

supply

n No zero or full scale adjustment required
n TTL/CMOS input/output compatible
n On chip 2.6V band-gap reference
n 0.3" standard width 8-, 14-, or 20-pin DIP package
n 14-, 20-pin small-outline packages

Key Specifications

n Resolution: 8 bits
n Conversion time (f
n Power dissipation: 20mW (max)
n Single supply: 5V
n Total unadjusted error:
n No missing codes over temperature

= 1 MHz): 8µs (max)

C

(±5%)

DC

1

±

⁄2LSB and±1LSB

Industrial (−40˚C ≤ TA≤ +85˚C) Package

ADC08031CIN* N08E
ADC08038CIN* N20A
ADC08031CIWM,
ADC08032CIWM, M14B
ADC08034CIWM
ADC08038CIWM M20B

*

Not recomended for new designs.

COPS™microcontrollers and MICROWIRE™are trademarks of National Semiconductor Corporation.

© 2000 National Semiconductor Corporation DS010555 www.national.com

Connection Diagrams

ADC08038

ADC08031/ADC08032/ADC08034/ADC08038

DS010555-2

ADC08031

Dual-In-Line Package

ADC08034

DS010555-3

ADC08032

Small Outline Package

ADC08031

Small Outline Package

DS010555-31

DS010555-5

DS010555-30

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ADC08031/ADC08032/ADC08034/ADC08038

Absolute Maximum Ratings (Notes 1, 3)

Storage Temperature −65˚C to +150˚C

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V
Voltage at Inputs and Outputs −0.3V to V
Input Current at Any Pin (Note 4)
Package Input Current (Note 4)
Power Dissipation at T

) 6.5V

CC

CC

±

= 25˚C

A

+ 0.3V

±

5mA

20 mA

(Note 5) 800 mW
ESD Susceptibility (Note 6) 1500V
Soldering Information

N Package (10 sec.)

235˚C

SO Package:

Vapor Phase (60 sec.)
Infrared (15 sec.) (Note 7)

215˚C
220˚C

Operating Ratings (Notes 2, 3)

Temperature Range T
ADC08031BIN, ADC08031CIN, −40˚C ≤ TA≤ +85˚C
ADC08032BIN, ADC08032CIN,
ADC08034BIN, ADC08034CIN,
ADC08038BIN, ADC08038CIN,
ADC08031BIWM, ADC08032BIWM,
ADC08034BIWM, ADC08038BIWM
ADC08031CIWM, ADC08032CIWM,
ADC08034CIWM, ADC08038CIWM
Supply Voltage (V

) 4.5 VDCto 6.3 V

CC

MIN

≤ TA≤ T

Electrical Characteristics

The following specifications apply for VCC=V

apply for TA=TJ=T

MIN

to T

; all other limits TA=TJ= 25˚C.

MAX

Symbol Parameter Conditions Typical Limits Units

CONVERTER AND MULTIPLEXER CHARACTERISTICS

Total Unadjusted Error (Note 10)

BIN, BIWM

CIN, CIWM
Differential 8 Bits (min)
Linearity

R

REF

V

IN

Reference Input Resistance (Note 11) 3.5 kΩ

Analog Input Voltage (Note 12) (VCC+ 0.05) V (max)

DC Common-Mode Error
Power Supply Sensitivity V

On Channel Leakage On Channel = 5V, 0.2 µA (max)
Current (Note 13) Off Channel = 0V 1

Off Channel Leakage On Channel = 5V, −0.2 µA (max)
Current (Note 13) Off Channel = 0V −1

DIGITAL AND DC CHARACTERISTICS

V
V
I
I
V

V

IN(1)
IN(0)

IN(1)
IN(0)

OUT(1)

OUT(0)

Logical “1” Input Voltage VCC= 5.25V 2.0 V (min)
Logical “0” Input Voltage VCC= 4.75V 0.8 V (max)
Logical “1” Input Current VIN= 5.0V 1 µA (max)
Logical “0” Input Current VIN=0V −1 µA (max)
Logical “1” Output Voltage VCC= 4.75V:

Logical “0” Output Voltage VCC= 4.75V 0.4 V (max)

=+5VDC, and f

REF

= 1 MHz unless otherwise specified. Boldface limits

CLK

(Note 8) (Note 9) (Limits)

1

±

⁄

2

±

1 LSB (max)

LSB (max)

1.3 kΩ (min)

6.0 kΩ (max)

(GND − 0.05) V (min)

1

±

⁄

CC

V

REF

=5V±5%,

= 4.75V

4

1

±

⁄

4

LSB (max)
LSB (max)

On Channel = 0V, −0.2 µA (max)
Off Channel = 5V −1

On Channel = 0V, 0.2 µA (max)
Off Channel = 5V 1

I

= −360 µA 2.4 V (min)

OUT

I

= −10 µA 4.5 V (min)

OUT

I

= 1.6 mA

OUT

MAX

DC

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Electrical Characteristics (Continued)

The following specifications apply for VCC=V

apply for TA=TJ=T

MIN

to T

; all other limits TA=TJ= 25˚C.

MAX

Symbol Parameter Conditions Typical Limits Units

DIGITAL AND DC CHARACTERISTICS

I

OUT

I

SOURCE

I

SINK

I

CC

TRI-STATE®Output Current V

Output Source Current V
Output Sink Current V
Supply Current

ADC08031, ADC08034, CS = HIGH
and ADC08038
ADC08032 (Note 16) 7.0 mA (max)

REFERENCE CHARACTERISTICS

ADC08031/ADC08032/ADC08034/ADC08038

V

OUT Nominal Reference Output V

REF

=+5VDC, and f

REF

= 1 MHz unless otherwise specified. Boldface limits

CLK

(Note 8) (Note 9) (Limits)

=0V −3.0 µA (max)

OUT

V

=5V 3.0 µA (max)

OUT

=0V −6.5 mA (min)

OUT
OUT=VCC

8.0 mA (min)

3.0 mA (max)

OUT Option

REF

Available Only on 2.6 V
ADC08034 and

ADC08038

Electrical Characteristics

The following specifications apply for VCC=V

apply for TA=TJ=T

MIN

to T

; all other limits TA=TJ= 25˚C.

MAX

Symbol Parameter Conditions Typical Limits Units

f

CLK

Clock Frequency 10 kHz (min)

Clock Duty Cycle 40 % (min)
(Note 14) 60 % (max)

T

C

Conversion Time (Not Including f
MUX Addressing Time) 8 µs (max)

t

CA

t

SELECT

t

SET-UP

Acquisition Time
CLK High while CS is High 50 ns
CS Falling Edge or Data Input 25 ns (min)
Valid to CLK Rising Edge

t

HOLD

Data Input Valid after CLK 20 ns (min)
Rising Edge

t

pd1,tpd0

CLK Falling Edge to Output CL= 100 pF:
Data Valid (Note 15) Data MSB First 250 ns (max)

t

1H,t0H

TRI-STATE Delay from Rising Edge CL= 10 pF, RL=10kΩ 50 ns
of CS to Data Output and SARS Hi-Z

C

IN

C

OUT

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed speci-

fications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance character­istics may degrade when the device is not operated under the listed test conditions.

Note 3: All voltages are measured with respect to AGND = DGND = 0 V
Note 4: When the input voltage V

The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

allowable power dissipation at any temperature is P

Capacitance of Logic Inputs 5 pF
Capacitance of Logic Outputs 5 pF

at any pin exceeds the power supplies (V

IN

=(T

D

=+5VDC, and tr=tf= 20 ns unless otherwise specified. Boldface limits

REF

(Note 8) (Note 9) (Limits)

1 MHz (max)

= 1 MHz 8 1/f

CLK

1

⁄

2

Data LSB First 200 ns (max)

(see TRI-STATE Test Circuits)
C

= 100 pF, RL=2kΩ 180 ns (max)

L

, unless otherwise specified.

DC

<

(AGND or DGND) or V

IN

)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower. For these de-

JMAX−TA

>

VCC) the current at that pin should be limited to 5 mA.

IN

, θJAand the ambient temperature, TA. The maximum

JMAX

1/f

CLK

CLK

(max)

(max)

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Electrical Characteristics (Continued)

vices, T
120˚C/W,ADC08038withCINsuffix80˚C/W. ADC08031 with CIWM suffix 140˚C/W, ADC08032 140˚C/W,ADC08034140˚C/W, ADC08038 with CIWM suffix 91˚C/W.

Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kΩ resistor.
Note 7: See AN450 “Surface MountingMethods and Their Effect on Product Reliability” or Linear DataBook section “Surface Mount” for other methods of soldering

surface mount devices.

Note 8: Typicals are at T
Note 9: Guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Total unadjusted error includes offset, full-scale, linearity, multiplexer.
Note 11: Cannot be tested for the ADC08032.
Note 12: For V

analog input voltages one diode drop below groundor one diode drop greater than V
(e.g., 5V) can cause an input diode to conduct, especially atelevated temperatures, which willcause errors for analog inputs near full-scale. Thespec allows 50 mV
forward bias of either diode; this means that as long as the analog V
ceeding this range on an unselected channelwillcorrupt the reading of a selected channel. Achievement of an absolute 0V
fore require a minimum supply voltage of 4.950 V

Note 13: Channel leakage currentis measured after a single-ended channelis selected and the clock isturned off. For off channel leakage currentthe following two
cases are considered: one, with the selected channel tied high(5 V
nels is measured; two, withthe selected channel tied low and the off channels tied high, totalcurrent flow through the off channelsis again measured. The two cases
considered for determining on channel leakage current are the same except total current flow through the selected channel is measured.

Note 14: A 40% to 60% dutycycle range insures proper operation at all clock frequencies. In thecase that an available clock hasa duty cycle outside of theselimits
the minimum time the clock is high or low must be at least 450 ns. The maximum time the clock can be high or low is 100 µs.

Note 15: Since data, MSB first, istheoutput of the comparator used in the successive approximationloop,an additional delay is built in (see Block Diagram)toallow
for comparator response time.

Note 16: For the ADC08032 V

= 125˚C. The typical thermal resistances (θJA) of these parts when board mounted follow: ADC08031 and ADC08032 with BIN and CIN suffixes

JMAX

= 25˚C and represent the most likely parametric norm.

J

≥ V

IN(−)

the digital code will be 0000 0000. Twoon-chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct for

IN(+)

does not exceed the supply voltage by more than 50 mV, the output code will be correct. Ex-

IN

over temperature variations, initial tolerance and loading.

DC

) and the remaining seven off channels tied low (0 VDC), total current flow through the off chan-

DC

IN is internally tied to VCC, therefore, for the ADC08032 reference current is included in the supply current.

REF

supply.During testing at low VCClevels (e.g., 4.5V), high level analog inputs

CC

to5VDCinput voltage range will there-

DC

Typical Performance Characteristics

ADC08031/ADC08032/ADC08034/ADC08038

Linearity Error vs
Reference Voltage

Power Supply Current vs
Temperature (ADC08038,
ADC08034, ADC08031)

DS010555-32

Linearity Error vs
Temperature

Output Current vs
Temperature

DS010555-33

Linearity Error vs
Clock Frequency

DS010555-34

Power Supply Current
vs Clock Frequency

Note: For ADC08032 add I

REF

DS010555-35

DS010555-36

DS010555-37

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Leakage Current Test Circuit

TRI-STATE Test Circuits and Waveforms

ADC08031/ADC08032/ADC08034/ADC08038

t

1H

DS010555-7

Timing Diagrams

DS010555-38

t

0H

DS010555-40

DS010555-39

DS010555-41

Data Input Timing

*To reset these devices, CLK and CS must be simultaneously high for a period of t
standards ADC0831/2/4/8.

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DS010555-10

or greater. Otherwise these devices are compatible with industry

SELECT

Timing Diagrams (Continued)

ADC08031/ADC08032/ADC08034/ADC08038

Data Output Timing

DS010555-11

ADC08031 Start Conversion Timing

ADC08031 Timing

*LSB first output not available on ADC08031.
LSB information is maintained for remainder of clock periods until CS goes high.

ADC08032 Timing

DS010555-12

DS010555-13

DS010555-14

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Timing Diagrams (Continued)

ADC08031/ADC08032/ADC08034/ADC08038

ADC08034 Timing

DS010555-15

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Timing Diagrams (Continued)

ADC08031/ADC08032/ADC08034/ADC08038

DS010555-16

ADC08038 Timing

18 clocks in the LSB before SE is taken low

#

*Make sure clock edge

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ADC08038 Functional Block Diagram

ADC08031/ADC08032/ADC08034/ADC08038

DS010555-17

Functional Description

1.0 MULTIPLEXER ADDRESSING

The design of these converters utilizes a comparator struc­ture with built-in sample-and-hold which provides for a differ­ential analog input to be converted by a successive­approximation routine.

The actual voltage converted is always the difference be­tween an assigned“+” input terminal and a“−” input terminal.
The polarity of each input terminal of the pair indicates which
line the converter expects to be the most positive. If the as­signed “+” input voltage is less than the “−” input voltage the
converter responds with an all zeros output code.

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For the ADC08034, the “SEL 1” Flip-Flop is bypassed, for the ADC08032, both “SEL 0” and “SEL 1” Flip-Flops are bypassed.

*Some of these functions/pins are not available with other options.

A unique input multiplexing scheme has been utilized to pro­vide multiple analog channels with software-configurable
single-ended, differential, or pseudo-differential (which will
convert the difference between the voltage at any analog in­put and a common terminal) operation. The analog signal
conditioning required in transducer-based data acquisition
systems is significantly simplified with this type of input flex­ibility. One converter package can now handle ground refer­enced inputs and true differential inputs as well as signals
with some arbitrary reference voltage.

A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be

Functional Description (Continued)

enabled and whetherthis input issingle-ended or differential.
Differential inputs are restricted to adjacent channel pairs.
For example,channel 0 and channel 1 may be selected as a
differential pair but channel 0 or 1 cannot act differentially
with any other channel. In addition to selecting differential
mode the polarity may also be selected. Channel 0 may be
selected as the positive input and channel 1 as the negative
input or viceversa. This programmabilityis best illustratedby
the MUX addressing codes shown in the following tables for
the various product options.

The MUX address is shifted into the converter via the DIline.
Because the ADC08031 contains only one differential input
channel with a fixed polarity assignment, it does not require
addressing.

The common input line (COM) on the ADC08038 can be
used as a pseudo-differential input. In this mode the voltage
on this pin is treated as the“−” input for any of the otherinput

TABLE 2. MUX Addressing: ADC08038

Single-Ended MUX Mode

MUX Address Analog Single-Ended Channel

START SGL/ ODD/ SELECT 01234567COM

DIF

11000+ −
11001 + −
11010 + −
11011 + −
11100 + −
11101 + −
11110 + −
11111 +−

SIGN 1 0

channels. This voltage does not have to be analog ground; it
can be any reference potential which is common to all of the
inputs. This feature is most useful in single-supply applica­tions where the analog circuity may be biased up to a poten­tial other than ground and the output signals are all referred
to this potential.

TABLE 1. Multiplexer/Package Options

Part

Number

ADC08031 1 1 8
ADC08032 2 1 8
ADC08034 4 2 14
ADC08038 8 4 20

Number of Analog

Channels

Single-Ended Differential

#

Number of

Package

Pins

ADC08031/ADC08032/ADC08034/ADC08038

TABLE 3. MUX Addressing: ADC08038

Differential MUX Mode

MUX Address Analog Differential Channel-Pair

START SGL/ ODD/ SELECT 0123

DIF

10000+−
10001 +−
10010 +−
10011 +−
10100−+
10101 −+
10110 −+
10111 −+

SIGN 1001234567

#

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Functional Description (Continued)

TABLE 4. MUX Addressing: ADC08034

Single-Ended MUX Mode

MUX Address Channel

START SGL/ ODD/ SELECT 0123

DIF

110 0+
110 1 +
111 0 +
111 1 +

COM is internally tied to AGND

SIGN 1

MUX Addressing:
ADC08032

ADC08031/ADC08032/ADC08034/ADC08038

Single-Ended MUX Mode

MUX Address Channel

START SGL/ ODD/ 0 1

110+
111 +

COM is internally tied to AGND

Differential MUX Mode

MUX Address Channel

START SGL/ ODD/ SELECT 0123

DIF

100 0+−
100 1 +−
101 0−+
101 1 −+

SIGN 1

DIF

#

#

SIGN

#

Differential MUX Mode

MUX Address Channel

START SGL/ ODD/ 0 1

DIF

SIGN

100+−
101−+

Since the input configuration is under software control, it can
be modified as required before each conversion. A channel
can be treated as a single-ended, ground referenced input
for one conversion; then it can be reconfigured as part of a
differential channel for another conversion.
trates the input flexibility which can be achieved.

The analog input voltages for each channel can range from
50mV below ground to 50mV above V
out degrading conversion accuracy.

2.0 THE DIGITAL INTERFACE

A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system im­provements; it allows many functions to be included in a
small package and it can eliminate the transmission of low

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Figure 1

(typically 5V) with-

CC

illus-

#

level analog signals by locating the converter right at the
analog sensor; transmitting highly noise immune digital data
back to the host processor.

To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate timing diagram is shown for each device.

1. A conversion is initiated by pulling the CS (chip select)
line low. This line must be held low for the entire conver­sion. The converter is now waiting for a start bit and its
MUX assignment word.

2. Oneach risingedge of the clock the status of the datain
(DI) line is clocked into the MUX address shift register.
The start bit is the first logic “1” that appears on this line
(all leading zeros are ignored). Following the start bit the
converter expects the next 2 to 4 bits to be the MUX as­signment word.

Functional Description (Continued)

3. Whenthe start bit hasbeen shiftedinto the start location
of the MUX register, the input channel has been as­signed and a conversion is about to begin. An interval of

1

⁄2clock period (wherenothing happens)is automatically
inserted to allow the selected MUX channel to settle.
The SARS linegoes high atthis time tosignal that a con­version is now in progress and the DI line is disabled (it
no longer accepts data).

4. The data out (DO) line now comes out of TRI-STATE
and provides a leading zero for this one clock period of
MUX settling time.

5. Duringthe conversionthe output of the SAR comparator
indicates whether the analog input is greater than (high)
or less than (low) a series of successive voltages gener­ated internally from a ratioed capacitor array (first 5 bits)
and a resistor ladder (last 3 bits).After each comparison
the comparator’s output is shipped to the DO line on the
falling edgeof CLK. This data is the result of the conver­sion being shifted out (with the MSB first) and can be
read by the processor immediately.

6. After 8 clock periods the conversion is completed. The
SARS line returnslow to indicatethis

1

⁄2clock cycle later.

7. Thestored data in the successive approximationregister
is loaded into an internal shift register.If the programmer
prefers the data can be provided in an LSB first format
[this makes use of the shift enable (SE) control line]. On
theADC08038 theSE lineis broughtout andif heldhigh
the value of the LSB remains valid on the DO line. When
SE is forced low the data is clocked out LSB first. On de­vices which do not include the SE control line, the data,
LSB first, is automatically shifted out the DO line after
the MSB first data stream. The DO line then goes low
and stays low until CS is returned high. The ADC08031
is an exception in that its data is only output in MSB first
format.

8. Allinternal registers are cleared when the CSline ishigh
and the t

requirement is met. See Data Input Tim-

SELECT

ing under Timing Diagrams. If another conversion is de­sired CS must make a high to low transition followed by
address information.

The DI and DO lines can be tied together and controlled
through a bidirectional processor I/O bit with one wire.
This is possible because the DI input is only “looked-at”
during the MUX addressing interval while the DO line is
still in a high impedance state.

ADC08031/ADC08032/ADC08034/ADC08038

8 Single-Ended

DS010555-48

4 Differential

8 Pseudo-Differential

DS010555-49

Mixed Mode

DS010555-50

FIGURE 1. Analog Input Multiplexer Options for the ADC08038

DS010555-51

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Functional Description (Continued)

3.0 REFERENCE CONSIDERATIONS

The voltage applied to the reference input on these convert­ers, V
(the difference between V
256 possible output codes apply. The devices can be used
either in ratiometric applications or in systems requiring ab­solute accuracy. The reference pin must be connected to a
voltage source capable of driving the reference input resis­tance which can be as low as 1.3kΩ. This pin is the top of a
resistor divider string and capacitor array used for the suc­cessive approximation conversion.

In a ratiometric system the analog input voltage is propor­tional to the voltage used for the A/D reference. This voltage
is typically the system power supply, so the V
be tied to V
nique relaxes the stability requirements of the system refer­ence as the analog input and A/D reference move together

ADC08031/ADC08032/ADC08034/ADC08038

maintaining the sameoutput code for a giveninput condition.

IN, defines the voltage span of the analog input

REF

(done internally on theADC08032). This tech-

CC

IN(MAX)

and V

IN(MIN)

over which the

IN pin can

REF

For absolute accuracy, where the analog input varies be­tween very specific voltage limits, the reference pin can be
biased with a time and temperature stable voltage source.
For the ADC08034 and the ADC08038 a band-gap derived
reference voltage of 2.6V (Note 8) is tied to V
can be tied back to V

IN. Bypassing V

REF

OUT. This

REF

OUT with a

REF

100µF capacitor is recommended. The LM385 and LM336
reference diodes are good low current devices to use with
these converters.

The maximum value of the reference is limited to the V

CC

supply voltage. The minimum value, however, can be quite
small (see Typical Performance Characteristics) to allow di­rect conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
noise pickup, circuit layoutand system error voltage sources
when operating with a reduced span due to the increased
sensitivity of the converter (1 LSB equals V

REF/

256).

DS010555-52

a) Ratiometric

FIGURE 2. Reference Examples

4.0 THE ANALOG INPUTS

The most important feature of these converters is that they
can be located right at the analog signal source and through
just a few wires can communicate with a controlling proces­sor with a highly noise immuneserial bitstream. This in itself
greatly minimizes circuitry to maintain analog signal accu­racy which otherwise is most susceptible to noise pickup.
However, a few words are in order with regard to the analog
inputs should the input be noisy to begin with or possibly
riding on a large common-mode voltage.

The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected “+” and “−” inputs for a conversion (60 Hz is
most typical). The time interval between sampling the “+” in­put and then the “−” input is

1

⁄2of a clock period.The change
in the common-mode voltage during this short time interval
can cause conversion errors. For a sinusoidal
common-mode signal this error is:

where fCMis the frequency of the common-mode signal,

DS010555-53

b) Absolute with a Reduced Span

is its peak voltage value

V

PEAK

and f

For a 60Hz common-mode signal to generate a

is the A/D clock frequency.

CLK

1

(≈5mV) with the converter running at 250kHz, its peak value
would have to be 6.63V which would be larger than allowed
as it exceeds the maximum analog input limits.

Source resistance limitation is important with regard to the
DC leakage currents ofthe input multiplexer. Bypass capaci­tors should not be used if the source resistance is greater
than 1kΩ. Theworst-case leakage current of

±

1µAover tem­perature will create a 1mV input error with a 1kΩ source re­sistance. An op amp RC active low pass filter can provide
both impedance buffering and noise filtering should a high
impedance signal source be required.

5.0 OPTIONAL ADJUSTMENTS

5.1 Zero Error

The zero of the A/D does not require adjustment. If the mini­mum analog input voltage value, V

, is not ground a

IN(MIN)

zero offset can be done. The converter can be made to out-

⁄4LSB error

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Functional Description (Continued)

put 0000 0000 digital code for this minimum input voltage by
biasing any V
the differential mode operation of the A/D.

The zero error of the A/D converter relates to the location of
the first riserof thetransfer function andcan bemeasured by
grounding the V
positive voltage to the V
ence between the actual DC input voltage which is neces­sary to just cause an output digital code transition from 0000
0000 to 0000 0001 and the ideal

9.8mV for V

(−) input at this V

IN

(−) input and applying a small magnitude

IN

= 5.000VDC).

REF

(+) input. Zero error is the differ-

IN

value. This utilizes

IN(MIN)

1

⁄2LSB value (1⁄2LSB =

should be properly adjusted first. A V
equals this desired zero reference plus

(+) voltage which

IN

1

⁄2LSB (where the
LSB is calculated for thedesired analog span, using 1 LSB =
analog span/256) is applied to selected “+” input and the
zero reference voltage at the corresponding “−” input should
then be adjusted to just obtain the 00

HEX

to 01

HEX

code tran-

sition.
The full-scale adjustment should be made [with the proper

V

(−) voltage applied] by forcing a voltage to the VIN(+) in-

IN

put which is given by:

ADC08031/ADC08032/ADC08034/ADC08038

5.2 Full Scale

The full-scale adjustment can be made by applying a differ­ential input voltage which is 1

1

⁄2LSB down from the desired
analog full-scale voltage range and then adjusting the mag­nitude of the V

IN input (or VCCfor the ADC08032) for a

REF

digital output code which is just changing from 1111 1110 to
1111 1111.

5.3 Adjusting for an Arbitrary Analog Input
Voltage Range

If the analog zero voltage of the A/D is shifted away from
ground (for example,to accommodate an analog inputsignal
which does not go to ground), this new zero reference

where:

V

= the high end of the analog input range

MAX

and

V

= the low end (the offset zero) of the analog range.

MIN

(Both are ground referenced.)
The V

code change from FE

IN (or VCC) voltage is then adjusted to provide a

REF

HEX

to FF

. This completes the ad-

HEX

justment procedure.

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Applications

A “Stand-Alone” Hook-Up for ADC08038 Evaluation

ADC08031/ADC08032/ADC08034/ADC08038

*Pinouts shown for ADC08038.
For all other products tie to pin functions as shown.

Low-Cost Remote Temperature Sensor

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DS010555-44

DS010555-45

Applications (Continued)

ADC08031/ADC08032/ADC08034/ADC08038

Digitizing a Current Flow

DS010555-22

Operating with Ratiometric Transducers

*VIN(−) = 0.15 V
15% of VCC≤ V

CC

XDR

≤ 85% of V

DS010555-23

CC

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Applications (Continued)

Span Adjust; 0V ≤ V

ADC08031/ADC08032/ADC08034/ADC08038

Zero-Shift and Span Adjust: 2V ≤ VIN≤ 5V

IN

≤ 3V

DS010555-46

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DS010555-47

Applications (Continued)

ADC08031/ADC08032/ADC08034/ADC08038

Diodes are 1N914

Protecting the Input

DS010555-25

Digital Load Cell

DO = all 1s if +V
DO = all 0s if +V

High Accuracy Comparators

>

−V

IN

IN

<

−V

IN

IN

DS010555-26

Uses one more wire than load cell itself

•

Two mini-DIPs could be mounted inside load cell for digital output transducer

•

Electronic offset and gain trims relax mechanical specs for gauge factor and offset

•

Low level cell output is converted immediately for high noise immunity

•

DS010555-27

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Applications (Continued)

4 mA-20 mA Current Loop Converter

ADC08031/ADC08032/ADC08034/ADC08038

All power supplied by loop

•

1500V isolation at output

•

DS010555-28

www.national.com 20

Applications (Continued)

ADC08031/ADC08032/ADC08034/ADC08038

Isolated Data Converter

No power required remotely

•

1500V isolation

•

DS010555-29

www.national.com21

Physical Dimensions inches (millimeters) unless otherwise noted

ADC08031/ADC08032/ADC08034/ADC08038

Order Number ADC08031CIWM, ADC08032CIWM, or ADC08034CIWM

NS Package Number M14B

www.national.com 22

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

ADC08031/ADC08032/ADC08034/ADC08038

Order Number ADC08038CIWM

NS Package Number M20B

Order Number ADC08031CIN

NS Package Number N08E

www.national.com23

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Order Number ADC08038CIN

NS Package Number N20A

Multiplexer Options, Voltage Reference, and Track/Hold Function

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whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.

National Semiconductor

ADC08031/ADC08032/ADC08034/ADC08038 8-Bit High-Speed Serial I/O A/D Converters with

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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