National Semiconductor ADC08031, ADC08032, ADC08034, ADC08038 Technical data

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ADC08031/ADC08032/ADC08034/ADC08038
8-Bit High-Speed Serial I/O A/D Converters with
Multiplexer Options, Voltage Reference, and Track/Hold
Function

June 2000

ADC08031/ADC08032/ADC08034/ADC08038 8-Bit High-Speed Serial I/O A/D Converters with

Multiplexer Options, Voltage Reference, and Track/Hold Function

General Description

The ADC08031/ADC08032/ADC08034/ADC08038 are 8-bit
successive approximationA/D converters with serial I/O and
configurable input multiplexers with up to 8 channels. The
serial I/O is configured to comply with the NSC MICROW-

™

IRE

serial data exchangestandard for easy interface tothe

™

COPS
standard shift registers or microprocessors.

TheADC08034 and ADC08038 provide a 2.6V band-gap de­rived reference. For devices offeringguaranteed voltage ref­erence performance over temperature see ADC08131,
ADC08134 and ADC08138.

Atrack/hold function allowsthe analog voltage at thepositive
input to vary during the actual A/D conversion.

The analog inputs can be configured to operate in various
combinations of single-ended, differential, or
pseudo-differential modes. In addition, input voltage spans
as small as 1V can be accommodated.

family of controllers, and can easily interface with

Applications

n Digitizing automotive sensors
n Process control monitoring
n Remote sensing in noisy environments
n Instrumentation

Ordering Information

n Test systems
n Embedded diagnostics

Features

n Serial digital data link requires few I/O pins
n Analog input track/hold function
n 2-, 4-, or 8-channel input multiplexer options with

address logic

n 0V to 5V analog input range with single 5V power

supply

n No zero or full scale adjustment required
n TTL/CMOS input/output compatible
n On chip 2.6V band-gap reference
n 0.3" standard width 8-, 14-, or 20-pin DIP package
n 14-, 20-pin small-outline packages

Key Specifications

n Resolution: 8 bits
n Conversion time (f
n Power dissipation: 20mW (max)
n Single supply: 5V
n Total unadjusted error:
n No missing codes over temperature

= 1 MHz): 8µs (max)

C

(±5%)

DC

1

±

⁄2LSB and±1LSB

Industrial (−40˚C ≤ TA≤ +85˚C) Package

ADC08031CIN* N08E
ADC08038CIN* N20A
ADC08031CIWM,
ADC08032CIWM, M14B
ADC08034CIWM
ADC08038CIWM M20B

*

Not recomended for new designs.

COPS™microcontrollers and MICROWIRE™are trademarks of National Semiconductor Corporation.

© 2000 National Semiconductor Corporation DS010555 www.national.com

Connection Diagrams

ADC08038

ADC08031/ADC08032/ADC08034/ADC08038

DS010555-2

ADC08031

Dual-In-Line Package

ADC08034

DS010555-3

ADC08032

Small Outline Package

ADC08031

Small Outline Package

DS010555-31

DS010555-5

DS010555-30

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ADC08031/ADC08032/ADC08034/ADC08038

Absolute Maximum Ratings (Notes 1, 3)

Storage Temperature −65˚C to +150˚C

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V
Voltage at Inputs and Outputs −0.3V to V
Input Current at Any Pin (Note 4)
Package Input Current (Note 4)
Power Dissipation at T

) 6.5V

CC

CC

±

= 25˚C

A

+ 0.3V

±

5mA

20 mA

(Note 5) 800 mW
ESD Susceptibility (Note 6) 1500V
Soldering Information

N Package (10 sec.)

235˚C

SO Package:

Vapor Phase (60 sec.)
Infrared (15 sec.) (Note 7)

215˚C
220˚C

Operating Ratings (Notes 2, 3)

Temperature Range T
ADC08031BIN, ADC08031CIN, −40˚C ≤ TA≤ +85˚C
ADC08032BIN, ADC08032CIN,
ADC08034BIN, ADC08034CIN,
ADC08038BIN, ADC08038CIN,
ADC08031BIWM, ADC08032BIWM,
ADC08034BIWM, ADC08038BIWM
ADC08031CIWM, ADC08032CIWM,
ADC08034CIWM, ADC08038CIWM
Supply Voltage (V

) 4.5 VDCto 6.3 V

CC

MIN

≤ TA≤ T

Electrical Characteristics

The following specifications apply for VCC=V

apply for TA=TJ=T

MIN

to T

; all other limits TA=TJ= 25˚C.

MAX

Symbol Parameter Conditions Typical Limits Units

CONVERTER AND MULTIPLEXER CHARACTERISTICS

Total Unadjusted Error (Note 10)

BIN, BIWM

CIN, CIWM
Differential 8 Bits (min)
Linearity

R

REF

V

IN

Reference Input Resistance (Note 11) 3.5 kΩ

Analog Input Voltage (Note 12) (VCC+ 0.05) V (max)

DC Common-Mode Error
Power Supply Sensitivity V

On Channel Leakage On Channel = 5V, 0.2 µA (max)
Current (Note 13) Off Channel = 0V 1

Off Channel Leakage On Channel = 5V, −0.2 µA (max)
Current (Note 13) Off Channel = 0V −1

DIGITAL AND DC CHARACTERISTICS

V
V
I
I
V

V

IN(1)
IN(0)

IN(1)
IN(0)

OUT(1)

OUT(0)

Logical “1” Input Voltage VCC= 5.25V 2.0 V (min)
Logical “0” Input Voltage VCC= 4.75V 0.8 V (max)
Logical “1” Input Current VIN= 5.0V 1 µA (max)
Logical “0” Input Current VIN=0V −1 µA (max)
Logical “1” Output Voltage VCC= 4.75V:

Logical “0” Output Voltage VCC= 4.75V 0.4 V (max)

=+5VDC, and f

REF

= 1 MHz unless otherwise specified. Boldface limits

CLK

(Note 8) (Note 9) (Limits)

1

±

⁄

2

±

1 LSB (max)

LSB (max)

1.3 kΩ (min)

6.0 kΩ (max)

(GND − 0.05) V (min)

1

±

⁄

CC

V

REF

=5V±5%,

= 4.75V

4

1

±

⁄

4

LSB (max)
LSB (max)

On Channel = 0V, −0.2 µA (max)
Off Channel = 5V −1

On Channel = 0V, 0.2 µA (max)
Off Channel = 5V 1

I

= −360 µA 2.4 V (min)

OUT

I

= −10 µA 4.5 V (min)

OUT

I

= 1.6 mA

OUT

MAX

DC

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Electrical Characteristics (Continued)

The following specifications apply for VCC=V

apply for TA=TJ=T

MIN

to T

; all other limits TA=TJ= 25˚C.

MAX

Symbol Parameter Conditions Typical Limits Units

DIGITAL AND DC CHARACTERISTICS

I

OUT

I

SOURCE

I

SINK

I

CC

TRI-STATE®Output Current V

Output Source Current V
Output Sink Current V
Supply Current

ADC08031, ADC08034, CS = HIGH
and ADC08038
ADC08032 (Note 16) 7.0 mA (max)

REFERENCE CHARACTERISTICS

ADC08031/ADC08032/ADC08034/ADC08038

V

OUT Nominal Reference Output V

REF

=+5VDC, and f

REF

= 1 MHz unless otherwise specified. Boldface limits

CLK

(Note 8) (Note 9) (Limits)

=0V −3.0 µA (max)

OUT

V

=5V 3.0 µA (max)

OUT

=0V −6.5 mA (min)

OUT
OUT=VCC

8.0 mA (min)

3.0 mA (max)

OUT Option

REF

Available Only on 2.6 V
ADC08034 and

ADC08038

Electrical Characteristics

The following specifications apply for VCC=V

apply for TA=TJ=T

MIN

to T

; all other limits TA=TJ= 25˚C.

MAX

Symbol Parameter Conditions Typical Limits Units

f

CLK

Clock Frequency 10 kHz (min)

Clock Duty Cycle 40 % (min)
(Note 14) 60 % (max)

T

C

Conversion Time (Not Including f
MUX Addressing Time) 8 µs (max)

t

CA

t

SELECT

t

SET-UP

Acquisition Time
CLK High while CS is High 50 ns
CS Falling Edge or Data Input 25 ns (min)
Valid to CLK Rising Edge

t

HOLD

Data Input Valid after CLK 20 ns (min)
Rising Edge

t

pd1,tpd0

CLK Falling Edge to Output CL= 100 pF:
Data Valid (Note 15) Data MSB First 250 ns (max)

t

1H,t0H

TRI-STATE Delay from Rising Edge CL= 10 pF, RL=10kΩ 50 ns
of CS to Data Output and SARS Hi-Z

C

IN

C

OUT

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed speci-

fications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance character­istics may degrade when the device is not operated under the listed test conditions.

Note 3: All voltages are measured with respect to AGND = DGND = 0 V
Note 4: When the input voltage V

The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

allowable power dissipation at any temperature is P

Capacitance of Logic Inputs 5 pF
Capacitance of Logic Outputs 5 pF

at any pin exceeds the power supplies (V

IN

=(T

D

=+5VDC, and tr=tf= 20 ns unless otherwise specified. Boldface limits

REF

(Note 8) (Note 9) (Limits)

1 MHz (max)

= 1 MHz 8 1/f

CLK

1

⁄

2

Data LSB First 200 ns (max)

(see TRI-STATE Test Circuits)
C

= 100 pF, RL=2kΩ 180 ns (max)

L

, unless otherwise specified.

DC

<

(AGND or DGND) or V

IN

)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower. For these de-

JMAX−TA

>

VCC) the current at that pin should be limited to 5 mA.

IN

, θJAand the ambient temperature, TA. The maximum

JMAX

1/f

CLK

CLK

(max)

(max)

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Electrical Characteristics (Continued)

vices, T
120˚C/W,ADC08038withCINsuffix80˚C/W. ADC08031 with CIWM suffix 140˚C/W, ADC08032 140˚C/W,ADC08034140˚C/W, ADC08038 with CIWM suffix 91˚C/W.

Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kΩ resistor.
Note 7: See AN450 “Surface MountingMethods and Their Effect on Product Reliability” or Linear DataBook section “Surface Mount” for other methods of soldering

surface mount devices.

Note 8: Typicals are at T
Note 9: Guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Total unadjusted error includes offset, full-scale, linearity, multiplexer.
Note 11: Cannot be tested for the ADC08032.
Note 12: For V

analog input voltages one diode drop below groundor one diode drop greater than V
(e.g., 5V) can cause an input diode to conduct, especially atelevated temperatures, which willcause errors for analog inputs near full-scale. Thespec allows 50 mV
forward bias of either diode; this means that as long as the analog V
ceeding this range on an unselected channelwillcorrupt the reading of a selected channel. Achievement of an absolute 0V
fore require a minimum supply voltage of 4.950 V

Note 13: Channel leakage currentis measured after a single-ended channelis selected and the clock isturned off. For off channel leakage currentthe following two
cases are considered: one, with the selected channel tied high(5 V
nels is measured; two, withthe selected channel tied low and the off channels tied high, totalcurrent flow through the off channelsis again measured. The two cases
considered for determining on channel leakage current are the same except total current flow through the selected channel is measured.

Note 14: A 40% to 60% dutycycle range insures proper operation at all clock frequencies. In thecase that an available clock hasa duty cycle outside of theselimits
the minimum time the clock is high or low must be at least 450 ns. The maximum time the clock can be high or low is 100 µs.

Note 15: Since data, MSB first, istheoutput of the comparator used in the successive approximationloop,an additional delay is built in (see Block Diagram)toallow
for comparator response time.

Note 16: For the ADC08032 V

= 125˚C. The typical thermal resistances (θJA) of these parts when board mounted follow: ADC08031 and ADC08032 with BIN and CIN suffixes

JMAX

= 25˚C and represent the most likely parametric norm.

J

≥ V

IN(−)

the digital code will be 0000 0000. Twoon-chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct for

IN(+)

does not exceed the supply voltage by more than 50 mV, the output code will be correct. Ex-

IN

over temperature variations, initial tolerance and loading.

DC

) and the remaining seven off channels tied low (0 VDC), total current flow through the off chan-

DC

IN is internally tied to VCC, therefore, for the ADC08032 reference current is included in the supply current.

REF

supply.During testing at low VCClevels (e.g., 4.5V), high level analog inputs

CC

to5VDCinput voltage range will there-

DC

Typical Performance Characteristics

ADC08031/ADC08032/ADC08034/ADC08038

Linearity Error vs
Reference Voltage

Power Supply Current vs
Temperature (ADC08038,
ADC08034, ADC08031)

DS010555-32

Linearity Error vs
Temperature

Output Current vs
Temperature

DS010555-33

Linearity Error vs
Clock Frequency

DS010555-34

Power Supply Current
vs Clock Frequency

Note: For ADC08032 add I

REF

DS010555-35

DS010555-36

DS010555-37

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Leakage Current Test Circuit

TRI-STATE Test Circuits and Waveforms

ADC08031/ADC08032/ADC08034/ADC08038

t

1H

DS010555-7

Timing Diagrams

DS010555-38

t

0H

DS010555-40

DS010555-39

DS010555-41

Data Input Timing

*To reset these devices, CLK and CS must be simultaneously high for a period of t
standards ADC0831/2/4/8.

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DS010555-10

or greater. Otherwise these devices are compatible with industry

SELECT

Timing Diagrams (Continued)

ADC08031/ADC08032/ADC08034/ADC08038

Data Output Timing

DS010555-11

ADC08031 Start Conversion Timing

ADC08031 Timing

*LSB first output not available on ADC08031.
LSB information is maintained for remainder of clock periods until CS goes high.

ADC08032 Timing

DS010555-12

DS010555-13

DS010555-14

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Timing Diagrams (Continued)

ADC08031/ADC08032/ADC08034/ADC08038

ADC08034 Timing

DS010555-15

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