National Semiconductor ADC0801, ADC0802, ADC0803, ADC0804, ADC0805 Technical data

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805
8-Bit µP Compatible A/D Converters

General Description

The ADC0801, ADC0802, ADC0803, ADC0804 and
ADC0805 are CMOS 8-bit successive approximation A/D
converters that use a differential potentiometric
ladder—similar to the 256R products. These converters are
designed to allowoperation with the NSC800 and INS8080A
derivative control buswith TRI-STATE output latchesdirectly
driving the data bus. These A/Ds appear like memory loca­tions or I/O ports to the microprocessor and no interfacing
logic is needed.

Differential analog voltage inputs allow increasing the
common-mode rejection and offsetting the analog zero input
voltage value. Inaddition, the voltage reference inputcan be
adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.

Features

n Compatible with 8080 µP derivatives—no interfacing

logic needed - access time - 135 ns

n Easy interface to all microprocessors, or operates “stand

alone”

n Differential analog voltage inputs
n Logic inputs and outputs meet both MOS and TTL

voltage level specifications

n Works with 2.5V (LM336) voltage reference
n On-chip clock generator
n 0V to 5V analog input voltage range with single 5V

supply

n No zero adjust required
n 0.3" standard width 20-pin DIP package
n 20-pin molded chip carrier or small outline package
n Operates ratiometrically or with 5 V

analog span adjusted voltage reference

Key Specifications

n Resolution 8 bits
n Total error
n Conversion time 100 µs

1

±

⁄4LSB,

November 1999

, 2.5 VDC,or

DC

1

±

⁄2LSB and±1 LSB

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 8-Bit µP Compatible A/D Converters

Connection Diagram

Ordering Information

TEMP RANGE 0˚C TO 70˚C 0˚C TO 70˚C −40˚C TO +85˚C

1

±

⁄4Bit Adjusted ADC0801LCN

1

ERROR

±

⁄2Bit Unadjusted ADC0802LCWM ADC0802LCN

1

±

⁄2Bit Adjusted ADC0803LCN

±

1Bit Unadjusted ADC0804LCWM ADC0804LCN ADC0805LCN/ADC0804LCJ

PACKAGE OUTLINE M20B—Small

ADC080X

Dual-In-Line and Small Outline (SO) Packages

DS005671-30

See Ordering Information

N20A—Molded DIP

Outline

Z-80®is a registered trademark of Zilog Corp.

© 2001 National Semiconductor Corporation DS005671 www.national.com

Typical Applications

8080 Interface

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805

DS005671-1

DS005671-31

Error Specification (Includes Full-Scale,

Zero Error, and Non-Linearity)

Part Full- V

/2=2.500 V

REF

V

DC

/2=No Connection

REF

Number Scale (No Adjustments) (No Adjustments)

Adjusted

1

ADC0801
ADC0802
ADC0803
ADC0804
ADC0805

±

1

±

⁄4LSB

⁄2LSB

1

±

±

⁄2LSB

1 LSB

±

1 LSB

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ADC0801/ADC0802/ADC0803/ADC0804/ADC0805

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,
please contactthe National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V
Voltage

Logic Control Inputs −0.3V to +18V
At Other Input and Outputs −0.3V to (V

Lead Temp. (Soldering, 10 seconds)

Dual-In-Line Package (plastic) 260˚C
Dual-In-Line Package (ceramic) 300˚C
Surface Mount Package

) (Note 3) 6.5V

CC

CC

+0.3V)

Infrared (15 seconds) 220˚C
Storage Temperature Range −65˚C to +150˚C
Package Dissipation at T

=25˚C 875 mW

A

ESD Susceptibility (Note 10) 800V

Operating Ratings (Notes 1, 2)

Temperature Range T

ADC0804LCJ −40˚C≤TA≤+85˚C
ADC0801/02/03/05LCN −40˚C≤T
ADC0804LCN 0˚C≤T
ADC0802/04LCWM 0˚C≤T

Range of V

CC

4.5 VDCto 6.3 V

Vapor Phase (60 seconds) 215˚C

Electrical Characteristics

The following specifications apply for VCC=5 VDC,T

MIN≤TA≤TMAX

Parameter Conditions Min Typ Max Units

ADC0801: Total Adjusted Error (Note 8) With Full-Scale Adj.

(See Section 2.5.2)

ADC0802: Total Unadjusted Error (Note 8) V

/2=2.500 V

REF

ADC0803: Total Adjusted Error (Note 8) With Full-Scale Adj.

(See Section 2.5.2)
ADC0804: Total Unadjusted Error (Note 8) V
ADC0805: Total Unadjusted Error (Note 8) V
V

/2 Input Resistance (Pin 9) ADC0801/02/03/05 2.5 8.0 kΩ

REF

/2=2.500 V

REF

/2-No Connection

REF

ADC0804 (Note 9) 0.75 1.1 kΩ
Analog Input Voltage Range (Note 4) V(+) or V(−) Gnd–0.05 V
DC Common-Mode Error Over Analog Input Voltage

Range
Power Supply Sensitivity V

CC

=5 V

DC

Allowed V

Voltage Range (Note 4)

and f

DC

DC

±

10% Over

(+) and VIN(−)

IN

=640 kHz unless otherwise specified.

CLK

±

1/16

±

1/16

1

±

⁄

4

1

±

⁄

2

1

±

⁄

2

±

1 LSB

±

1 LSB

+0.05 V

CC

1

±

⁄

8

1

±

⁄

8

MIN≤TA≤TMAX

≤+85˚C

A

≤+70˚C

A

≤+70˚C

A

LSB

LSB
LSB

DC

LSB

LSB

DC

AC Electrical Characteristics

The following specifications apply for VCC=5 VDCand T

MIN≤TA≤TMAX

Symbol Parameter Conditions Min Typ Max Units

T
T
f

C
C

CLK

Conversion Time f

CLK

Conversion Time (Notes 5, 6) 66 73 1/f
Clock Frequency VCC=5V, (Note 5) 100 640 1460 kHz
Clock Duty Cycle 40 60 %

CR Conversion Rate in Free-Running INTR tied to WR with

Mode CS =0 V

t

W(WR)L

t

ACC

Width of WR Input (Start Pulse Width) CS =0 VDC(Note 7) 100 ns
Access Time (Delay from Falling CL=100 pF 135 200 ns
Edge of RD to Output Data Valid)

t1H,t

0H

TRI-STATE Control (Delay CL=10 pF, RL=10k 125 200 ns
from Rising Edge of RD to

(See TRI-STATE Test

Hi-Z State) Circuits)

t

WI,tRI

Delay from Falling Edge 300 450 ns
of WR or RD to Reset of INTR

C

IN

Input Capacitance of Logic 5 7.5 pF
Control Inputs

unless otherwise specified.

=640 kHz (Note 6) 103 114 µs

8770 9708 conv/s

DC,fCLK

=640 kHz

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CLK

AC Electrical Characteristics (Continued)

The following specifications apply for VCC=5 VDCand T

MIN≤TA≤TMAX

Symbol Parameter Conditions Min Typ Max Units

C

OUT

TRI-STATE Output 5 7.5 pF

Capacitance (Data Buffers)
CONTROL INPUTS [Note: CLK IN (Pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately]
V

(1) Logical “1” Input Voltage VCC=5.25 V

IN

(Except Pin 4 CLK IN)
V

(0) Logical “0” Input Voltage VCC=4.75 V

IN

(Except Pin 4 CLK IN)
I

(1) Logical “1” Input Current VIN=5 V

IN

(All Inputs)
I

(0) Logical “0” Input Current VIN=0 V

IN

(All Inputs)

CLOCK IN AND CLOCK R

V

+ CLK IN (Pin 4) Positive Going 2.7 3.1 3.5 V

T

Threshold Voltage
V

− CLK IN (Pin 4) Negative 1.5 1.8 2.1 V

T

Going Threshold Voltage
V

H

CLK IN (Pin 4) Hysteresis 0.6 1.3 2.0 V

(VT+)−(VT−)
V

(0) Logical “0” CLK R Output IO=360 µA 0.4 V

OUT

Voltage VCC=4.75 V
V

(1) Logical “1” CLK R Output IO=−360 µA 2.4 V

OUT

Voltage VCC=4.75 V

DATA OUTPUTS AND INTR

V

(0) Logical “0” Output Voltage

OUT

Data Outputs I

INTR Output I
V

(1) Logical “1” Output Voltage IO=−360 µA, VCC=4.75 V

OUT

V

(1) Logical “1” Output Voltage IO=−10 µA, VCC=4.75 V

OUT

I

OUT

TRI-STATE Disabled Output V

Leakage (All Data Buffers) V
I

SOURCE

I

SINK

V
V

OUT
OUT

OUT
OUT
OUT
OUT

POWER SUPPLY

I

CC

Supply Current (Includes f

Ladder Current) V

CLK

REF

and CS =5V
ADC0801/02/03/04LCJ/05 1.1 1.8 mA
ADC0804LCN/LCWM 1.9 2.5 mA

Note 1: Absolute MaximumRatings indicatelimits beyond which damage tothe devicemay occur. DCandAC electricalspecifications do not apply whenoperating
the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The separate A Gnd point should always be wired to the D Gnd.
Note 3: A zener diode exists, internally, from V

CC

unless otherwise specified.

DC

DC

DC

DC

DC

DC

=1.6 mA, VCC=4.75 V
=1.0 mA, VCC=4.75 V

=0 V

DC

=5 V

DC

DC
DC

DC

DC

2.0 15 V

0.8 V

0.005 1 µA

−1 −0.005 µA

0.4 V

0.4 V

2.4 V

4.5 V

−3 µA
3µA

Short to Gnd, TA=25˚C 4.5 6 mA
Short to VCC,TA=25˚C 9.0 16 mA

=640 kHz,

/2=NC, TA=25˚C

DC

DC

DC

DC

DC

DC

DC

DC

DC

DC
DC
DC
DC

DC
DC

DC
DC

AC Electrical Characteristics (Continued)

Note 7: The CS input is assumed to bracket the WRstrobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold

the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see timing diagrams).

Note 8: None of these A/Ds requires a zero adjust (see section 2.5.1). To obtain zero code at other analog input voltages see section 2.5 and
Note 9: The V

ADC0805, and in the ADC0804LCJ, each resistor is typically 16 kΩ. In all versions of the ADC0804 except the ADC0804LCJ, each resistor is typically 2.2 kΩ.
Note 10: Human body model, 100 pF discharged through a 1.5 kΩ resistor.

/2 pin is the center point of a two-resistor divider connected from VCCto ground. In all versions of the ADC0801, ADC0802, ADC0803, and

REF

Figure 7

.

Typical Performance Characteristics

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805

Logic Input Threshold Voltage
vs. Supply Voltage

DS005671-38

f

vs. Clock Capacitor

CLK

Delay From Falling Edge of
RD to Output Data Valid
vs. Load Capacitance

Full-Scale Error vs
Conversion Time

DS005671-39

CLK IN Schmitt Trip Levels
vs. Supply Voltage

DS005671-40

Effect of Unadjusted Offset Error
vs. V

/2 Voltage

REF

Output Current vs
Temperature

DS005671-41

DS005671-44

Power Supply Current
vs Temperature (Note 9)

DS005671-42

DS005671-45

Linearity Error at Low
V

/2 Voltages

REF

DS005671-43

DS005671-46

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TRI-STATE Test Circuits and Waveforms

t

1H

DS005671-47

t

0H

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805

DS005671-49

Timing Diagrams

(All timing is measured from the 50% voltage points)

t1H,CL=10 pF

DS005671-48

tr=20 ns

t0H,CL=10 pF

DS005671-50

tr=20 ns

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DS005671-51

Timing Diagrams (All timing is measured from the 50% voltage points) (Continued)

Output Enable and Reset with INTR

Note: Read strobe must occur 8 clock periods (8/f

) after assertion of interrupt to guarantee reset of INTR .

CLK

Typical Applications

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805

DS005671-52

6800 Interface

DS005671-53

Ratiometeric with Full-Scale Adjust

Note: before using caps at VINor V
see section 2.3.2 Input Bypass Capacitors.

REF

/2,

DS005671-54

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Typical Applications (Continued)

Absolute with a 2.500V Reference

DS005671-55

*For low power, see also LM385–2.5

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805

Zero-Shift and Span Adjust: 2V ≤ VIN≤ 5V

Absolute with a 5V Reference

DS005671-56

Span Adjust: 0V ≤ VIN≤ 3V

DS005671-57

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DS005671-58

Typical Applications (Continued)

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805

V

REF

/2=256 mV

Directly Converting a Low-Level Signal

1 mV Resolution with µP Controlled Range

DS005671-59

A µP Interfaced Comparator

For:

(+)>VIN(−)

V

IN

Output=FF
For:
V
Output=00

(+)<VIN(−)

IN

HEX

HEX

DS005671-60

V

/2=128 mV

REF

1 LSB=1 mV

≤(V

V

DAC≤VIN

<

0 ≤ V

DAC

DAC

2.5V

DS005671-61

+256 mV)

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Typical Applications (Continued)

Digitizing a Current Flow

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805

Self-Clocking Multiple A/Ds

* Use a large R value
to reduce loading
at CLK R output.

DS005671-63

100 kHz≤f

DS005671-62

External Clocking

≤1460 kHz

CLK

DS005671-64

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Typical Applications (Continued)

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805

Self-Clocking in Free-Running Mode

DS005671-65

*After power-up, a momentary grounding of the WR input is needed to
guarantee operation.

Operating with “Automotive” Ratiometric Transducers

µP Interface for Free-Running A/D

Ratiometric with V

/2 Forced

REF

DS005671-66

*VIN(−)=0.15 V
15% of VCC≤V

CC

XDR

≤85% of V

CC

µP Compatible Differential-Input Comparator with Pre-Set VOS(with or without Hysteresis)

*See

Figure 5

to select R value
DB7=“1” for V
Omit circuitry within the dotted area if
hysteresis is not needed

(+)>VIN(−)+(V

IN

REF

/2)

DS005671-67

DS005671-68

DS005671-69

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Typical Applications (Continued)

Handling

*Beckman Instruments#694-3-R10K resistor array

±

10V Analog Inputs

Low-Cost, µP Interfaced, Temperature-to-Digital

DS005671-70

µP Interfaced Temperature-to-Digital Converter

Converter

DS005671-71

*Circuit values shown are for 0˚C≤TA≤+128˚C

*

**

DS005671-72

Typical Applications (Continued)

ADC0801/ADC0802/ADC0803/ADC0804/ADC0805

Handling

*Beckman Instruments#694-3-R10K resistor array

±

µP Interfaced Comparator with Hysteresis

5V Analog Inputs

Read-Only Interface

DS005671-34

DS005671-33

Protecting the Input

DS005671-35

DS005671-9

Diodes are 1N914

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