National Semiconductor ADC0800 Technical data

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ADC0800 8-Bit A/D Converter

ADC0800 8-Bit A/D Converter

February 1995

General Description

The ADC0800 is an 8-bit monolithic A/D converter using P­channel ion-implanted MOS technology. It contains a high
input impedance comparator, 256 series resistors and ana­log switches, control logic and output latches. Conversion is
performed using a successive approximation technique
where the unknown analog voltage is compared to the re­sistor tie points using analog switches. When the appropri­ate tie point voltage matches the unknown voltage, conver­sion is complete and the digital outputs contain an 8-bit
complementary binary word corresponding to the unknown.
The binary output is TRI-STATE

to permit bussing on com-

É

mon data lines.

The ADC0800PD is specified over
the ADC0800PCD is specified over 0

b

55§Ctoa125§C and
Cto70§C.

§

Block Diagram

Features

Y

Low cost

Y

g

5V, 10V input ranges

Y

No missing codes

Y

Ratiometric conversion

Y

TRI-STATE outputs

Y

Fast T

Y

Contains output latches

Y

TTL compatible

Y

Supply voltages 5 VDCandb12 V

Y

Resolution 8 bits

Y

Linearity

Y

Conversion speed 40 clock periods

Y

Clock range 50 to 800 kHz

e

C

g

50 ms

DC

1 LSB

(00000000eafull-scale)

TRI-STATEÉis a registered trademark of National Semiconductor Corp.

C

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

TL/H/5670

TL/H/5670– 1

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (V

)V

DD

Supply Voltage (VGG)V

a

Voltage at Any Input V

SS

0.3V to V

b

22V

SS

b

22V

SS

b

22V

SS

Input Current at Any Pin (Note 2) 5 mA

Package Input Current (Note 2) 20 mA

Power Dissipation (Note 3) 875 mW

ESD Susceptibility (Note 4) 500V

Storage Temperature 150

Lead Temperature (Soldering, 10 sec.) 300§C

Operating Ratings (Note 1)

s

s

T

Temperature Range T

ADC0800PD

b

55§CsT

ADC0800PCD 0

MIN

CsT

§

T

A

MAX

s

a

125§C

A

s

a

70§C

A

Electrical Characteristics

These specifications apply for V
on-chip R-network (V
kHz. For all tests, a 475X resistor is used from pin 5 to V

R-NETWORK TOP

e

SS

5.0 VDC,V

e

5.000 VDCand V

specifications apply over an ambient temperature range of
ADC0800PCD.

Parameter Conditions Min Typ Max Units

Non-Linearity T

Differential Non-Linearity

Zero Error

Zero Error Temperature Coefficient (Note 9) 0.01 %/§C

Full-Scale Error

Full-Scale Error Temperature Coefficient (Note 9) 0.01 %/§C

Input Leakage 1 mA

Logical ‘‘1’’ Input Voltage All Inputs V

Logical ‘‘0’’ Input Voltage All Inputs V

Logical Input Leakage T

Logical ‘‘1’’ Output Voltage All Outputs, I

Logical ‘‘0’’ Output Voltage All Outputs, I

Disabled Output Leakage T

Clock Frequency 0§CsT

Clock Pulse Duty Cycle 40 60 %

TRI-STATE Enable/Disable Time 1 ms

Start Conversion Pulse (Note 10) 1 3(/2 Clock

Power Supply Current T

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.

Note 2: When the input voltage (V
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries witha5mAcurrent limit to four.

Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
device, T

Note 4: Human body model, 100 pF discharged through a 1.5 kX resistor.

Note 5: Typicals are at 25

Note 6: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 7: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.

Note 8: Non-linearity specifications are based on best straight line.

Note 9: Guaranteed by design only.

Note 10: Start conversion pulse duration greater than 3(/2 clock periods will cause conversion errors.

e

125§C, and the typical junction-to-ambient thermal resistance of the ADC0800PD and ADC0800PCD when board mounted is 66§C/W.

JMAX

) at any pin exceeds the power supply rails (V

IN

D

C and represent most likely parametric norm.

§

eb

12.0 VDC,V

GG

e

A

Over Temperature, (Note 8)

e

A

V

SS

e

A

V

SS

b

55§CsT

R-NETWORK BOTTOM

R-NETWORK BOTTOM

b

25§C, (Note 8)

25§C, All Inputs, V

b

10V

OH

e

OL

25§C, All Outputs, V

@

10V

s

a

70§C 50 800 kHz

A

s

a

A

e

0VDC, a reference voltage of 10.000 VDCacross the

DD

eb

5.000 VDC), and a clock frequency of 800

eb

5VDC. Unless otherwise noted, these

55§Ctoa125§C for the ADC0800PD and 0§Ctoa70§C for the

g

1 LSB

g

2 LSB

g

(/2 LSB

g

2 LSB

g

2 LSB

b

1.0 V

SS

GG

e

IL

e

100 mA 2.4 V

SS

b

V

4.2 V

SS

1 mA

1.6 mA 0.4 V

e

OL

2 mA

125§C 100 500 kHz

V

Periods

e

25§C20mA

A

k

IN

e

b

(T

TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this

JMAX

Vbor V

l

Va) the absolute value of current at that pin should be limited

IN

, iJA, and the ambient temperature, TA. The maximum

JMAX

C

§

2

Timing Diagram

Data is complementary binary (full scale is all ‘‘0’s’’ output).

Application Hints

OPERATION

The ADC0800 contains a network with 256-300X resistors
in series. Analog switch taps are made at the junction of
each resistor and at each end of the network. In operation,
a reference (10.00V) is applied across this network of 256
resistors. An analog input (V
ter point of the ladder via the appropriate switch. If V
larger than V
points and now compares V

/2, the internal logic changes the switch

REF

known as successive approximation, continues until the
best match of V
specific tap on the resistor network. When the conversion is

IN

and V

complete, the logic loads a binary word corresponding to
this tap into the output latch and an end of conversion
(EOC) logic level appears. The output latches hold this data
valid until a new conversion is completed and new data is
loaded into the latches. The data transfer occurs in about
200 ns so that valid data is present virtually all the time in
the latches. The data outputs are activated when the Output
Enable is high, and in TRI-STATE when Output Enable is
low. The Enable Delay time is approximately 200 ns. Each
conversion requires 40 clock periods. The device may be
operated in the free running mode by connecting the Start
Conversion line to the End of Conversion line. However, to
ensure start-up under all possible conditions, an external
Start Conversion pulse is required during power up condi­tions.

REFERENCE

The reference applied across the 256 resistor network de­termines the analog input range. V
of the R-network connected to 5V and the bottom connect-

b

ed to

5V gives ag5V range. The reference can be level
shifted between V
plied to the top of the R-network (pin 15), must not exceed
V

, to prevent forward biasing the on-chip parasitic silicon

SS

diodes that exist between the P-diffused resistors (pin 15)

SS

and the N-type body (pin 10, V
power supply for V
voltage tolerance and changes over temperature. A solution
is to power the V
of the op amp that is used to bias the top of the

SS

line (15 mA max drain) from the output

SS

) is first compared to the cen-

IN

and */4 V

IN

/N is made. N now defines a

REF

REF

. This process,

REF

e

10.00V with the top

IN

and VGG. However, the voltage, ap-

). Use of a standard logic

can cause problems, both due to initial

SS

R-network (pin 15). The analog input voltage and the volt­age that is applied to the bottom of the R-network (pin 5)
must be at least 7V above the

b

VGGsupply voltage to

ensure adequate voltage drive to the analog switches.

Other reference voltages may be used (such as 10.24V). If a
5V reference is used, the analog range will be 5V and accu­racy will be reduced by a factor of 2. Thus, for maximum

is

accuracy, it is desirable to operate with at least a 10V refer­ence. For TTL logic levels, this requires 5V and
R-network. CMOS can operate at the 10 V
a single 10 V
levels for both inputs and outputs will be from ground to
V

.

SS

reference can be used. All digital voltage

DC

ANALOG INPUT AND SOURCE RESISTANCE
CONSIDERATIONS

The lead to the analog input (pin 12) should be kept as short
as possible. Both noise and digital clock coupling to this
input can cause conversion errors. To minimize any input
errors, the following source resistance considerations
should be noted:

s

For R

5k No analog input bypass capacitor re-

S

quired, although a 0.1 mF input bypass
capacitor will prevent pickup due to un­avoidable series lead inductance.

s

k

For 5k

R

20k A 0.1 mF capacitor from the input (pin

S

l

For R

20k Input buffering is necessary.

S

12) to ground should be used.

If the overall converter system requires lowpass filtering of
the analog input signal, use a 20 kX or less series resistor
for a passive RC section or add an op amp RC active low­pass filter (with its inherent low output resistance) to ensure
accurate conversions.

CLOCK COUPLING

The clock lead should be kept away from the analog input
line to reduce coupling.

LOGIC INPUTS

The logical ‘‘1’’ input voltage swing for the Clock, Start Con­version and Output Enable should be (V

DCVSS

b

SS

b

1.0V).

TL/H/5670– 2

5V for the

level and

3