National Semiconductor 74F158A Technical data
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74F158A
Quad 2-Input Multiplexer
General Description
The F158A is a high speed quad 2-input multiplexer. It
selects four bits of data from two sources using the common Select and Enable inputs. The four outputs present
the selected data in the inverted form. The F158A can also
generate any four of the 16 differe nt functions o f two variables.
Ordering Code:
Order Number Package Number Package Description
74F158ASC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F158ASJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F158APC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
74F158A Quad 2-Input Multiplexer
April 1988
Revised July 1999
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation DS009484 www.fairchildsemi.com
Unit Loading/Fan Out
74F158A
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= E × (I1nS + I0n S)
Z
n
Pin Names Description
I0a–I
I
1a–I1d
E
0d
Source 0 Data Inputs 1.0/1.0 20 µA/−0.6 mA
Source 1 Data Inputs 1.0/1.0 20 µA/−0.6 mA
Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA
U.L.
HIGH/LOW
S Select Input 1.0/1.0 20 µA/−0.6 mA
Z
a–Zd
Inverted Outputs 50/33.3 −1 mA/20 mA
Functional Description
Inputs Outputs
E
SI0I
1
Z
HX X X H
LL L X H
LLH X L
LH X L H
LH X H L
The F158A quad 2-input multiplexer selects four bits of
data from two sources under the control of a common
Select input (S) and prese nts the data in inverted for m at
the four outputs. The Enable input (E
is HIGH, all of the outputs (Z) a re forced HIGH regar d-
E
less of all other inputs. The F158A is the logic implementation of a 4-pole, 2-positi on switc h whe re the p osition of the
switch is determined by the logic levels supplied to the
Select input.
A common use of the F158A is the moving of data from two
groups of registers to four common output busses. The
particular register from which the data comes is determined
by the state of t he S elect i nput . A l ess ob vious us e is as a
function generat or. The F15 8A ca n generate four func tions
of two variables wit h one variable co mmon. This i s useful
for implementing gating functions.
Input I
Output I
IH/IIL
OH/IOL
) is active LOW. When
Logic Diagram
Please note that this diagram is provided o nly f or t he understanding of lo gic operations and shou ld not be used to estimate propagation delays.
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