National Semiconductor 54FCT533 Technical data
查询54FCT533供应商
54FCT533
Octal Transparent Latch with TRI-STATE
®
Outputs
54FCT533 Octal Transparent Latch with TRI-STATE Outputs
September 1998
General Description
The FCT533 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is low,thedata satisfying the input timing requirements is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.
Logic Symbols
DS100969-1
Pin
Names
D
0–D7
LE Latch Enable Input
OE
O
0–O7
Data Inputs
Output Enable Input
TRI-STATE Latch
Outputs
Features
n Eight latches in a single package
n TTL input and output level compatible
n CMOS power consumption
n TRI-STATE outputs drive bus lines or buffer memory
address registers
n Output sink capability of 32mA, source capability of 12
mA
n Inverted version of the FCT373
n Standard Microcircuit Drawing (SMD) 5962-8865101
IEEE/IEC
DS100969-2
Description
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
™
FACT
is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100969 www.national.com
Connection Diagrams
Pin Assignment
for DIP and Flatpak
DS100969-3
Functional Description
The FCT533 contains eight D-type latches with TRI-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the D
dition the latches are transparent, i.e., a latch output will
inputs enters the latches. In this con-
n
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE standard outputs are controlled
by the Output Enable (OE) input. When OE is LOW,the standard outputs are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but this
does not interfere with entering new data into the latches.
Logic Diagram
Pin Assignment
for LCC
DS100969-4
Truth Table
Inputs Outputs
LE OE
XHX Z
HLL H
HLH L
LLX O
=
H
HIGH Voltage Level
L=LOW Voltage Level
Z=High Impedance
X=Immaterial
O
0
=
Previous O
before HIGH to Low transition of Latch Enable
0
D
n
O
n
0
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com 2
DS100969-5
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
DC Input Diode Current (I
=
−0.5V −20 mA
V
I
=
V
V
I
CC
DC Input Voltage (V
DC Output Diode Current (I
=
−0.5V −20 mA
V
O
=
V
V
O
CC
DC Output Voltage (V
DC Output Source
or Sink Current (I
or Ground Current
DC V
CC
per Output Pin (I
Storage Temperature (T
) −0.5V to +7.0V
CC
)
IK
+ 0.5V +20 mA
) −0.5V to VCC+ 0.5V
I
)
OK
+ 0.5V +20 mA
) −0.5V to VCC+ 0.5V
O
)
O
or I
CC
)
GND
) −65˚C to +150˚C
STG
±
50 mA
±
50 mA
DC Latchup Source
or Sink Current
Junction Temperature (T
CDIP 175˚C
Recommended Operating
Conditions
Supply Voltage (VCC)
’FCT 4.5V to 5.5V
Input Voltage (V
Output Voltage (VO) 0VtoV
Operating Temperature (TA)
54FCT −55˚C to +125˚C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT
) 0VtoV
I
®
DC Characteristics for ’FCT Family Devices
Symbol Parameter FCT541 Units V
Min Typ Max
V
Input HIGH Voltage 2.0 V Recognized HIGH Signal
IH
V
Input LOW Voltage 0.8 V Recognized LOW Signal
IL
V
Input Clamp Diode Voltage −1.2 V Min I
CD
V
Output HIGH Voltage 54FCT 4.3 V Min I
OH
V
Output LOW Voltage 54FCT 0.2 V Min I
OL
I
Input HIGH Current 5 µA Max V
IH
I
Input LOW Current −5 µA Max V
IL
I
Output Leakage Current 10 µA Max V
OZH
I
Output Leakage Current −10 µA Max V
OZL
I
Output Short-Circuit Current -60 mA Max V
OS
I
Quiescent Power
CCQ
Supply Current
Quiescent Power
∆I
CC
Supply Current
Dynamic I
I
CCD
I
Total Power Supply
CC
Current
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
CC
54FCT 2.4 V Min I
54FCT 0.5 V Min I
1.5 mA Max V
2.0 mA Max V
0.4 mA/
MHz
6.0 mA Max VCC= 5.5V, Outputs Open, fI
±
n
n
300 mA
=
2.0V
=
2.0V
)
J
circuits outside databook specifications.
CC
Conditions
=
−18 mA
IN
=
−300 µA
OH
=
−12 mA
OH
=
300 µA
OL
=
32 mA
OL
=
V
IN
CC
=
0.0V
IN
=
5.5V; OE
OUT
=
0.0V; OE
OUT
=
0.0V
OUT
<
0.2V or VIN5.3V, VCC=
IN
5.5V
=
− 2.1V
V
I
CC
Max VCC= 5.5V, Outputs Open,
One Bit Toggling, 50%Duty
=
Cycle, OE
= 10MHz, OE
Bit Toggling, 50%Duty Cycle
n
GND
n
=
GND, One
CC
CC
www.national.com3
Loading...