November 1994
54F/74F191
Up/Down Binary Counter with Preset and Ripple Clock
54F/74F191 Up/Down Binary Counter with Preset and Ripple Clock
General Description
The ’F191 is a reversible modulo-16 binary counter featuring synchronous counting and asynchronous presetting.
The preset feature allows the ’F191 to be used in programmable dividers. The Count Enable input, the Terminal Count
output and Ripple Clock output make possible a variety of
Features
Y
High-SpeedÐ125 MHz typical count frequency
Y
Synchronous counting
Y
Asynchronous parallel load
Y
Cascadable
methods of implementing multistage counters. In the counting modes, state changes are initiated by the rising edge of
the clock.
Commercial Military
Package
Number
Package Description
74F191PC N16E 16-Lead (0.300×Wide) Molded Dual-In-Line
54F191DM (Note 2) J16A 16-Lead Ceramic Dual-In-Line
74F191SC (Note 1) M16A 16-Lead (0.150×Wide) Molded Small Outline, JEDEC
74F191SJ (Note 1) M16D 16-Lead (0.300×Wide) Molded Small Outline, EIAJ
54F191FM (Note 2) W16A 16-Lead Cerpack
54F191LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13×reel. Use suffixeSCX and SJX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix
Logic Symbols
Pin Assignment for
DIP, SOIC and Flatpak
e
DMQB, FMQB and LMQB.
Connection Diagrams
Pin Assignment
for LCC
TL/F/9495– 1
IEEE/IEC
TL/F/9495– 2
TL/F/9495– 4
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
TL/F/9495
TL/F/9495– 3
Unit Loading/Fan Out
54F/74F
Pin Names Description
U.L. Input I
HIGH/LOW Output IOH/I
IH/IIL
CE Count Enable Input (Active LOW) 1.0/3.0 20 mA/b1.8 mA
b
CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 mA/
P
PL
0–P3
Parallel Data Inputs 1.0/1.0 20 mA/b0.6 mA
Asynchronous Parallel Load Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA
0.6 mA
U/D Up/Down Count Control Input 1.0/1.0 20 mA/b0.6 mA
Q0–Q3Flip-Flop Outputs 50/33.3b1 mA/20 mA
RC
TC Terminal Count Output (Active HIGH) 50/33.3
Ripple Clock Output (Active LOW) 50/33.3b1 mA/20 mA
b
1 mA/20 mA
Functional Description
The ’F191 is a synchronous up/down 4-bit binary counter. It
contains four edge-triggered flip-flops, with internal gating
and steering logic to provide individual preset, count-up and
count-down operations.
Each circuit has an asynchronous parallel load capability
permitting the counter to be preset to any desired number.
When the Parallel Load (PL
ent on the Parallel Data inputs (P
counter and appears on the Q outputs. This operation over-
) input is LOW, information pres-
) is loaded into the
0–P3
rides the counting functions, as indicated in the Mode Select Table.
A HIGH signal on the CE
input inhibits counting. When CE is
LOW, internal state changes are initiated synchronously by
the LOW-to-HIGH transition of the clock input. The direction
of counting is determined by the U
cated in the Mode Select Table. CE
/D input signal, as indi-
and U/D can be
changed with the clock in either state, provided only that the
recommended setup and hold times are observed.
Two types of outputs are provided as overflow/underflow
indicators. The Terminal Count (TC) output is normally LOW
and goes HIGH when a circuit reaches zero in the countdown mode or reaches 15 in the count-up mode. The TC
output will then remain HIGH until a state change occurs,
whether by counting or presetting or until U
/D is changed.
The TC output should not be used as a clock signal because it is subject to decoding spikes.
The TC signal is also used internally to enable the Ripple
Clock (RC
CE
) output. The RC output is normally HIGH. When
is LOW and TC is HIGH, the RC output will go LOW
when the clock next goes LOW and will stay LOW until the
clock goes HIGH again. This feature simplifies the design of
multistage counters, as indicated in
ure 1
, each RC output is used as the clock input for the next
Figures 1
and2.In
Fig-
higher stage. This configuration is particularly advantageous
when the clock source has a limited drive capability, since it
drives only the first stage. To prevent counting in all stages
it is only necessary to inhibit the first stage, since a HIGH
signal on CE
RC
inhibits the RC output pulse, as indicated in the
Truth Table. A disadvantage of this configuration, in
some applications, is the timing skew between state changes in the first and last stages. This represents the cumulative delay of the clock as it ripples through the preceding
stages.
A method of causing state changes to occur simultaneously
in all stages is shown in
in parallel and the RC
signals in ripple fashion. In this configuration the LOW state
duration of the clock must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through
to the last stage before the clock goes HIGH. There is no
such restriction on the HIGH state duration of the clock,
since the RC
output of any device goes HIGH shortly after
its CP input goes HIGH.
The configuration shown in
and their associated restrictions. The CE
stage is formed by combining the TC signals from all the
preceding stages. Note that in order to inhibit counting an
enable signal must be included in each carry gate. The simple inhibit scheme of
cause the TC output of a given stage is not affected by its
own CE
.
Mode Select Table
Inputs
PL CE U/D CP
HL LLCount Up
HL HLCount Down
L X X X Preset (Asyn.)
H H X X No Change (Hold)
Inputs Output
CE TC* CP RC
LHßß
HX X H
XL X H
*TC is generated internally
e
HIGH Voltage Level
H
e
LOW Voltage Level
L
e
Immaterial
X
e
LOW-to-HIGH Clock Transition
L
e
LOW Pulse
ß
OL
Figure 2
. All clock inputs are driven
outputs propagate the carry/borrow
Figure 3
avoids ripple delays
input for a given
Figures 1
and2doesn’t apply, be-
Mode
RC Truth Table
2
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
TL/F/9495– 6
FIGURE 1. n-Stage Counter Using Ripple Clock
TL/F/9495– 7
FIGURE 2. Synchronous n-Stage Counter Using Ripple Carry/Borrow
TL/F/9495– 5
FIGURE 3. Synchronous n-Stage Counter with Gated Carry/Borrow
3
TL/F/9495– 8
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
Pin Potential to
V
CC
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
Standard Output
CC
e
TRI-STATEÉOutput
0V)
b
65§Ctoa150§C
b
55§Ctoa125§C
b
55§Ctoa175§C
b
55§Ctoa150§C
b
0.5V toa7.0V
b
0.5V toa7.0V
b
30 mA toa5.0 mA
b
0.5V to V
b
0.5V toa5.5V
Current Applied to Output
in LOW State (Max) twice the rated I
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
(mA)
OL
DC Electrical Characteristics
Symbol Parameter
V
V
V
V
V
I
I
I
V
I
I
I
I
IH
IL
CD
OH
OL
IH
BVI
CEX
ID
OD
IL
OS
CC
Input HIGH Voltage 2.0 V Recognized as a HIGH Signal
Input LOW Voltage 0.8 V Recognized as a LOW Signal
Input Clamp Diode Voltage
Output HIGH 54F 10% V
Voltage 74F 10% V
Output LOW 54F 10% V
Voltage 74F 10% V
Input HIGH 54F 20.0
Current 74F 5.0
Input HIGH Current 54F 100
Breakdown Test 74F 7.0
Output HIGH 54F 250
Leakage Current 74F 50
Input Leakage
Test All Other Pins Grounded
Output Leakage
Circuit Current All Other Pins Grounded
Input LOW Current
Output Short-Circuit Current
Power Supply Current 38 55 mA Max
74F 5% V
74F 4.75 V 0.0
74F 3.75 mA 0.0
Min Typ Max
2.5 I
CC
2.5 V Min I
CC
2.7 I
CC
CC
CC
b
60
CC
54F/74F
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial 0
Supply Voltage
Military
Commercial
Units V
b
1.2 V Min I
0.5
0.5 I
CC
V Min
mA Max
mA Max
mA Max
b
0.6
b
b
mA Max
1.8 V
150 mA Max V
eb
IN
eb
OH
eb
OH
eb
OH
e
I
20 mA
OL
e
20 mA
OL
e
V
2.7V
IN
e
V
7.0V
IN
e
V
OUT
e
I
1.9 mA,
ID
e
V
IOD
e
V
0.5V (except CE)
IN
e
0.5V (CE)
IN
e
OUT
Conditions
18 mA
1mA
1mA
1mA
V
150 mV
0V
b
55§Ctoa125§C
Ctoa70§C
§
a
4.5V toa5.5V
a
4.5V toa5.5V
CC
4
AC Electrical Characteristics
Symbol Parameter V
Min Typ Max Min Max Min Max
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
Maximum Count Frequency 100 125 75 90 MHz
Propagation Delay 3.0 5.5 7.5 3.0 9.5 3.0 8.5
CP to Q
n
5.0 8.5 11.0 5.0 13.5 5.0 12.0
Propagation Delay 6.0 10.0 13.0 6.0 16.5 6.0 14.0
CP to TC 5.0 8.5 11.0 5.0 13.5 5.0 12.0
Propagation Delay 3.0 5.5 7.5 3.0 9.5 3.0 8.5
CP to RC 3.0 5.0 7.0 3.0 9.0 3.0 8.0
Propagation Delay 3.0 5.0 7.0 3.0 9.0 3.0 8.0
CE to RC 3.0 5.5 7.0 3.0 9.0 3.0 8.0
Propagation Delay 7.0 11.0 18.0 7.0 22.0 7.0 20.0
U/D to RC 5.5 9.0 12.0 5.5 14.0 5.5 13.0
Propagation Delay 4.0 7.0 10.0 4.0 13.5 4.0 11.0
U/D to TC 4.0 6.5 10.0 4.0 12.5 4.0 11.0
Propagation Delay 3.0 4.5 7.0 3.0 9.0 3.0 8.0
Pnto Q
n
6.0 10.0 13.0 6.0 16.0 6.0 14.0
Propagation Delay 5.0 8.5 11.0 5.0 13.0 5.0 12.0
PL to Q
n
5.5 9.0 12.0 5.5 14.5 5.5 13.0
Propagation Delay 5.0 14.0 5.0 15.0
Pnto TC 6.5 13.0 6.0 14.0
Propagation Delay 6.5 19.0 6.5 20.0
Pnto RC 6.0 14.0 6.0 15.0
Propagation Delay 8.0 16.5 8.0 17.5
PL to TC 6.0 13.5 6.0 14.5
Propagation Delay 10.0 20.0 10.0 21.0
PL to RC 9.0 15.5 9.0 16.0
74F 54F 74F
ea
T
25§C
CC
C
A
L
ea
e
50 pF
5.0V
T
A,VCC
e
C
50 pF C
L
e
Mil TA,V
e
Com
CC
e
50 pF
L
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
AC Operating Requirements
74F 54F 74F
Symbol Parameter
A
ea
CC
5.0V
V
T
A,VCC
e
Mil TA,V
e
Com Units
CC
ea
25§C
T
Min Max Min Max Min Max
ts(H) Setup Time, HIGH or LOW 4.5 6.0 5.0
t
(L) Pnto PL 4.5 6.0 5.0
s
ns
th(H) Hold Time, HIGH or LOW 2.0 2.0 2.0
t
(L) Pnto PL 2.0 2.0 2.0
h
ts(L) Setup Time LOW
CE
to CP
th(L) Hold Time LOW
CE
to CP
10.0 10.5 10.0
ns
000
ts(H) Setup Time, HIGH or LOW 12.0 12.0 12.0
t
(L) U/D to CP 12.0 12.0 12.0
s
ns
th(H) Hold Time, HIGH or LOW 0 0 0
t
(L) U/D to CP 0 0 0
h
tw(L) PL Pulse Width LOW 6.0 8.5 6.0 ns
tw(L) CP Pulse Width LOW 5.0 7.0 5.0 ns
t
rec
Recovery Time
PL
to CP
6.0 7.5 6.0 ns
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74F 191 S C X
Temperature Range Family Special Variations
e
74F
Commercial XeDevices shipped in 13×reels
e
54F
Military QBeMilitary grade with environmental
Device Type
Package Code
e
Plastic DIP
P
e
Ceramic DIP
D
e
Flatpak
F
e
L
Leadless Ceramic Chip Carrier (LCC)
e
S
Small Outline SOIC JEDEC
e
SJ
Small Outline SOIC EIAJ
and burn-in processing shipped
in tubes
Temperature Range
e
Commercial (0§Ctoa70§C)
C
e
Military (b55§Ctoa125§C)
M
6
Physical Dimensions inches (millimeters)
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
7
Physical Dimensions inches (millimeters) (Continued)
16-Lead (0.150×Wide) Molded Small Outline Package, JEDEC (S)
16-Lead (0.300×Wide) Molded Small Outline Package, EIAJ (SJ)
NS Package Number M16A
NS Package Number M16D
8
Physical Dimensions inches (millimeters) (Continued)
16-Lead (0.300×Wide) Molded Dual-In-Line Package (P)
NS Package Number N16E
9
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flatpak (F)
NS Package Number W16A
54F/74F191 Up/Down Binary Counter with Preset and Ripple Clock
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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