National Semiconductor 54F191, 74F191 Technical data

November 1994

54F/74F191
Up/Down Binary Counter with Preset and Ripple Clock

54F/74F191 Up/Down Binary Counter with Preset and Ripple Clock

General Description

The ’F191 is a reversible modulo-16 binary counter featur­ing synchronous counting and asynchronous presetting.
The preset feature allows the ’F191 to be used in program­mable dividers. The Count Enable input, the Terminal Count
output and Ripple Clock output make possible a variety of

Features

Y

High-SpeedÐ125 MHz typical count frequency

Y

Synchronous counting

Y

Asynchronous parallel load

Y

Cascadable

methods of implementing multistage counters. In the count­ing modes, state changes are initiated by the rising edge of
the clock.

Commercial Military

Package

Number

Package Description

74F191PC N16E 16-Lead (0.300×Wide) Molded Dual-In-Line

54F191DM (Note 2) J16A 16-Lead Ceramic Dual-In-Line

74F191SC (Note 1) M16A 16-Lead (0.150×Wide) Molded Small Outline, JEDEC

74F191SJ (Note 1) M16D 16-Lead (0.300×Wide) Molded Small Outline, EIAJ

54F191FM (Note 2) W16A 16-Lead Cerpack

54F191LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C

Note 1: Devices also available in 13×reel. Use suffixeSCX and SJX.

Note 2: Military grade device with environmental and burn-in processing. Use suffix

Logic Symbols

Pin Assignment for

DIP, SOIC and Flatpak

e

DMQB, FMQB and LMQB.

Connection Diagrams

Pin Assignment

for LCC

TL/F/9495– 1

IEEE/IEC

TL/F/9495– 2

TL/F/9495– 4

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

TL/F/9495

TL/F/9495– 3

Unit Loading/Fan Out

54F/74F

Pin Names Description

U.L. Input I

HIGH/LOW Output IOH/I

IH/IIL

CE Count Enable Input (Active LOW) 1.0/3.0 20 mA/b1.8 mA

b

CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 mA/
P
PL

0–P3

Parallel Data Inputs 1.0/1.0 20 mA/b0.6 mA
Asynchronous Parallel Load Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA

0.6 mA

U/D Up/Down Count Control Input 1.0/1.0 20 mA/b0.6 mA
Q0–Q3Flip-Flop Outputs 50/33.3b1 mA/20 mA
RC
TC Terminal Count Output (Active HIGH) 50/33.3

Ripple Clock Output (Active LOW) 50/33.3b1 mA/20 mA

b

1 mA/20 mA

Functional Description

The ’F191 is a synchronous up/down 4-bit binary counter. It
contains four edge-triggered flip-flops, with internal gating
and steering logic to provide individual preset, count-up and
count-down operations.

Each circuit has an asynchronous parallel load capability
permitting the counter to be preset to any desired number.
When the Parallel Load (PL
ent on the Parallel Data inputs (P
counter and appears on the Q outputs. This operation over-

) input is LOW, information pres-

) is loaded into the

0–P3

rides the counting functions, as indicated in the Mode Se­lect Table.

A HIGH signal on the CE

input inhibits counting. When CE is
LOW, internal state changes are initiated synchronously by
the LOW-to-HIGH transition of the clock input. The direction
of counting is determined by the U
cated in the Mode Select Table. CE

/D input signal, as indi-

and U/D can be
changed with the clock in either state, provided only that the
recommended setup and hold times are observed.

Two types of outputs are provided as overflow/underflow
indicators. The Terminal Count (TC) output is normally LOW
and goes HIGH when a circuit reaches zero in the count­down mode or reaches 15 in the count-up mode. The TC
output will then remain HIGH until a state change occurs,
whether by counting or presetting or until U

/D is changed.
The TC output should not be used as a clock signal be­cause it is subject to decoding spikes.

The TC signal is also used internally to enable the Ripple
Clock (RC
CE

) output. The RC output is normally HIGH. When

is LOW and TC is HIGH, the RC output will go LOW
when the clock next goes LOW and will stay LOW until the
clock goes HIGH again. This feature simplifies the design of
multistage counters, as indicated in

ure 1

, each RC output is used as the clock input for the next

Figures 1

and2.In

Fig-

higher stage. This configuration is particularly advantageous
when the clock source has a limited drive capability, since it
drives only the first stage. To prevent counting in all stages
it is only necessary to inhibit the first stage, since a HIGH
signal on CE
RC

inhibits the RC output pulse, as indicated in the

Truth Table. A disadvantage of this configuration, in
some applications, is the timing skew between state chang­es in the first and last stages. This represents the cumula­tive delay of the clock as it ripples through the preceding
stages.

A method of causing state changes to occur simultaneously
in all stages is shown in
in parallel and the RC
signals in ripple fashion. In this configuration the LOW state
duration of the clock must be long enough to allow the neg­ative-going edge of the carry/borrow signal to ripple through
to the last stage before the clock goes HIGH. There is no
such restriction on the HIGH state duration of the clock,
since the RC

output of any device goes HIGH shortly after

its CP input goes HIGH.

The configuration shown in
and their associated restrictions. The CE
stage is formed by combining the TC signals from all the
preceding stages. Note that in order to inhibit counting an
enable signal must be included in each carry gate. The sim­ple inhibit scheme of
cause the TC output of a given stage is not affected by its
own CE

.

Mode Select Table

Inputs

PL CE U/D CP

HL LLCount Up
HL HLCount Down

L X X X Preset (Asyn.)

H H X X No Change (Hold)

Inputs Output

CE TC* CP RC

LHßß
HX X H
XL X H

*TC is generated internally

e

HIGH Voltage Level

H

e

LOW Voltage Level

L

e

Immaterial

X

e

LOW-to-HIGH Clock Transition

L

e

LOW Pulse

ß

OL

Figure 2

. All clock inputs are driven

outputs propagate the carry/borrow

Figure 3

avoids ripple delays

input for a given

Figures 1

and2doesn’t apply, be-

Mode

RC Truth Table

2

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

TL/F/9495– 6

FIGURE 1. n-Stage Counter Using Ripple Clock

TL/F/9495– 7

FIGURE 2. Synchronous n-Stage Counter Using Ripple Carry/Borrow

TL/F/9495– 5

FIGURE 3. Synchronous n-Stage Counter with Gated Carry/Borrow

3

TL/F/9495– 8