Datasheet 5476, DM5476, DM7476 Datasheet (National Semiconductor)

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5476/DM5476/DM7476
Dual Master-Slave J-K Flip-Flops with Clear,
Preset, and Complementary Outputs

General Description

This device contains two independent positive pulse trig­gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flop after a complete clock
pulse. While the clock is low the slave is isolated from the
master. On the positive transition of the clock, the data from
the J and K inputs is transferred to the master. While the
clock is high the J and K inputs are disabled. On the nega­tive transition of the clock, the data from the master is trans-

June 1989

ferred to the slave. The logic state of J and K inputs must
not be allowed to change while the clock is high. The data is
transfered to the outputs on the falling edge of the clock
pulse. A low logic level on the preset or clear inputs will set
or reset the outputs regardless of the logic levels of the
other inputs.

Features

Y

Alternate Military/Aerospace device (5476) is available.
Contact a National Semiconductor Sales Office/Distrib­utor for specifications.

5476/DM5476/DM7476 Dual Master-Slave J-K Flip-Flops

with Clear, Preset, and Complementary Outputs

Connection Diagram

Dual-In-Line Package

Order Number 5476DMQB, 5476FMQB,

DM5476J, DM5476W or DM7476N

See NS Package Number J16A, N16E or W16A

TL/F/6528– 1

Function Table

Inputs Outputs

PR CLR CLK J K Q Q

LH XXXHL
HL XXXLH
LL XXXH*H*
HHÉLLQ
HHÉHL H L
HHÉLH L H
HHÉH H Toggle

HeHigh Logic Level

e

L

Low Logic Level

e

X

Either Low or High Logic Level

e

É

Positive pulse data. The J and K inputs must be held constant while
the clock is high. Data is transfered to the outputs on the falling edge of the
clock pulse.

e

*

This configuration is nonstable; that is, it will not persist when the preset

and/or clear inputs return to their inactive (high) level.

e

Q

The output logic level before the indicated input conditions were es-

0

tablished.

e

Toggle

Each output changes to the complement of its previous level on

each complete active high level clock pulse.

0

Q

0

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

TL/F/6528

Absolute Maximum Ratings (Note)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage 7V

Input Voltage 5.5V

Operating Free Air Temperature Range

DM54 and 54
DM74 0

Storage Temperature Range

b

55§Ctoa125§C

Ctoa70§C

§

b

65§Ctoa150§C

Recommended Operating Conditions

Symbol Parameter

V

V

V

I

I

f

t

t

t

T

CC

IH

IL

OH

OL

CLK

W

SU

H

A

Supply Voltage 4.5 5 5.5 4.75 5 5.25 V

High Level Input Voltage 2 2 V

Low Level Input Voltage 0.8 0.8 V

High Level Output Current

Low Level Output Current 16 16 mA

Clock Frequency (Note 6) 0 15 0 15 MHz

Pulse Width Clock High 20 20
(Note 6)

Input Setup Time (Notes1&6) 0

Input Hold Time (Notes1&6) 0

Free Air Operating Temperature

Clock Low 47 47

Preset Low 25 25

Clear Low 25 25

Min Nom Max Min Nom Max

u
v

b

55 125 0 70

The ‘‘Absolute Maximum Ratings’’ are those values

Note:

beyond which the safety of the device cannot be guaran­teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.

DM5476 DM7476

b

0.4

0

u

0

v

b

0.4 mA

Units

ns

ns

ns

C

§

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)

Symbol Parameter Conditions Min

e

V

I

V

OH

V

OL

I

I

I

IH

Input Clamp Voltage V

High Level Output V
Voltage V

Low Level Output V
Voltage V

Input Current@Max V
Input Voltage

High Level Input V
Current V

CC

CC
IL

CC
IH

CC

CC
I

e

e

e

eb

Min, I

e

Min, I

Max, V

e

Min, I

Min, V

e

Max, V

e

Max J, K 40

2.4V

12 mA

I

e

Max

OH

OL
IL

e

Min

IH

e

Max

e

Max

e

5.5V

I

2.4 3.4 V

Clock 80

Clear 80

Preset 80

I

IL

Low Level Input V
Current V

e

Max J, K

CC

e

0.4V

I

(Note 5)

Clock

Clear

Preset

I

OS

I

CC

Note 1: The symbol (u,v) indicates the edge of the clock pulse is used for reference (u) for rising edge, (v) for falling edge.

Note 2: All typicals are at V

Note 3: Not more than one output should be shorted at a time.

Note 4: With all outputs open, I

Note 5: Clear is measured with preset high and preset is measured with clear high.

Note 6: T

Short Circuit V
Output Current (Note 3)

Supply Current V

e

5V, T

CC

A

is measured with the Q and Q outputs high in turn. At the time of measurement the clock input is grounded.

CC

e

A

25§C and V

e

5V.

CC

e

25§C.

e

Max DM54

CC

DM74

e

Max (Note 4) 18 34 mA

CC

b

20

b

18

2

Typ

(Note 2)

Max Units

b

1.5 V

0.2 0.4 V

1mA

b

1.6

b

3.2

b

3.2

b

3.2

b

55

b

55

mA

mA

mA

Switching Characteristics at V

CC

e

Symbol Parameter

f

MAX

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

Maximum Clock
Frequency

Propagation Delay Time Preset
High to Low Level Output to Q

Propagation Delay Time Preset
Low to High Level Output to Q

Propagation Delay Time Clear
High to Low Level Output to Q

Propagation Delay Time Clear
Low to High Level Output to Q

Propagation Delay Time Clock to
High to Low Level Output Q or Q

Propagation Delay Time Clock to
Low to High Level Output Q or Q

Physical Dimensions inches (millimeters)

5V and T

From (Input)

To (Output)

e

25§C (See Section 1 for Test Waveforms and Output Load)

A

e

R

400X

L

e

15 pF Units

C

L

Min Max

15 MHz

40 ns

25 ns

40 ns

25 ns

40 ns

25 ns

16-Lead Ceramic Dual-In-Line Package (J)

Order Number 5476DMQB or DM5476J

NS Package Number J16A

3

Physical Dimensions inches (millimeters) (Continued)

16-Lead Molded Dual-In-Line Package (N)

Order Number DM7476N

NS Package Number N16E

with Clear, Preset, and Complementary Outputs

5476/DM5476/DM7476 Dual Master-Slave J-K Flip-Flops

16-Lead Ceramic Flat Package (W)

Order Number 5476FMQB or DM7476W

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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

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