National Semiconductor 54173, DM54173, DM74173 Technical data

查询54173供应商
54173/DM54173/DM74173 TRI-STATE
General Description
Gated enable inputs are provided for controlling the entry of data into the flip-flops. When both data-enable inputs are low, data at the D inputs are loaded into their respective flip­flops on the next positive transition of the buffered clock input. Gate output control inputs are also provided. When both are low, the normal logic states of the four outputs are available for driving the loads or bus lines. The outputs are disabled independently from the level of the clock by a high logic level at either output control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed operation is given in the function table.
Quad D Registers
É
June 1989
To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output con­trol circuitry is designed so that the average output disable times are shorter than the average output enable times.
Features
Y
TRI-STATE outputs interface directly with system bus
Y
Gated output control lines for enabling or disabling the outputs
Y
Fully independent clock elminates restrictions for oper­ating in one of two modes:
Parallel load Do nothing (hold)
Y
For application as bus buffer registers
Y
Typical propagation delay 18 ns
Y
Typical frequency 30 MHz
Y
Typical power dissipation 250 mW
Y
Alternate Military/Aerospace device (54173) is avail­able. Contact a National Semiconductor Sales Office/ Distributor for specifications.
54173/DM54173/DM74173 TRI-STATE Quad D Registers
Connection Diagram
Dual-In-Line Package
Order Number 54173DMQB, 54173FMQB,
DM54173J, DM54173W or DM74173N
See NS Package Number J16A, N16E or W16A
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/6556
TL/F/6556– 1
Function Table
Inputs
Clear Clock
HX X X X L LL X X XQ L
u
L
u
L
u
L
u
When either M or N (or both) is (are) high the output is disabled to the high-impedance state; however, sequential operation of the flip-flops is not affected.
Hehigh level (steady state)
e
L
low level (steady state)
e
low-to-high level transition
u
e
X
don’t care (any input including transitions)
e
Q
the level of Q before the indicated steady state input conditions were
0
established
Data Enable
G1 G2
HXXQ XHXQ LLLL LLHH
Data
D
Output
Q
0
0
0
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage 7V
Input Voltage 5.5V
Operating Free Air Temperature Range
DM54 and 54 DM74 0
Storage Temperature Range
b
55§Ctoa125§C
Ctoa70§C
§
b
65§Ctoa150§C
Recommended Operating Conditions
Symbol Parameter
V
V
V
I
OH
I
OL
f
CLK
t
W
t
SU
t
H
t
REL
T
CC
IH
IL
A
Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
High Level Input Voltage 2 2 V
Low Level Input Voltage 0.8 0.8 V
High Level Output Current
Low Level Output Current 16 16 mA
Clock Frequency (Note 4) 0 25 0 25 MHz
Pulse Width Clock 20 20 (Note 4)
Clear 20 20
Setup Time Enable 17 17 (Note 4)
Data 10 10
Hold Time Enable 2 2 (Note 4)
Data 10 10
Clear Release Time (Note 4) 10 10 ns
Free Air Operating Temperature
Min Nom Max Min Nom Max
b
55 125 0 70
The ‘‘Absolute Maximum Ratings’’ are those values
Note:
beyond which the safety of the device cannot be guaran­teed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation.
DM54173 DM74173
b
2
b
5.2 mA
Units
ns
ns
ns
C
§
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Conditions Min
e
V
I
V
OH
V
OL
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
CC
Note 1: All typicals are at V
Note 2: Not more than one output should be shorted at a time.
Note 3: I
input and M input at 4.5V.
Note 4: T
Input Clamp Voltage V
High Level Output V Voltage V
Low Level Output V Voltage V
Input Current@Max V Input Voltage
High Level Input Current V
Low Level Input Current V
Off-State Output Current with High V Level Output Voltage Applied V
Off-State Output Current with Low V Level Output Voltage Applied V
Short Circuit V Output Current (Note 2)
Supply Current V
e
e
5V, T
5V.
25§C.
A
CC
is measured with all outputs open, CLEAR grounded after a momentary connection to 4.5V: N, G1, G2 and all DATA inputs grounded: and the CLOCK
CC
e
A
25§C and V
e
CC
CC
CC
IL
CC
IH
CC
CC
CC
CC
IH
CC
IH
CC
CC
e
e
e
e
eb
Min, I
e
Min, I
Max, V
e
Min, I
Min, V
e
Max, V
e
Max, V
e
Max, V
e
Max, V
Min, V
e
Max, V
Min, V
e
Max DM54
e
Max (Note 3) 50 72 mA
12 mA
I
e
Max
OH
e
Min
IH
e
Max
OL
e
Max
IL
e
5.5V
I
e
2.4V 40 mA
I
e
0.4V
I
e
2.4V
O
e
Max
IL
e
0.4V
O
e
Max
IL
DM74
2.4 V
b
b
2
Typ
(Note 1)
Max Units
b
1.5 V
0.4 V
1mA
b
1.6 mA
40 mA
b
40 mA
30
30
b
70
b
70
mA
Loading...
+ 4 hidden pages