Datasheet 100331 Datasheet (National Semiconductor)

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100331
Low Power Triple D Flip-Flop

100331 Low Power Triple D Flip-Flop

August 1998

General Description

The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Com­mon Clock (CP
(MR) inputs. Each flip-flophas individual Clock (CP
Set (SD
ter when both CP
slave when CP
Master Reset and individual CD
the Clock inputs. All inputs have 50 kΩ pull-down resistors.

), and Master Set (MS) and Master Reset

C

) and Direct Clear (CDn) inputs. Data enters a mas-

n

and CPCare LOW and transfers to a

n

or CPC(or both) go HIGH. The Master Set,

n

and SDninputs override

n

), Direct

n

Logic Symbol

DS100300-1

Connection Diagrams

24-Pin DIP

Features

n 35%power reduction of the 100131
n 2000V ESD protection
n Pin/function compatible with 100131
n Voltage compensated operating range=−4.2V to −5.7V
n Available to industrial grade temperature range
n Available to Standard Microcircuit Drawing (SMD)

5962-9153601

Pin Names Description

CP

–CP

0

2

CP

C

D

0–D2

CD

–CD

0

2

SD

n

MR Master Reset Input
MS Master Set Input
Q

0-Q2

Q

0–Q2

Individual Clock Inputs
Common Clock Input
Data Inputs
Individual Direct Clear Inputs
Individual Direct Set Inputs

Data Outputs
Complementary Data Outputs

24-Pin Quad Cerpak

DS100300-3

DS100300-2

© 1998 National Semiconductor Corporation DS100300 www.national.com

Logic Diagram

Truth Tables
Synchronous Operation

(Each Flip-Flop)

Inputs Outputs

CPnCPCMS MR Qn(t+1)

D

n

N

L

N

H
LL
HL

LLL L
LLL H

N

N

XLLLL Qn(t)
X H X L L Qn(t)
X X H L L Qn(t)

H=HIGH Voltage Level
L=LOW Voltage Level
X=Don’t Care
U=Undefined
t=Time before CP Positive Transition
t+1=Time after CP Positive Transition

=

N

LOW to HIGH Transition

CD

SD

n

n

LL L
LL H

DS100300-5

Asynchronous Operation

(Each Flip-Flop)

Inputs Outputs

CPnCP

D

n

XX XH L H
XX X L H L
XX XHH U

MS MR Qn(t+1)

C

SD

CD

n

n

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Above which the useful life may be impaired
Storage Temperature (T
Maximum Junction Temperature (T

Ceramic +175˚C

Pin Potential to

Ground Pin (V

EE

) −65˚C to +150˚C

STG

)

J

) −7.0V to +0.5V

Input Voltage (DC) V

EE

to +0.5V

Output Current

(DC Output HIGH) −50 mA

ESD (Note 2) ≤ 2000V

Recommended Operating
Conditions

Case Temperature (TC)

Military −55˚C to +125˚C

Supply Voltage (V

Note 1: Absolute maximum ratings are those values beyond which the de­vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

) −5.7V to −4.2V

EE

Military Version

DC Electrical Characteristics

=

V

−4.2V to −5.7V, V

EE

Symbol Parameter Min Max Units T

V

OH

V

OL

V

OHC

V

OLC

V

IH

V

IL

I

IL

I

IH

I

EE

Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (toguaranteejunctiontemperatureequals−55˚C),thentestingimmediately
without allowing for the junction temperature to stabilize due toheatdissipationafterpower-up.Thisprovides“coldstart”specswhichcanbeconsideredaworstcase
condition at cold temperatures.

Note 4: Screen tested 100%on each device at −55˚C, +25˚C, and +125˚C, Subgroups, 1, 2, 3, 7 and 8.
Note 5: Sampled tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7 and 8.
Note 6: Guaranteed by applying specified input condition and testing V

Output HIGH Voltage −1025 −870 mV 0˚C to V

Output LOW Voltage −1830 −1620 mV 0˚C to

Output HIGH Voltage −1035 mV 0˚C to V

Output LOW Voltage −1610 mV 0˚C to

Input HIGH Voltage −1165 −870 mV −55˚C to Guaranteed HIGH Signal

Input LOW Voltage −1830 −1475 mV −55˚C to Guaranteed LOW Signal

Input LOW Current 0.50 µA −55˚C to V

Input HIGH Current 240 µA 0˚C to V

Power Supply Current −130 −50 mA −55˚C to Inputs Open

=

=

V

CCA

GND, T

CC

−1085 −870 mV −55˚C

=

−55˚C to +125˚C

C

C

+125˚C

Conditions Notes

=

or V

IN

(Max)

IL

V

(Min)

IH

Loading with

50Ω to −2.0V

(Notes 3,

+125˚C

−1830 −1555 mV −55˚C
=

+125˚C

−1085 mV −55˚C

or V

IN

(Min)

IL

V

(Max)

IH

Loading with

50Ω to −2.0V

(Notes 3,

+125˚C

−1555 mV −55˚C
(Notes 3,

+125˚C for all Inputs

4, 5, 6)

(Notes 3,

+125˚C for all Inputs

=

−4.2V

EE

=

(Min)

+125˚C V

+125˚C

V

IN

IL

=

−5.7V

EE

=

V

V

IN

IH

(Max)

4, 5, 6)

(Notes 3,

(Notes 3,

340 µA −55˚C

(Notes 3,

+125˚C

.

OH/VOL

4, 5)

4, 5)

4, 5)

4, 5)

4, 5)

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AC Electrical Characteristics

=

V

−4.2V to −5.7V, V

EE

Symbol Parameter T

f

t
t
t
t
t
t
t
t
t
t
t
t
t
t
t

Toggle Frequency 400 400 400 MHz

max

Propagation Delay 0.50 2.20 0.60 2.00 0.50 2.40 ns

PLH

CPCto Output

PHL

Propagation Delay 0.50 2.20 0.60 2.00 0.50 2.40 ns

PLH

CPnto Output

PHL

Propagation Delay 0.50 2.20 0.60 2.00 0.50 2.40 CPn,CP

PLH

CDn,SDnto Output ns

PHL
PLH
PHL

Propagation Delay 0.70 2.70 0.80 2.60 0.80 2.90 CPn,CP

PLH

MS, MR to Output ns

PHL
PLH
PHL

Transition Time 0.20 1.40 0.20 1.40 0.20 1.40 ns

TLH

20%to 80%,80%to 20

THL

Setup Time

s

D

n

CD

,SDn(Release Time) 1.50 1.30 1.60 ns

n

MS, MR (Release Time) 2.50 2.30 2.50

t

h

Hold Time D

tpw(H) Pulse Width HIGH

CP

,CPC,CDn, 2.00 2.00 2.00 ns

n

SDn, MR, MS

Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (toguaranteejunctiontemperatureequals−55˚C),thentestingimmediately
without allowing for the junction temperature to stabilize due toheatdissipationafterpower-up.Thisprovides“coldstart”specswhichcanbeconsideredaworstcase
condition at cold temperatures.

Note 8: Screen tested 100%on each device at +25˚C. Temperature only, Subgroup A9.
Note 9: Sample tested (Method 5005, Table I) on each Mfg. lot at +25˚C, Subgroup A9, and at +125˚C, and −55˚C Temp., Subgroups A10 and A11.
Note 10: Not tested at +25˚C, +125˚C and −55˚C Temperature (design characterization data).

=

=

V

CCA

GND

=

−55˚C T

C

=

C

+25˚C T

=

+125˚C Units Conditions Notes

C

CC

Min Max Min Max Min Max

Figures 2, 3

Figures 1, 3

=

Figures

L

0.50 2.40 0.60 2.10 0.50 2.50 CPn,CP

0.70 2.90 0.80 2.80 0.80 3.10 CPn,CP

C

C

C

C

1, 4

=

H

=

L

=

H

Figures 1, 3, 4

%

Figure 5

1.00 0.80 0.90

Figure 4

n

1.50 1.30 1.60 ns

Figure 5

Figures 3, 4

(Note

10)

(Notes

7, 8,

9)

(Note

10)

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Test Circuits

DS100300-6

FIGURE 1. AC Test Circuit

Notes:

=

V

CC,VCCA

L1 and L2=Equal length 50Ω impedance lines

=

50Ω terminator internal to scope

R

T

Decoupling 0.1 µF from GND to V
All unused outputs are loaded with 50Ω to GND

=

Fixture and stray capacitance ≤ 3pF

C

L

+2V, V

=

−2.5V

EE

and V

CC

EE

DS100300-7

FIGURE 2. Toggle Frequency Test Circuit

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Switching Waveforms

FIGURE 3. Propagation Delay (Clock) and Transition Times

DS100300-8

FIGURE 4. Propagation Delay (Resets)

FIGURE 5. Data Setup and Hold Time

Note 11: tsis the minimum time before the transition of the clock that information must be present at the data input.
Note 12: t

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is the minimum time after the transition of the clock that information must remain unchanged at the data input.

h

DS100300-9

DS100300-10

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Ceramic Dual-In-Line Package (0.400" Wide) (D)

NS Package Number J24E

24-Lead Quad Cerpak (F)

NS Package Number W24B

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100331 Low Power Triple D Flip-Flop

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