National Instruments Corporation GPIB-1014P User Manual

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GPIB-1014P

User Manual

June 1994 Edition

Part Number 370944A-01

National Instruments Corporate Headquarters

6504 Bridge Point Parkway Austin, TX 78730-5039 (512) 794-0100 Technical support fax: (800) 328-2203

(512) 794-5678

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Limited Warranty

The GPIB-1014P is warranted against defects in materials and workmanship for a period of two years from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.

A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work. National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty.

National Instruments believes that the information in this manual is accurate. The document has been carefully reviewed for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition. The reader should consult National Instruments if errors are suspected. In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it.

EXCEPT AS SPECIFIED HEREIN, NATIONAL INSTRUMENTS MAKES NO WARRANTIES, EXPRESS OR IMPLIED,

AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OF

NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA, PROFITS,

USE OF PRODUCTS, OR INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY THEREOF

whether in contract or tort, including negligence. Any action against National Instruments must be brought within one year after the cause of action accrues. National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control. The warranty provided herein does not cover damages, defects, malfunctions, or service failures caused by owner’s failure to follow the National Instruments installation, operation, or maintenance instructions; owner’s modification of the product; owner’s abuse, misuse, or negligent acts; and power failure or surges, fire, flood, accident, actions of third parties, or other events outside reasonable control.

. CUSTOMER’S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART

NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER.

. This limitation of the liability of National Instruments will apply regardless of the form of action,

Copyright

Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical, including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part, without the prior written consent of National Instruments Corporation.

Trademarks

Product and company names listed are trademarks or trade names of their respective companies.

WARNING REGARDING MEDICAL AND CLINICAL USE

OF NATIONAL INSTRUMENTS PRODUCTS

National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the part of the user or application designer. Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel, and all traditional medical safeguards, equipment, and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used. National Instruments products are NOT intended to be a substitute for any form of established process, procedure, or equipment used to monitor or safeguard human health and safety in medical or clinical treatment.

FCC/DOC Radio Frequency Interference Compliance

This equipment generates and uses radio frequency energy and, if not installed and used in strict accordance with the instructions in this manual, may cause interference to radio and television reception. This equipment has been tested and found to comply with the following two regulatory agencies:

Federal Communications Commission

This device complies with Part 15 of the Federal Communications Commission (FCC) Rules for a Class A digital device. Operation is subject to the following two conditions:

1. This device may not cause harmful interference in commercial environments.

2. This device must accept any interference received, including interference that may cause undesired operation.

Canadian Department of Communications

This device complies with the limits for radio noise emissions from digital apparatus set out in the Radio Interference Regulations of the Canadian Department of Communications (DOC).

Le présent appareil numérique n’émet pas de bruits radioélectriques dépassant les limites applicables aux appareils numériques de classe A prescrites dans le règlement sur le brouillage radioélectrique édicté par le ministère des communications du Canada.

Instructions to Users

These regulations are designed to provide reasonable protection against harmful interference from the equipment to radio reception in commercial areas. Operation of this equipment in a residential area is likely to cause harmful interference, in which case the user will be required to correct the interference at his own expense.

There is no guarantee that interference will not occur in a particular installation. However, the chances of interference are much less if the equipment is installed and used according to this instruction manual.

If the equipment does cause interference to radio or television reception, which can be determined by turning the equipment on and off, one or more of the following suggestions may reduce or eliminate the problem.

• Operate the equipment and the receiver on different branches of your AC electrical system.

• Move the equipment away from the receiver with which it is interfering.

• Reorient or relocate the receiver’s antenna.

• Be sure that the equipment is plugged into a grounded outlet and that the grounding has not been defeated with a cheater plug.

Notice to user: Changes or modifications not expressly approved by National Instruments could void the user’s

authority to operate the equipment under the FCC Rules.

If necessary, consult National Instruments or an experienced radio/television technician for additional suggestions. The following booklet prepared by the FCC may also be helpful: How to Identify and Resolve Radio-TV Interference Problems. This booklet is available from the U.S. Government Printing Office, Washington, DC 20402, Stock Number 004-000-00345-4.

Preface

The GPIB-1014P is a single-height circuit board which interfaces the VMEbus to the IEEE-488 General Purpose Interface Bus (GPIB). The GPIB-1014P provides a means to implement VMEbus test and measurement systems with standard interconnecting cables.

Organization of the Manual

This manual describes the mechanical and electrical aspects of the GPIB-1014P and contains information concerning its operation and programming. The manual is divided into the following sections:

• Section One, General Information, describes the GPIB-1014P, lists the contents of your GPIB-1014P kit, and explains how to unpack the GPIB-1014P kit.

• Section Two, General Description, contains the physical and electrical specifications for the GPIB-1014P and describes the characteristics of key interface board components.

• Section Three, Configuration and Installation, describes the steps needed to configure the GPIB-1014P hardware and to verify that it is functioning properly.

• Section Four, Register Bit Descriptions, contains detailed descriptions of the GPIB Interface registers of the NEC µPD7210 LSI GPIB Talker/Listener/Controller as well as summary tables for easy reference.

• Section Five, Programming Considerations, explains important considerations for programming the GPIB-1014P.

• Section Six, Theory of Operation, contains a functional overview of the GPIB-1014P board and explains the operation of each functional block making up the GPIB-1014P.

• Section Seven, GPIB-1014P Diagnostic and Troubleshooting Test Procedures, contains test procedures for determining if the GPIB-1014P is installed and operating correctly.

• Appendix A, Specifications, lists the specifications of the GPIB-1014P.

• Appendix B, Parts List and Schematic Diagrams, contains a parts list and detailed schematic diagrams.

• Appendix C, Sample Programs, provides sample programs in 68000 Assembly Language code for implementing the most commonly used GPIB functions. Line-by-line comments provide an explanation of each function.

• Appendix D, Multiline Interface Command Messages, contains a listing of the multiline GPIB interface messages.

Preface

• Appendix E, Operation of the GPIB, describes the operation of the GPIB.

• Appendix F, Mnemonics Key, contains an alphabetical listing of all mnemonics used in this manual and indicates whether the mnemonic represents a bit, register, function, remote message, local message, state, VMEbus operation, or VMEbus signal.

• Appendix G, Customer Communication, contains forms you can use to request help from National Instruments or to comment on our products and manuals.

• The Index contains an alphabetical list of key terms and topics in this manual, including the page where you can find each one.

Abbreviations Used in This Manual

The following abbreviations are used in the text of this manual.

A ampere C Celsius ° degree hex hexadecimal in. inch kbytes 1000 bytes m meter Mbytes million bytes mm millimeter MHz megahertz µsec microsecond nsec nanosecond sec second V volt VDC volts direct current

GPIB-1014P User Manual vi © National Instruments Corporation

Preface

Customer Communication

National Instruments wants to receive your comments on our products and manuals. We are interested in the applications you develop with our products, and we want to help if you have problems with them. To make it easy for you to contact us, this manual contains comment and configuration forms for you to complete. These forms are in Appendix G, Customer

Communication, at the end of this manual.

Section One General Information

What Your Kit Should Contain .....................................................................................1-3

Optional Equipment ......................................................................................................1-3

Unpacking ..................................................................................................................... 1-3

Section Two General Description

Physical Characteristics ................................................................................................ 2-1

Electrical Characteristics ...............................................................................................2-1

VMEbus Characteristics ...............................................................................................2-2

VMEbus Slave-Addressing ............................................................................... 2-2

VMEbus Slave-Data .........................................................................................2-3

Interrupter ..........................................................................................................2-4

VMEbus Modules Not Provided ....................................................................... 2-5

Diagnostic Aids ................................................................................................. 2-5

Data Transfer Features ..................................................................................................2-5

GPIB-1014P Functional Description ............................................................................ 2-5

........................................................................................................1-1

.......................................................................................................... 2-1

Section Three Configuration and Installation

Configuration ................................................................................................................ 3-1

Access Mode ..................................................................................................... 3-3

VMEbus Base Address ..................................................................................... 3-3

VMEbus Interrupt Configuration ...................................................................... 3-5

Interrupt Request Line Selection ...........................................................3-5

Interrupt Priority Code .......................................................................... 3-5

Interrupt Status/ID Vector Selection ................................................................. 3-7

GPIB Cable Shield Grounding ..........................................................................3-8

Installation .....................................................................................................................3-9

Verification of System Compatibility ............................................................... 3-9

Verification Testing .......................................................................................... 3-10

Cabling ..............................................................................................................3-10

Section Four Register Bit Descriptions

Register Map ................................................................................................................. 4-1

Terminology ..........................................................................................4-2

Interface Registers .........................................................................................................4-3

Data In Register (DIR) ......................................................................................4-6

Command/Data Out Register (CDOR) ............................................................. 4-7

Interrupt Status Register 1 (ISR1) .....................................................................4-8

Interrupt Mask Register 1 (IMR1) .................................................................... 4-8

................................................................................................ 4-1

....................................................................................3-1

Contents

Interrupt Status Register 2 (ISR2) .....................................................................4-14

Interrupt Mask Register 2 (IMR2) .................................................................... 4-14

Serial Poll Status Register (SPSR) .................................................................... 4-19

Serial Poll Mode Register (SPMR) ................................................................... 4-19

Address Status Register (ADSR) ...................................................................... 4-20

Address Mode Register (ADMR) ..................................................................... 4-22

Command Pass Through Register (CPTR) ....................................................... 4-25

Auxiliary Mode Register (AUXMR) ................................................................ 4-27

Hidden Registers ............................................................................................... 4-34

Internal Counter Register (ICR) ............................................................4-35

Parallel Poll Register (PPR) .................................................................. 4-36

Auxiliary Register A (AUXRA) ........................................................... 4-38

Auxiliary Register B (AUXRB) ............................................................4-40

Auxiliary Register E (AUXRE) ............................................................ 4-42

Address Register 0 (ADR0) .............................................................................. 4-43

Address Register (ADR) ................................................................................... 4-44

Address Register 1 (ADR1) .............................................................................. 4-45

End Of String Register (EOSR) ........................................................................ 4-46

Section Five Programming Considerations

Initialization .................................................................................................................. 5-1

The GPIB-1014P as GPIB Controller ...........................................................................5-2

Becoming Controller-In-Charge (CIC) and Active Controller ......................... 5-2

Sending Remote Multiline Messages (Commands) .......................................... 5-3

Going from Active to Standby Controller .........................................................5-3

Going from Standby to Active Controller .........................................................5-4

Going from Active to Idle Controller ...............................................................5-4

The GPIB-1014P as GPIB Talker and Listener ............................................................ 5-5

Programmed Implementation of Talker and Listener ....................................... 5-5

Addressed Implementation of the Talker and Listener .....................................5-5

Address Mode 1 .................................................................................... 5-5

Address Mode 2 .................................................................................... 5-5

Address Mode 3 .................................................................................... 5-6

Sending/Receiving Messages ........................................................................................5-7

Sending/Receiving END or EOS ...................................................................... 5-7

Interrupts ....................................................................................................................... 5-7

Serial Polls .................................................................................................................... 5-8

Conducting Serial Polls .....................................................................................5-8

Responding to a Serial Poll ............................................................................... 5-8

Parallel Polls .................................................................................................................5-9

Conducting a Parallel Poll .................................................................................5-9

Responding To a Parallel Poll ...........................................................................5-10

....................................................................................... 5-1

Section Six Theory of Operation

VMEbus Interface ......................................................................................................... 6-1

Data Lines ......................................................................................................... 6-1

Control Signals ..................................................................................................6-1

Address Lines ....................................................................................................6-2

GPIB-1014P User Manual xii © National Instruments Corporation

........................................................................................................6-1

Address Decoding ......................................................................................................... 6-2

Clock and Reset Circuitry ............................................................................................. 6-2

Timing Control Logic ................................................................................................... 6-3

Interrupter Logic ........................................................................................................... 6-3

GPIB Interface .............................................................................................................. 6-4

Test and Troubleshooting ..............................................................................................6-5

Section Seven GPIB-1014P Diagnostic and Troubleshooting Test Procedures

Interpreting Test Procedures ......................................................................................... 7-1

GPIB-1014P Hardware Installation Tests ..................................................................... 7-2

Appendix A Specifications

.......................................................................................................................A-1

Appendix B Parts List and Schematic Diagrams

...........................................................................B-1

Contents

.....................7-1

Appendix C Sample Programs

...............................................................................................................C-1

Appendix D Multiline Interface Command Messages

Appendix E Operation of the GPIB

Types of Messages ........................................................................................................ E-1

Talkers, Listeners, and Controllers ............................................................................... E-1

The Controller-In-Charge and System Controller ........................................................E-2

GPIB Signals and Lines ................................................................................................ E-2

Data Lines ......................................................................................................... E-2

Handshake Lines ............................................................................................... E-2

Interface Management Lines .............................................................................E-3

Physical and Electrical Characteristics ......................................................................... E-3

Configuration Requirements ......................................................................................... E-6

Related Document ......................................................................................................... E-7

....................................................................................................E-1

NRFD (not ready for data) .................................................................... E-2

NDAC (not data accepted) ....................................................................E-2

DAV (data valid) ...................................................................................E-3

ATN (attention) ..................................................................................... E-3

IFC (interface clear) .............................................................................. E-3

REN (remote enable) ............................................................................E-3

SRQ (service request) ........................................................................... E-3

EOI (end or identify) ............................................................................. E-3

..................................................................D-1

Appendix F Mnemonics Key

..................................................................................................................F-1

Contents

Appendix G Customer Communication

...............................................................................................G-1

Index..................................................................................................................................Index-1

Figures

Figure 1-1. GPIB-1014P Interface Board ............................................................................... 1-2

Figure 2-1. GPIB-1014P with a VMEbus Computer ..............................................................2-6

Figure 2-2. GPIB-1014P in a Multiprocessor Application ..................................................... 2-7

Figure 2-3. GPIB-1014P Block Diagram ...............................................................................2-8

Figure 3-1. GPIB-1014P Parts Locator Diagram ....................................................................3-2

Figure 3-2. Access Selection ..................................................................................................3-3

Figure 3-3. Configuration for VMEbus Base Address 1000 hex (default setting) ................. 3-4

Figure 3-4. VMEbus Interrupt Line Selection ........................................................................ 3-5

Figure 3-5. VMEbus Interrupt Priority Code Selection ..........................................................3-6

Figure 3-6. Status/ID Byte 1A hex ......................................................................................... 3-7

Figure 3-7. GPIB Cable Shield Grounding .............................................................................3-8

Figure 3-8. GPIB Cable Connector .........................................................................................3-11

Figure 4-1. µPD7210 Interface Registers ...............................................................................4-4

Figure 4-2. Writing to the Hidden Registers ...........................................................................4-5

Figure E-1. GPIB Connector and the Signal Assignment .......................................................E-4

Figure E-2. Linear Configuration ............................................................................................ E-5

Figure E-3. Star Configuration ................................................................................................ E-6

Tables

Table 2-1. GPIB-1014P Signals ............................................................................................ 2-1

Table 2-2. µPD7210 Internal GPIB Interface Registers ........................................................2-3

Table 2-3. GPIB-1014P IEEE-488 Interface Capabilities .....................................................2-10

Table 2-4. GPIB-1014P IEEE-1014 Interrupter Compliance Levels .................................... 2-12

Table 3-1. GPIB-1014P Pin Assignment on VMEbus Connector P1 ................................... 3-9

Table 4-1. GPIB-1014P Register Map .................................................................................. 4-1

Table 4-2. Clues to Understanding Mnemonics .................................................................... 4-3

Table 4-3. Multiline GPIB Commands Recognized by the µPD7210 ...................................4-25

Table 4-4. Auxiliary Command Summary ............................................................................ 4-28

Table 4-5. Auxiliary Commands Detail Description .............................................................4-30

GPIB-1014P User Manual xiv © National Instruments Corporation

Section One General Information

The GPIB-1014P is an IEEE-488 interface for the VMEbus. This interface permits IEEE-488 compatible engineering, scientific, or medical instruments to be controlled from a VMEbus-based computer. The GPIB-1014P has the following features:

• Complete IEEE-488 Talker/Listener/Controller (TLC) capability using the NEC µPD7210

GPIB TLC chip

• Polled or interrupt driven transfers

• Transfer rates up to 80 kbytes/sec

• User configurable parameters

- Base Address

- Interrupt Request Line

- Interrupt Status/ID byte

- Supervisor or User Access

• IEEE-1014 (VMEbus) standard compliance

• Comprehensive software support The GPIB-1014P conforms to all requirements and conventions specified in the ANSI/IEEE Std.

1014-1987. Hereafter, the General Purpose Interface Bus is referred to as the GPIB, the GPIB standard is referred to as the IEEE-488 standard, and the ANSI/IEEE Std. 1014-1987 is referred to as the IEEE-1014 standard.

Section One General Information

What Your Kit Should Contain

Your GPIB-1014P kit contains one of the following boards:

• GPIB-1014P-1

• GPIB-1014P-2

• GPIB-1014P-1S

Optional Equipment

You can contact National Instruments to order the following optional equipment:

• Single-shielded Type X1 GPIB cables* (1 m, 2 m, 4 m, or 8 m)

• Double-shielded Type X2 GPIB cables* (1 m, 2 m, or 4 m) * To meet FCC emission limits for this Class A device, you must use a shielded

(Type X1 or X2) GPIB cable. Operating this equipment with a non-shielded cable may cause interference to radio and television reception in commercial areas.

• GPIB Monitor/Analyzer – GPIB-400 – GPIB-410

Unpacking

Follow these steps when unpacking your GPIB-1014P:

1. Your GPIB-1014P board is shipped packaged in an antistatic plastic bag to prevent electrostatic damage to the board. Several components on the board can be damaged by electrostatic discharge. To avoid such damage in handling the board, touch the plastic bag to a metal part of your VMEbus computer chassis before removing the board from the bag.

2. Remove the board from the bag and inspect the board for loose components or any other sign of damage. Notify National Instruments if the board appears damaged in any way. DO NOT install a damaged board into your computer.

Section Two General Description

This section contains the physical and electrical specifications for the GPIB-1014P and describes the characteristics of key interface board components, including a functional block diagram as well as illustrations of applications in test and measurement configurations.

Physical Characteristics

The GPIB-1014P measures 160 by 100 mm and is supplied with a standard 24-pin GPIB connector mounted on the front panel. The card is available with both single- and double-height metal front panels (.8 in. width). A DIN 41612 96-pin connector connects the GPIB-1014P to the VMEbus backplane.

Electrical Characteristics

All integrated circuit drivers and receivers used on the GPIB-1014P meet the requirements of the VMEbus Specification and the IEEE-1014 standard. Table 2-1 contains a list of the VMEbus signals used by the GPIB-1014P and the device used to interface to each signal.

Note: The asterisk (*) after the bus signal indicates the signal is active low.

Table 2-1. GPIB-1014P Signals

Driver Device Receiver Device

Bus Signals Part Number Part Number

D00-D07 F245 F245

A15-A04 LS2521

AM4-AM3,AM0,AM1 LS2521

DS0*,WRITE*,IACK*,IACKIN*, LS240 SYSRESET*, SYSCLK*

LWORD*,AM5,AM2 F20

(continues)

General Description Section Two

Table 2-1. GPIB-1014P Signals (continued)

Driver Device Receiver Device

Bus Signals Part Number Part Number

DTACK* F38 LS240

IACKOUT* F20 –

IRQ1*through IRQ7* F38 –

AS*,DS1*,WRITE* – ALS244

A03 through A01 – ALS244

The GPIB transceivers meet the requirements of the IEEE-488 standard. The components used are as follows:

Transceivers Component Designation

Data Transceivers 75160 Control Transceivers 75162

Note: Current load is typically 0.5 A (1 A maximum).

VMEbus Characteristics

The following paragraphs describe both modules on the GPIB-1014P: slave and interrupter. Table 2-3 later in this section summarizes the capabilities of these modules.

VMEbus Slave-Addressing

The GPIB-1014P occupies 16 bytes of consecutive memory addresses located in the A16 (short) Input/Output (I/O) space. These addresses are used to access the GPIB Talker/Listener/Controller (TLC). As a VMEbus slave, it only responds when the address modifier (AM) lines specify a short supervisory access (AM code = 2D) or short non-privileged access (AM code = 29). An onboard jumper allows selection of privileged or non-privileged access to the board.

The board responds to 16-bit addresses. It compares address lines A04 through A15 with its hardware-programmable base address (see Base Address in Section Three) to generate its board select signal. The Talker/Listener/Controller (TLC) decodes the remaining address lines, A01 through A03, and the data strobe DSO* into eight memory-mapped interface register addresses. The GPIB TLC (µPD7210) interface registers are addressed relative to the base address of the board as shown in Table 2-2.

GPIB-1014P User Manual 2-2 © National Instruments Corporation

Section Two General Description

Table 2-2. µPD7210 Internal GPIB Interface Registers

Address (Base

+ Hex Offset) Mode Register Size

1 R Data In (DIR) 8 bits 1 W Control/Data Out (CDOR) 8 bits 3 R Interrupt Status 1 (ISR1) 8 bits 3 W Interrupt Mask 1 (IMR1) 8 bits 5 R Interrupt Status 2 (ISR2) 8 bits 5 W Interrupt Mask 2 (IMR2) 8 bits 7 R Serial Poll Status (SPSR) 8 bits 7 W Serial Poll Mode (SPMR) 8 bits 9 R Address Status (ADSR) 8 bits

9 W Address Mode (ADMR) 8 bits B R Command Pass Through (CPTR) 8 bits B W Auxiliary Mode (AUXMR) 8 bits

D R Address 0 (ADR0) 8 bits D W Address (ADR) 8 bits

F R Address 1 (ADR1) 8 bits F W End of String (EOSR) 8 bits

VMEbus Slave-Data

As discussed previously, the GPIB-1014P can function as a VMEbus slave, decoding memory addresses and commands from a VMEbus master. It is designed to accommodate address pipelining as well as Address Only (ADO) cycles. All data is transferred to and from the VMEbus with lines D00 through D07. In VMEbus terminology, the slave module of the board is designated as A16/D08(0). The board does not implement Unaligned Transfer (UAT), Block Transfer (BLT), and Read-Modify-Write (RMW) cycles.

General Description Section Two

Interrupter

Interrupt events that originate from the TLC are as follows:

• GPIB Data In (DI)

• GPIB Data Out (DO)

• END message received (END RX)

• GPIB Command Out (CO)

• Remote mode change (REMC)

• GPIB handshake error (ERR)

• Lockout change (LOKC)

• Address Status Change (ADSC)

• Secondary Address received (APT)

• Service Request received (SRQI)

• Trigger command received (DET)

• Device Clear received (DEC RX)

• Unrecognized Command received (CPT) All 13 interrupt events are wire-ORed in the TLC to a single signal designated INT on the interface

board. When one of these events occurs, INT goes high and one of the interrupt request lines (IRQ1* through IRQ7*) is driven low. You select the interrupt request line by means of an onboard jumper. You set the interrupt priority via three hardware switches (U28). The encoded value of the priority must match the level of the interrupt request line. See Interrupt Request Line Selection in Section Three for more information on setting the interrupt level.

The onboard hardware implements the VMEbus interrupt acknowledge protocol. The interrupter drives the VMEbus with an 8-bit Status/ID byte (vector) during an interrupt acknowledge cycle. This Status/ID byte is set by an onboard 8-position Dual In-line Package (DIP) switch (U7). After the interrupt handler reads the Status/ID byte from the data bus, it releases the data strobe DS0* to high. Upon seeing DS0* high, the interrupter releases the data bus and the interrupt request line. This implies that the GPIB-1014P interrupter is a Release On Acknowledge (ROAK) interrupter.

Note: Even though the interrupt request line is no longer driven, the TLC Interrupt (INT) line

remains asserted until it is cleared in the interrupt service routine by reading the appropriate status register (ISR1 or ISR2). Clearing the TLC INT line in the interrupt routine enables further interrupts from the GPIB-1014P.

GPIB-1014P User Manual 2-4 © National Instruments Corporation

Section Two General Description

VMEbus Modules Not Provided

Because the GPIB-1014P is not designed to be VMEbus System Controller, it does not have the following modules:

• Master

• Bus Timer

• Arbiter

• Interrupt Handler

• IACK Daisy Chain Driver

• System Clock Driver

• Serial Clock Driver

• Power Monitor

Diagnostic Aids

The GPIB-1014P is designed to allow stand-alone verification of I/O functions. See Section Seven, GPIB-1014P Diagnostic and Troubleshooting Test Procedures, for details.

Data Transfer Features

The GPIB-1014P can be used to transfer data to and from the GPIB using programmed I/O. Typical transfer rates range from 10 to 80 kbytes/sec. Data transfer rates approaching 1 Mbyte/sec can be obtained with very high performance microprocessors and driver software. The actual transfer rate for any particular GPIB system is a function of several factors including the following:

• Response time of the GPIB devices involved

• Microprocessor speed and operating system and application program overhead

• Interrupt service response time

GPIB-1014P Functional Description

In the simplest terms, the GPIB-1014P can be thought of as a bus translator, converting messages and signals present on the VMEbus into appropriate GPIB messages and signals. Expressed in GPIB terminology, the GPIB-1014P implements GPIB interface functions for communicating with other GPIB devices and device functions for communicating with the central processor and memory. Expressed in VMEbus terminology, the GPIB-1014P is an interface to the outside world.

General Description Section Two

Figure 2-1 and Figure 2-2 show typical applications for the GPIB-1014P. In Figure 2-2, the GPIB-1014P is used to interface an assortment of test instruments to a VMEbus computer system, which then functions as an intelligent System Controller. This is the traditional role of the GPIB.

In Figure 2-2, the GPIB-1014P is used along with other National Instruments interface boards to connect a VMEbus computer to other processors in order to transfer information or to perform other communication functions.

Device A

VMEbus Computer with GPIB-1014P

Able to Talk, Listen, and Control

Device C

Digital

Voltmeter

Able to Talk

and Listen

8 Lines

3 Lines

Frequency

Counter

Able to Talk

Device B

Printer

Able to Listen

Data Lines DIO1-DIO8

Handshake Lines DAV (Data Valid)

NRFD (Not Ready for Data) NDAC (Not Data Accepted)

Management Lines

5 Lines

IFC (Interface Clear) ATN (Attention) SRQ (Service Request) REN (Remote Enable) EOI (End or Identify)

Figure 2-1. GPIB-1014P with a VMEbus Computer

GPIB-1014P User Manual 2-6 © National Instruments Corporation

Section Two General Description

R&D Lab

Microprocessor

Work Station

VMEbus Computer with

GPIB-1014P IEEE-488 Interface

Computer

Center

IBM PC with GPIB-PC

IEEE-488 Interface

GPIB-100

Bus Extender

Up to

300 Meters

(RS-422)

GPIB-100

Bus Extender

Production

& Testing

PDP 11/44 with GPIB11-2

IEEE-488 Interface

S-100 Computer

GPIB-696P IEEE-488 Interface

Figure 2-2. GPIB-1014P in a Multiprocessor Application

GPIB-1014P User Manual 2-8 © National Instruments Corporation

AM5-AM0

A15-A01

A03-A01

Figure 2-3 is a block diagram of the GPIB-1014P.

General Description Section Two

Figure 2-3. GPIB-1014P Block Diagram

LWORD*

DSO*

IACK*

VMEbus

WRITE* DTACK*

IACKIN* IACKOUT*

DO7-DO0

AS*,

DS1*

IRQ1*-

IRQ7*

Bus Address

Decoding

Timing and

Data

Direction

Control

Interrupt

Logic

Data Bus

Transceivers

D7-D0

WR* RD* CS*

INT

LOCAL BUS

µPD7210

TLC

System

Controller

Select

75160A

Transceiver

75162A

Transceiver

SAC

GPIB

DI08*-

DI01*

SRQ*, ATN*

EOI*, DAV*

NRFD*, NDAC*

IFC*, REN*

Section Two General Description

The interface consists of these major components which are discussed in greater detail in Section Six.

• VMEbus Interface Consists of the buffers, drivers, and transceivers for the address, data, status, and control lines used on the VMEbus, plus other logic circuitry that converts internal signals to bus-compatible signals.

• Address Decoder Recognizes when the VMEbus master addresses one of the GPIB-1014P registers and generates the appropriate strobe to effect the data transfer.

• Clock and Reset Circuitry Monitors the VMEbus utility signals to generate the 8 MHz clock used by the TLC and to detect System Reset.

• Timing State Machine Controls the timing of accesses to the GPIB-1014P from the VMEbus.

• Interrupter Implements the correct VMEbus priority interrupt protocol, allowing the GPIB-1014P to request and respond to an interrupt acknowledge cycle. All interrupt conditions are also detectable by polling.

• GPIB TLC (NEC µPD7210) Implements many of the GPIB interface functions, either independently or with assistance of or interpretation by the controlling program. Together with special transceivers, the TLC forms the GPIB interface side of the GPIB-1014P.

General Description Section Two

Table 2-3 lists the capabilities of the GPIB-1014P in terms of the IEEE-488 standard codes.

Table 2-3. GPIB-1014P IEEE-488 Interface Capabilities

Capability Code Description

SH1 Complete Source Handshake capability

AH1 Complete Acceptor Handshake capability DAC and RFD

Holdoff on certain events

T5 Complete Talker capability

Basic Talker Serial Poll Talk Only mode Unaddressed on MLA Send END or EOS Dual primary addressing

TE5 Complete Extended Talker capability

Basic Extended Talker Serial Poll Talk Only mode Unaddressed on MSA*LPAS Send END or EOS Dual primary addressing

L3 Complete Listener capability

Basic Listener Listen Only mode Unaddressed on MTA Detect END or EOS Dual extended addressing with software assist

LE3 Complete Extended Listener capability

Basic Listener Listen Only mode Unaddressed on MSA*TPAS Detect END or EOS Dual extended addressing with software assist

(continues)

GPIB-1014P User Manual 2-10 © National Instruments Corporation

Section Two General Description

Table 2-3. GPIB-1014P IEEE-488 Interface Capabilities (continued)

Capability Code Description

SR1 Complete Service Request capability

RL1 Complete Remote/Local capability with software

interpretation

PP1 Remote Parallel Poll configuration

PP2 Local Parallel Poll configuration with software assist

DC1 Complete Device Clear capability with software

interpretation

DT1 Complete Device Trigger capability with software

interpretation

C1, 2, 3 ,4, 5 Complete Controller capability

System Controller Send IFC and take charge Send REN Respond to SRQ Send interface messages Receive control Pass control Pass Control to Self Parallel Poll Take control synchronously

E1, E2 Tri-state bus drivers with automatic switch to open

Collector drivers during Parallel Poll

The GPIB-1014P has complete Source and Acceptor Handshake capability. The GPIB-1014P can operate as a basic Talker or Extended Talker and can respond to a Serial Poll. It can be placed in a Talk Only mode, and it is unaddressed to talk when it receives its listen address. The interface can operate as a basic Listener or Extended Listener. It can be placed in a Listen Only mode, and it is unaddressed to listen when it receives its talk address. The GPIB-1014P has full capabilities for requesting service from another Controller. It can be placed in local mode, but the interpretation of remote versus local mode is software-dependent. The interface has full Parallel Poll capability, although local configuration requires software assistance. It also has Device Clear and Trigger

General Description Section Two

capability, but the interpretation is software dependent. All Controller functions as specified by the IEEE-488 standard are included in the GPIB-1014P. These include the capability to:

• Be System Controller

• Initialize the interface

• Send Remote Enable

• Respond to Service Request

• Send multiline command messages

• Receive control

• Pass control

• Conduct a Parallel Poll

• Take control synchronously or asynchronously

Table 2-4 indicates the GPIB-1014P IEEE-1014 compliance levels.

Table 2-4. GPIB-1014P IEEE-1014 Compliance Levels

Compliance Notation Description

Bus Slave Compliance Levels D08(O) 8-bit data path to TLC A16 Responds to 16-bit short I/O addresses when specified

on the address modifier lines

ADO Accommodates Address Only cycles

Interrupter Compliance Levels D08(O) Provides an 8-bit status/ID byte on D00 through D07 ROAK Releases its interrupt request line when the interrupt

handler acknowledges the interrupt

I1 through I7 Full support of all seven interrupt priority levels and

interrupt acknowledge daisy chain

GPIB-1014P User Manual 2-12 © National Instruments Corporation

Section Three Configuration and Installation

This section describes the configuration and installation of the GPIB-1014P.

Configuration

Before installing the GPIB-1014P in the VMEbus backplane, the following options must be configured with hardware jumpers or switches that are located on the GPIB-1014P interface board:

• Access Mode (W2)

• VMEbus Base Address (U28, U29)

• VMEbus Interrupt Configuration (W3)

• Interrupt Status/ID Vector (U7)

• GPIB Cable Shield Grounding (W1)

Section Three Configuration and Installation

Access Mode

The GPIB-1014P can be configured to allow Supervisor (privileged) or Supervisor-and-User (nonprivileged) access using hardware jumper W2 as shown in Figure 3-2. To configure the board for privileged access only, place the jumper on the side labeled S as shown in Figure 3-2a. To configure the board for non-privileged access, place the jumper on the side labeled NP as shown in Figure 3-2b. The default setting for the GPIB-1014P is for non-privileged access. In the Supervisor (privileged) mode, the GPIB-1014P only responds to Address Modifier (AM) code 2D. In the Supervisor-and-User (non-privileged) mode, the board responds to AM codes 2D or 29. (Refer to the ANSI/IEEE Std. 1014-1987, IEEE Standard for a Versatile Backplane Bus: VMEbus for more information on Supervisor and Non-privileged modes.)

•

W2I/O

•

a. Supervisor only

(Privileged)

b. Supervisor-and-User

(Non-privileged)

Figure 3-2. Access Selection

VMEbus Base Address

The address space required by the GPIB-1014P consists of one block of 16 consecutive byte addresses. The GPIB-1014P responds only to AM codes that indicate short (16-bit) addressing (See Access Mode previously in this section). The GPIB-1014P decodes the 12 most significant address bits (A04 through A15) as the base address. The Talker/Listener/Controller (TLC) internally decodes the Register Select signals, which are address bits A01 through A03.

Configuration and Installation Section Three

Dual In-line Package (DIP) switches U28 and U29 select the base address. U29 selects address lines A8 through A15, and U28 selects address lines A4 through A7. Press the side labeled 0 to select a logical zero for the corresponding address bit. Press the side labeled 1 to select a logical one. Figure 3-3 shows the configuration for the base address default setting 1000 hex.

Key

= the side you press down for Base Address 1000 hex = not involved in Base Address selection

This side down for logic 0This side down for logic 1

1 23456

I1 I2

I3 A4

U28

U29

1 23 4 5

This side down for logic 0This side down for logic 1

A5 A6

A8 A9

A10 A11 A12

A13 A14 A15

Figure 3-3. Configuration for VMEbus Base Address 1000 hex (default setting)

GPIB-1014P User Manual 3-4 © National Instruments Corporation

Section Three Configuration and Installation

VMEbus Interrupt Configuration

The GPIB-1014P contains circuitry that permits it to request service by driving one of the VMEbus interrupt request lines. The GPIB-1014P responds to an interrupt acknowledge cycle of correct priority by providing an 8-bit vector (status byte) that is used to locate the appropriate interrupt service routine. The following paragraphs explain the actions that must be performed to configure the interrupt request line, the interrupt priority, and the status/ID byte or interrupt vector.

Interrupt Request Line Selection

The VMEbus provides seven interrupt request lines IRQ1* to IRQ7*. The GPIB-1014P can be configured to drive any one of these seven lines. The jumper shown in Figure 3-4 is used to connect the interrupt request from the GPIB-1014P to one of the VMEbus interrupt request lines. The jumper is placed on the pins that correspond to the desired interrupt request line.

Note: The interrupt priority code must be set to correspond to the interrupt request line. Figure 3-4a shows the jumper configured to select interrupt request line IRQ2*, while Figure 3-4b

shows the configuration for selecting IRQ4*. The default setting for the GPIB-1014P is IRQ2*.

• •

a. Select Interrupt Request Line Configured

IRQ

• •

to IRQ2*

(Default setting)

• •

b. Select Interrupt Request Line Configure

• •

IRQ

• •

to IRQ4*

• •

Figure 3-4. VMEbus Interrupt Line Selection

Note: An asterisk implies that the signal is active low. Interrupt Priority Code

The interrupt priority code is used to identify an interrupt acknowledge cycle intended for the GPIB1014P. Three bits, I1 through I3, represent the interrupt priority code of the GPIB-1014P. The encoded value of these three bits must correspond to the interrupt request line used (1 through 7) by the board, I1 is the least significant bit. Three switches located at U28 set these bits. Press the side labeled 0 to select a logical zero for the corresponding address bit. Press the side labeled 1 to select a logical one. Figure 3-5a shows the switch configuration for using IRQ2* while Figure 3-5b shows the switch configuration for using IRQ4*. The default setting for the GPIB-1014P is IRQ2*.

Configuration and Installation Section Three

Key

= the side you press down for Interrupt Priority Code selectio = not involved in Interrupt Priority Code selection

This side down for logic 0This side down for logic 1

1 23456

I1 I2

2 I3 A4

A5 A6

U28

a. Switch configuration using IRQ2*

(Default setting)

This side down for logic 0This side down for logic 1

1 23456

I1 I2

4 I3 A4

A5 A6

U28

b. Switch configuration using IRQ4*

Figure 3-5. VMEbus Interrupt Priority Code Selection

GPIB-1014P User Manual 3-6 © National Instruments Corporation

Section Three Configuration and Installation

Interrupt Status/ID Vector Selection

Switches located at U7 configure the interrupt status/ID vector, which is provided by the GPIB1014P during an interrupt acknowledge cycle. This interrupt vector consists of eight bits, labeled V0 through V7, as shown in Figure 3-6. Bit V7 corresponds to the most significant bit while V0 corresponds to the least significant. Press the side labeled 0 to select a logical zero for the corresponding address bit. Press the side labeled 1 to select a logical one. Figure 3-6 shows the configuration for a status/ID byte value 1A hex.

Key

= the side you press down for Status/ID Byte 1A hex

This side down for logic 0This side down for logic 1

1 23 4 5

V6 V5 V4 V3

V2 V1 V0

Figure 3-6. Status/ID Byte 1A hex

Configuration and Installation Section Three

GPIB Cable Shield Grounding

The GPIB cable shield connects to the chassis ground through the metal front panel on the GPIB1014P. The cable shield can also be connected to the system logic ground if desired. Usually, the GPIB cable shield is grounded only at the GPIB System Controller. Set hardware jumper W1 to the side labeled CON to short or connect the GPIB cable shield to VMEbus digital logic ground. Place the jumper on the side labeled ISO to leave the GPIB cable shield isolated. Select one configuration depending on whether or not the GPIB-1014P is the GPIB System Controller and whether or not the GPIB cable shield is grounded elsewhere. Figure 3-7 shows the two possible configurations. The GPIB-1014P is shipped in the isolated or unconnected configuration.

ISO

SHLD

a. Shield Isolated or Unconnected

(Default setting)

•

CON

Figure 3-7. GPIB Cable Shield Grounding

ISO

SHLD

b. Shield Grounded or Connecte

•

CON

GPIB-1014P User Manual 3-8 © National Instruments Corporation

Section Three Configuration and Installation

Installation

The GPIB-1014P is a single-height board that interfaces to the VMEbus P1 and is available with either a single- or double-height metal front cover plate. The following paragraphs describe the GPIB-1014P interface to the VMEbus backplane and to the IEEE-488 bus.

Verification of System Compatibility

The GPIB-1014P monitors and drives those signals required by the IEEE-1014 Standard and is compatible with certified VMEbus systems. Compare the signals listed in Table 3-1 to those used by the VMEbus system in which the GPIB-1014P will be installed to ensure that the GPIB-1014P provides all the necessary signals needed by the VMEbus system and vice versa.

Table 3-1. GPIB-1014P Pin Assignment on VMEbus Connector P1

Pin No. Signal Used Signal Not Used Pin No. Signal Used Signal Not Used

A1 D00 A17 GND A2 D01 A18 AS* A3 D02 A19 GND A4 D03 A20 IACK* A5 D04 A21 IACKIN* A6 D05 A22 IACKOUT* A7 D06 A23 AM4 A8 D07 A24 A07 A9 GND A25 A06 A10 SYSCLK A26 A05 A11 GND A27 A04 A12 DS1* A28 A03 A13 DS0* A29 A02 A14 WRITE* A30 A01 A15 GND A31 -12V A16 DTACK* A32 + 5V

B1 BBSY* B17 AM1 B2 BCLR* B18 AM2 B3 ACFAIL* B19 AM3 B4 BG0IN* B20 GND B5 BG0OUT* B21 SERCLK B6 BG1IN* B22 SERDAT B7 BG1OUT* B23 GND B8 BG2IN* B24 IRQ7* B9 BG2OUT* B 25 IRQ6* B10 BG3IN* B2 6 IRQ5* B11 BG3OUT* B27 IRQ4* B12 BR0* B28 IRQ3* B13 BR1* B29 IRQ2* B14 BR2* B30 IRQ1* B15 BR3* B31 +5V STDBY B16 AM0 B32 +5V

(continues)

Configuration and Installation Section Three

Table 3-1. GPIB-1014P Pin Assignment on VMEbus Connector P1 (continued)

Pin No. Signal Used Signal Not Used Pin No. Signal Used Signal Not Used

C1 D08 C17 A21 C2 D09 C18 A20 C3 D10 C19 A19 C4 D11 C20 A18 C5 D12 C21 A17 C6 D13 C22 A16 C7 D14 C23 A15 C8 D15 C24 A14 C9 GND C2 5 A1 3 C10 SYSFAIL* C26 A12 C11 BERR* C27 A11 C12 SYSRESET* C28 A10 C13 LWORD* C29 A09 C14 AM5 C30 A08 C15 A23 C31 +12V C16 A22 C32 +5V

Verification Testing

A verification test can be run to ensure that the board has not been damaged during shipment and also to ensure that the board has been configured correctly. This requires an interactive control program or an equivalent mechanism, such as front panel control switches or front panel emulator, that provides a way to load and read memory and I/O addresses.

The tests presented in Section Seven of this manual consist of a series of steps written in a pseudo (processor-independent) language with instructions. The steps generally involve writing data to specific GPIB-1014P device registers followed by reading other GPIB-1014P registers to verify that the programming is correct. These tests exercise virtually all of the major functions of the GPIB-1014P, including I/O communications and GPIB communications. All functions except GPIB communications can be performed as stand-alone operations (that is, without another GPIB device). To completely check the GPIB functions, you must use a bus tester or analyzer (such as National Instruments GPIB-400 or GPIB-410) that can monitor and control GPIB signal lines; emulate GPIB Talker, Listener, and Controller devices; and single-step through the Source and Acceptor Handshakes.

Cabling

Optional cables are available to connect the GPIB-1014P to other GPIB devices. Connect the cable to the GPIB-1014P at the standard GPIB connector labeled J1 at the top of the interface board. (The GPIB connector protrudes through the metal front cover plate.)

GPIB-1014P User Manual 3-10 © National Instruments Corporation

Section Three Configuration and Installation

Figure 3-8 shows the signals present on the GPIB cable connector.

10 11 12

21 22 23 24

DIO5* DIO6*

DIO7* DIO8* REN* GND (TW PAIR W/DAV*) GND (TW PAIR W/NRFD*)

GND (TW PAIR W/NDAC*) GND (TW PAIR W/IFC*) GND (TW PAIR W/SRQ*) GND (TW PAIR W/ATN*) SIGNAL GROUND

DIO1* DIO2*

DIO3* DIO4*

EOI*

DAV*

NRFD*

NDAC*

IFC* SRQ* ATN*

SHIELD

Figure 3-8. GPIB Cable Connector

Section Four Register Bit Descriptions

This section presents detailed information on the use of the GPIB-1014P Talker/Listener/Controller registers.

Register Map

The register map for the GPIB-1014P is shown in Table 4-1. This table gives the register name, the register address, the type of the register, and the size of the register in bits.

Table 4-1. GPIB-1014P Register Map

GPIB Interface Register Group:

Data In Register Base address + 1 Read only 8-bit Command/Data Out Register Base address + 1 Write only 8-bit Interrupt Status Register 1 Base address + 3 Read only 8-bit Interrupt Mask Register 1 Base address + 3 Write only 8-bit Interrupt Status Register 2 Base address + 5 Read only 8-bit Interrupt Mask Register 2 Base address + 5 Write only 8-bit Serial Poll Status Register Base address + 7 Read only 8-bit Serial Poll Mode Register Base address + 7 Write only 8-bit Address Status Register Base address + 9 Read only 8-bit Address Mode Register Base address + 9 Write only 8-bit Command Pass Through Register Base address + B Read only 8-bit Auxiliary Mode Register Base address + B Write only 8-bit Hidden Registers

Internal Counter Register Base address + B Write only 8-bit Parallel Poll Register Base address + B Write only 8-bit Auxiliary Register A Base address + B Write only 8-bit

(continues)

Table 4-1. GPIB-1014P Register Map (continued)

Auxiliary Register B Base address + B Write only 8-bit

Auxiliary Register E Base address + B Write only 8-bit Address Register 0 Base address + D Read only 8-bit Address Register Base address + D Write only 8-bit Address Register 1 Base address + F Read only 8-bit End Of String Register Base address + F Write only 8-bit

Register Sizes

All program registers on the GPIB-1014P are 8-bit registers.

Register Description Format

The remainder of this section discusses each of the GPIB-1014P registers in the order shown in Table 4-1. Each register group is introduced, followed by a detailed bit description of each register. The individual register description gives the address, type, word size, and bit map of the register, followed by a description of each bit.

The register bit map shows a diagram of the register with the most significant bit (bit 7 for an 8-bit register) shown on the left, and the least significant bit (bit 0) shown on the right. A rectangle is used to represent each bit. Each bit is labeled with a name inside its rectangle. An asterisk (*) after the bit name indicates that the signal is active low. An asterisk is equivalent to an overbar.

In many of the registers, several bits are labeled with an X, indicating don't care bits. When a register is read, these bits may appear set or cleared but should be ignored because they have no significance. When a register is written to, these bit locations should be cleared.

Terminology

The terms set, set true, and set to one are synonymous. The terms clear, set false, set to zero, and clear to zero are synonymous. The meanings of preset and reset are determined by the context in

which they are used. Bit signatures are written in uppercase letters. The term addressed means the interface has been configured to perform a function from the GPIB

side, while the term programmed means that it has been configured from the VMEbus side. This distinction is important to make because many functions, such as making the interface a Talker or Listener, can be activated from either side.

GPIB-1014P User Manual 4-2 © National Instruments Corporation

Section Four Register Bit Descriptions

Where it is necessary to specify a particular bit of a register, the bit position appears as a decimal number in square brackets after the mnemonic (for example, ISR1[1] indicates the DI bit of Interrupt Status Register 1).

A minus sign (-) is used to indicate logical negation. An ampersand (&) represents AND, and a plus sign (+) represents OR in logical expressions.

All numbers, except register offsets, are decimal unless specified otherwise. Register offsets are given in hexadecimal.

Uppercase mnemonics are used for control, status, data registers, register contents, and interface functions, as well as GPIB remote messages, commands, and logic states as defined in the IEEE488 standard.

After a mnemonic of a name has been defined, the mnemonic is used thereafter. Appendix F contains a list of all mnemonics used in this manual along with their type and name. Mnemonics are assigned to messages, states, registers, bits, functions, and integrated circuits. Most mnemonics contain a clue to their meaning. Table 4-2 contains a list of clues to look for.

Table 4-2. Clues to Understanding Mnemonics

Clue Mnemonic Probably Stands For:

Ends in IE Interrupt enable bit

Ends in EN Enable bit

4 letters, Interface function as defined in the ends in S IEEE-488 standard

Ends in R, R0, R1, R2 GPIB program register

3 letters, uppercase Remote GPIB message

3 letters, lowercase Local GPIB message

Interface Registers

All program registers are GPIB interface registers; eight are read only, eight are write only, and five are hidden or indirectly accessible. All are located within the NEC µPD7210 Talker/Listener/Controller (TLC) integrated circuit. Each of the 16 interface registers is addressed relative to the GPIB-1014P VMEbus base address which is set with DIP switches (refer to Base Address in Section Three).

Figure 4-1 shows the µPD7210 Interface registers, the bit mnemonics of each, its read/write accessibility, and its relative address. Figure 4-2 shows the hidden GPIB interface registers and illustrates the method of writing to those registers via the Auxiliary Mode Register. A detailed function description of all 16 interface registers is provided in the paragraphs following the figures.

GPIB-1014P User Manual 4-4 © National Instruments Corporation

Section Four Register Bit Descriptions

Legend

(Contents of Read Register)

Bit

(Contents of Write Register)

Bit

DIR CDOR

ISR1 IMR1

ISR2 IMR2

SPSR

SPMR

ADSR

ADMR

Address Offset

(hex)

DI7

CDO7 CDO6

CPT APT DET END RX DEC ERR DO DI

CPT IE APT IE DET IE END IE DEC IE ERR IE DO IE DI IE

INT SRQI LOK

0 SRQI IE DMAO DMAI CO IE LOKC IE REMC IEADSC IE

S8 PEND S8 rsv S6

CIC

ton lon TRM1 TRM0

DI6

ATN*

DI5 DI4 DI3

CDO5

SPMS

CDO4 CDO3 CDO2 CDO1 CDO0

REM

LPAS TPAS LA TA MJMN

CO LOKC REMC ADSC

S5 S5

S4 S4 S3

0 0 ADM1

DI2

S3 S2 S1

DI1

DI0

ADM0

Read/

Write

R W

CPTR AUXMR

ADR0 ADR

ADR1

EOSR

CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0

CNT2 CNT1 CNT0 COM4 COM3 COM2 COM1 COM0

X DT0 DL0 AD5-0 AD4-0

ARS DT DL

EOI DT1 DL1 AD5-1 AD4-1 AD3-1 AD2-1 AD1-1

EOS7 EOS6 EOS0EOS5 EOS4 EOS3 EOS2 EOS1

Note: X indicates a don't care bit.

AD5 AD4

AD3-0

AD3

AD2-0 AD1-0

AD2 AD1

R W

Figure 4-1. µPD7210 Interface Registers

Control Code Command Code

AUXMR

CNT2 CNT1 CNT0 COM4 COM3 COM2 COM1 COM0

When CNT2-CNT0 is:

ICR is loaded with:

010

011

100

110

101

0 CLK3 CLK2 CLK1 CLK0

U S P3 P2

AUXRA is loaded with:

BIN XEOS REOS HLDE

AUXRB is loaded with:

ISS INV TRI SPEOI

AUXRE is loaded with:

0 0 0 DHDT DHDC

Figure 4-2. Writing to the Hidden Registers

PPR is loaded with:

HLDA

CPT

ENABLE

GPIB-1014P User Manual 4-6 © National Instruments Corporation

Section Four Register Bit Descriptions

Data In Register (DIR)

VMEbus Address: Base Address + 1 (hex) Attributes: Read Only

7 654 3210

DI7

DI6 DI5 DI4 DI3 DI2 DI1 DI0

The Data In Register (DIR) is used to move data from the GPIB to the VMEbus when the interface is a Listener. Incoming information is separately latched by this register and is not destroyed by a write to the Command/Data Out Register (CDOR) which locates at the same address. The GPIB Ready For Data (RFD) message is held false until the byte is removed from the DIR by an I/O read from a VMEbus master. The Acceptor Handshake (AH) completes automatically after the byte has been read. In RFD Holdoff mode (refer to Auxiliary Register A, later in this section) the GPIB Handshake is not finished until the Finish Handshake (FH) auxiliary command is issued telling the TLC to release the Holdoff. By using the RFD Holdoff mode, the same byte can be read several times, or a GPIB Talker that is ready to provide more data can be held off until the program is ready to proceed.

DI0 is the least significant bit of the data byte and corresponds to GPIB DIO1. DI7 is the most significant bit of the data byte and corresponds to GPIB DIO8.

Bit Mnemonic Description

7-0r DIR[7-0] Data In Bits 7 through 0

Command/Data Out Register (CDOR)

VMEbus Address: Base Address + 1 (hex) Attributes: Write Only

7 654 3210

CDO7 CDO6 CDO5 CDO4 CDO3 CDO2 CDO1 CDO0

The Command/Data Out Register (CDOR) is used to move data from the VMEbus to the GPIB when the TLC is the GPIB Talker or the Active Controller. Outgoing data is separately latched by this register and is not destroyed by a read of the DIR which is located at the same address. When a byte is written to the CDOR, the TLC GPIB Source Handshake (SH) function is initiated and the byte is transferred to the GPIB.

Bit Mnemonic Description

7-0w CDO[7-0] Command/Data Out Bits 7 through 0

GPIB-1014P User Manual 4-8 © National Instruments Corporation

Section Four Register Bit Descriptions

Interrupt Status Register 1 (ISR1)

VMEbus Address: Base Address + 3 (hex) Attributes: Read Only,

Bits are cleared when read

Interrupt Mask Register 1 (IMR1)

VMEbus Address: Base Address + 3 (hex) Attributes: Write Only

7 654 3210

CPT

CPT IE

APT

APT IE

DET

DET IE

END RX

END IE

DEC

DEC IE

ERR

ERR IE

DO IE

DI IE

ISR1 is composed of eight interrupt status bits. IMR1 is composed of eight interrupt enable bits which directly correspond to the interrupt status bits in ISR1. As a result, ISR1 and IMR1 service eight possible interrupt conditions, where each condition has an interrupt status bit and an interrupt enable bit associated with it. If the Interrupt Enable bit is true when the corresponding status condition or event occurs, a hardware interrupt request is generated. Bits in ISR1 are set and cleared by the TLC regardless of the status of the interrupt enable bits in IMR1. If an interrupt condition occurs at the same time ISR1 is being read, the TLC holds off setting the corresponding status bit until the read has finished.

Bit Mnemonic Description

7r CPT Command Pass-Through Bit 7w CPT IE Command Pass-Through Interrupt Enable Bit

CPT is set on:

[UCG + ACG & (TADS + LADS)] & undefined & ACDS & (CPTENAB) + UDPCF & SCG & ACDS & CPT ENAB

CPT is cleared by:

pon + (Read ISR1)

Notes:

UCG: GPIB Universal Command Group message ACG: GPIB Addressed Command Group message TADS: GPIB Talker Addressed State LADS: GPIB Listener Addressed State defined: GPIB command automatically recognized and executed

by TLC

Bit Mnemonic Description

undefined: GPIB command not automatically recognized and

executed by TLC ACDS: GPIB Accept Data State CPT ENAB: AUXRB[0]w UDPCF: Undefined primary command function (see below) SCG: GPIB Secondary Command Group message pon: power on reset TAG: GPIB Talk Address Group message LAG: GPIB Listen Address Group message Read ISR1: Bit is cleared immediately after it is read

UDPCF is set on:

[UCG + ACG & (TADS + LADS)] & undefined & ACDS & CPT ENAB

UDPCF is cleared on:

[(UCG + ACG) & defined + TAG + LAG] & ACDS + (-CPT ENAB) + pon

The CPT bit flags the occurrence of a GPIB command not recognized by the TLC, and all following GPIB secondary commands when the Command pass-through feature is enabled by the CPT ENAB bit, AUXRB[0]w. Any GPIB command message not decoded by the TLC is treated as an undefined command (for example, the Go To Local command, GTL). However, any addressed command is automatically ignored when the TLC is not addressed.

Undefined commands are read using the CPTR. The TLC holds off the GPIB Acceptor Handshake in the Accept Data State (ACDS) until the Valid auxiliary command function code, octal 017, is written to the AUXMR. If the CPT feature is not enabled, undefined commands are simply ignored.

6r APT Address Pass-Through Bit 6w APT IE Address Pass-Through Interrupt Enable Bit

APT is set by:

ADM1 & ADM0 & (TPAS + LPAS) & SCG & ACDS

APT is cleared by:

pon + (Read ISR1)

Notes:

ADM1: Address Mode Register bit 1, ADMR[1]w ADM0: Address Mode Register bit 0, ADMR[0]w

GPIB-1014P User Manual 4-10 © National Instruments Corporation

Section Four Register Bit Descriptions

Bit Mnemonic Description

TPAS: GPIB Talker Primary Addressed State LPAS: GPIB Listener Primary Addressed State SCG: GPIB Secondary Command Group ACDS: GPIB Accept Data State pon: power on reset Read ISR1: Bit is cleared immediately after it is read.

The APT bit indicates that a secondary GPIB address has been received and is available in the CPTR for inspection.

Note: The application program must check this bit when using TLC

address mode 3).

When APT is set, the DAC message is held and the GPIB handshake stops until either the Valid or Non-Valid auxiliary command is issued. The secondary address can be read from the CPTR.

5r DET Device Execute Trigger Bit 5w DET IE Device Execute Trigger Interrupt Enable Bit

DET is set by:

DTAS

DET is cleared by:

pon + (Read ISR1)

Notes:

DTAS: GPIB Device Trigger Active State pon: power on reset Read ISR1: Bit is cleared immediately after it is read.

The DET bit indicates that the GPIB Device Execute Trigger (DET) command has been received while the TLC was a GPIB Listener (the TLC has been in DTAS).

4r END RX End Received Bit 4w END IE End Received Interrupt Enable Bit

END RX is set by:

LACS & (EOI + EOS & REOS) & ACDS

END RX is cleared by:

pon + (Read ISR1)

Bit Mnemonic Description

Notes:

LACS: GPIB Listener Active State EOI: GPIB End Or Identify Signal EOS: GPIB End Of String message REOS: Reception Of GPIB EOS allowed, AUXRA[2]w

ACDS: GPIB Accept Data State pon: power on reset Read ISR1: Bit is cleared immediately after it is read.

The END RX bit is set when the TLC is a Listener and the GPIB uniline message, END, is received with a data byte from the GPIB Talker, or the data byte in the DIR matches the contents of the End Of String Register (EOSR).

3r DEC Device Clear Bit 3w DEC IE Device Clear Interrupt Enable Bit

DEC is set by:

DCAS

DEC is cleared by:

pon + (Read ISR1)

Notes:

DCAS: GPIB Device Clear Active State pon: power on reset Read ISR1: Bit is cleared immediately after it is read.

The DEC bit indicates that the GPIB Device Clear (DCL) command has been received or that the GPIB Selected Device Clear (SDC) command has been received while the TLC was a GPIB Listener (the TLC is in DCAS).

2r ERR Error Bit 2w ERR IE Error Interrupt Enable Bit

ERR is set by:

TACS & SDYS & DAC & RFD + SIDS & (Write CDOR) + (SDYS - SIDS)

ERR is cleared by:

pon + (Read ISR1)

GPIB-1014P User Manual 4-12 © National Instruments Corporation

Section Four Register Bit Descriptions

Bit Mnemonic Description

Notes:

TACS: GPIB Talker Active State SDYS: GPIB Source Delay State DAC: GPIB Data Accepted message RFD: GPIB Ready For Data message SIDS: GPIB Source Idle State (Write CDOR): Bit is set immediately after writing to the

Command/Data Out Register

SDYS->SIDS: Transition from GPIB Source Delay State to Source

Idle State pon: power on reset Read ISR1: Bit is cleared immediately after it is read.

The ERR bit indicates that the contents of the CDOR have been lost. ERR is set when data is sent over the GPIB without a specified Listener or when a byte is written to the CDOR during SIDS or during the SDYS to SIDS transition.

1r DO Data Out Bit 1w DO IE Data Out Interrupt Enable Bit

DO is set as:

(TACS & SGNS) becomes true

DO is cleared by:

(Read ISR1) + -(TACS) + -(SGNS)

Notes:

TACS:GPIB Talker Active State SGNS: GPIB Source Generate State Read ISR1: Bit is cleared immediately after it is read.

The DO bit indicates that the TLC is ready to accept another data byte from the VMEbus for transmission onto the GPIB when the TLC is the GPIB Talker. The DO bit is cleared when a byte is written to the CDOR and also when the TLC ceases to be the Active Talker.

0r DI Data In Bit 0w DI IE Data In Interrupt Enable Bit

DI is set by:

LACS & ACDS & -(Continuous Mode)

Bit Mnemonic Description

DI is cleared by:

pon + (Read ISR1) + (Finish Handshake) & (Holdoff Mode) + (Read DIR)

Notes:

LACS: GPIB Listener Active State ACDS: GPIB Accept Data State Continuous Mode: Listen

In Continuous Mode auxiliary command in effect pon: power on reset Read ISR1: Bit is cleared immediately after it is read Finish Handshake: Finish Handshake auxiliary command issued Holdoff Mode: RFD holdoff state Read DIR: Read Data In Register

The DI bit indicates that the TLC, as a GPIB Listener, has accepted a data byte from the GPIB Talker.

GPIB-1014P User Manual 4-14 © National Instruments Corporation

Section Four Register Bit Descriptions

Interrupt Status Register 2 (ISR2)

VMEbus Address: Base Address + 5 (hex) Attributes: Read Only,

Bits are cleared when read

Interrupt Mask Register 2 (IMR2)

VMEbus Address: Base Address + 5 (hex) Attributes: Write Only

7 654 3210

INT

SRQI

SRQI IE

LOK

DMAO

REM

DMAI

CO IE

LOKC

LOKC IE

REMC

REMC IE

ADSC IE

ADSC

ISR2 consists of six interrupt status bits and two TLC internal status bits. IMR2 consists of five interrupt enable bits and two TLC internal control bits. If the Interrupt Enable bit is true when the corresponding status condition or event occurs, a hardware interrupt request is generated. Bits in ISR2 are set and cleared regardless of the status of the bits in IMR2. If a condition occurs which requires the TLC to set or clear a bit or bits in ISR2 at the same time ISR2 is being read, the TLC holds off setting or clearing the bit or bits until the read is finished.

Bit Mnemonic Description

7r INT Interrupt Bit

This bit is the logical OR of all the enabled interrupt status bits in both ISR1 and ISR2, each one ANDed with its interrupt enable bit (refer below). There is no corresponding mask bit for INT. If the INT=1, the INT output pin of the TLC, signal GPIB IR, is asserted.

Note: Program the INT output pin of the TLC to be active high; see

description of AUXRB.

INT is set by:

(CPT & CPT IE) + (APT & APT IE) + (DET & DET IE) + (ERR & ERR IE) + (END RX & END IE) + (DEC & DEC IE) + (DO & DO IE) + (DI & DI IE) + (SRQI & SRQI IE) + (REMC & REMC IE) + (CO & CO IE) + (LOKC & LOKC IE) + (ADSC & ADSC IE)

Bit Mnemonic Description

Notes

CPT: Command Pass Through Bit CPT IE: Enable Interrupt on Command Pass Through Bit APT: Address Pass Through Bit APT IE: Enable Interrupt on Address Pass Through Bit DET: Device Execute Trigger Bit DET IE: Enable Interrupt on Device Execute Trigger Bit ERR: Error Bit ERR IE: Enable Interrupt on Error Bit END RX: End Received Bit END IE: Enable Interrupt on End Received Bit DEC: Device Clear Bit DEC IE: Enable Interrupt on Device Clear Bit DO: Data Out Bit DO IE: Enable Interrupt on Data Out Bit DI: Data In Bit DI IE: Enable Interrupt on Data In Bit SRQI: Service Request Input Bit SRQI IE: Enable Interrupt on Service Request Input Bit REMC: Remote Change Bit REMC IE: Enable Interrupt on Remote Change Bit CO: Command Output Bit CO IE: Enable Interrupt on Command Output Bit LOKC: Lockout Change Bit LOKC IE: Enable Interrupt on Lockout Change Bit ADSC: Address Status Change Bit ADSC IE: Enable Interrupt on Address Status Change Bit

7w 0 Reserved Bit

Write zero to this bit.

6r SRQI Service Request Input Bit 6w SRQI IE Service Request Input Interrupt Enable Bit

SRQI is set when:

(CIC & SRQ & -(RQS & DAV)) becomes true

SRQI is cleared by:

pon + (Read ISR2)

Notes:

CIC: GPIB Controller In Charge SRQ: GPIB Service Request message RQS: GPIB Request Service message DAV: GPIB Data Valid message

GPIB-1014P User Manual 4-16 © National Instruments Corporation

Section Four Register Bit Descriptions

Bit Mnemonic Description

pon: power on reset Read ISR2: Bit is cleared immediately after it is read.

The SRQI bit indicates that a GPIB Service Request (SRQ) message has been received while the TLC Controller function is active (CIC=1).

5r LOK Lockout Bit

LOK is used, along with the REM bit, to indicate the status of the TLC GPIB Remote/Local (RL) function. If set, the LOK bit indicates that the TLC is in Local With Lockout State (LWLS) or Remote With Lockout State (RWLS). LOK is a non-interrupt bit.

5w DMAO DMA Out Enable Bit

The DMA feature is not implemented. Do not set this bit.

4r REM Remote Bit

This bit is true whenever the TLC GPIB RL function is in one of two states: Remote State (REMS) or Remote With Lockout State (RWLS). The TLC RL function enters one of these states when the System Controller has asserted the Remote Enable line (REN), and the Controller-In-Charge addresses the TLC as a Listener.

4w DMAI DMA Input Enable Bit

The DMA feature is not implemented. Do not set this bit.

3r CO Command Out Bit 3w CO IE Command Out Interrupt Enable Bit

CO is set when:

(CACS & SGNS) becomes true

CO is cleared by:

(Read ISR2) + -(CACS) + -(SGNS)

Notes:

CACS: GPIB Controller Active State SGNS: GPIB Source Generate State Read ISR2: Bit is cleared immediately after it is read.

CO = 1 indicates CDOR is empty and that another command can be written to it for transmission to the GPIB without overwriting a previous command.

Bit Mnemonic Description

2w LOKC Lockout Change Bit 2r LOKC IE Lockout Change Interrupt Enable Bit

LOKC is set by:

any change in LOK

LOKC is cleared by:

pon + (Read ISR2)

Notes:

LOK: ISR2[5]r pon: power on reset Read ISR2: Bit is cleared immediately after it is read.

LOKC is set whenever there is a change in the LOK bit, ISR2[5]r, (REMS + RELS).

1w REMC Remote Change Bit 1r REMC IE Remote Change Interrupt Enable Bit

REMC is set by:

any change in REM

REMC is cleared by:

pon + (Read ISR2)

Notes:

REM: ISR2[4]r pon: power on reset Read ISR2: Bit is cleared immediately after it is read.

REMC is set whenever there is a change in the REM bit, ISR2[4]r, (REMS + RELS).

0r ADSC Addressed Status Change Bit 0w ADSC IE Addressed Status Change Interrupt Enable Bit

ADSC is set by:

[(any change in TA) + (any change in LA) + (any change in CIC) + (any change in MJMN)] & -(lon + ton)

ADSC is cleared by:

pon + (Read ISR2)

GPIB-1014P User Manual 4-18 © National Instruments Corporation

Section Four Register Bit Descriptions

Bit Mnemonic Description

Notes:

TA: Talker Active bit, ADSR[1]r LA: Listener Active bit, ADSR[2]r CIC: Controller In Charge bit,ADSR[7]r MJMN: Major/Minor bit, ADSR[0]r lon: Listen Only bit, ADMR[6]w ton: Talk Only bit, ADMR[7]w pon: power on reset Read ISR2: Bit is cleared immediately after it is read.

ADSC is set whenever there is a change in one of the four bits: TA, LA, CIC, MJMN of the Address Status Register (ADSR).

Serial Poll Status Register (SPSR)

VMEbus Address: Base Address + 7 (hex) Attributes: Read Only

Serial Poll Mode Register (SPMR)

VMEbus Address: Base Address + 7 (hex) Attributes: Write Only

7 654 3210

S8 S8

PEND

rsv

S6 S6

S5 S5

S4 S4

S3 S3

S2 S2

S1 S1

Bit Mnemonic Description

7r,7w S8 Serial Poll Status Byte 5-0r S6-S1

5-0w Cleared by Power On Reset (pon) and by issuing the Chip Reset

auxiliary command. These bits are used for sending device- or systemdependent status information over the GPIB when the TLC is serial polled. When the TLC is addressed as the GPIB Talker and receives the GPIB multiline Serial Poll Enable (SPE) command message, it transmits a byte of status information, SPMR[7-0], to the Controller-In-Charge after the Controller goes to Standby and becomes an active Listener.

6r PEND Pending Bit

PEND is set when rsv=1 and cleared when Negative Poll Response States (NPRS) & Request Service (rsv) = 1. Reading the PEND status bit can confirm that a request was accepted and that the Status Byte (STB) was transmitted (PEND=0).

6w rsv Request Service Bit

The rsv bit is used for generating the GPIB local request service message. When rsv is set and the GPIB Active Controller is not serially polling the TLC, the TLC enters the Service Request State (SRQS) and asserts the GPIB SRQ signal. When the Active Controller reads the STB during the poll, the TLC clears rsv at the Affirmative Poll Response State (APRS). The rsv bit is also cleared by power on reset, LMR (CFG2[1]w), and by issuing the Chip Reset auxiliary command.

GPIB-1014P User Manual 4-20 © National Instruments Corporation

Section Four Register Bit Descriptions

Address Status Register (ADSR)

VMEbus Address: Base Address + 9 (hex) Attributes: Read Only

756 43210

CIC ATN* SPMS

LPAS TPAS

MJMN

The ADSR contains information that can be used to monitor the TLC GPIB address status.

Bit Mnemonic Description

7r CIC Controller-In-Charge Bit

CIC = -(CIDS + CADS) CIC indicates that the TLC GPIB Controller function is in an active or

standby state, with ATN* on or off, respectively. The Controller function is in an idle state, with ATN* off, if CIC=0.

6r ATN* Attention* Bit

ATN* is a status bit which indicates the current level of the GPIB ATN* signal. If ATN* is 0, the GPIB ATN* signal is asserted.

5r SPMS Serial Poll Mode State Bit

If SPMS=1, the TLC GPIB Talker (T) or Talker Extended (TE) function is enabled to participate in a serial poll. SPMS is set when the TLC has been addressed as a GPIB Talker and the GPIB Active Controller has issued the GPIB Serial Poll Enable (SPE) command message. SPMS is cleared when the GPIB Serial Poll Disable (SPD) command is received, by power on reset, or by issuing the Chip Reset auxiliary command.

4r LPAS Listener Primary Addressed State Bit

The LPAS bit is used when the TLC is configured for extended GPIB addressing and, when set, indicates that the TLC has received its primary listen address. In Mode 3, addressing (see Address Mode Register Description), LPAS=1 indicates that the secondary address being received on the next GPIB command may represent the TLC Extended (Secondary) GPIB Listen address. LPAS is cleared by pon or by issuing the Chip Reset auxiliary command.

Bit Mnemonic Description

3r TPAS Talker Primary Addressed State Bit

TPAS is used when the TLC is configured for extended GPIB addressing, and, when set, indicates that the TLC has received its primary GPIB Talk address. In Mode 3 addressing extended mode, TPAS=1 indicates that the secondary address being received as the next GPIB command message may represent the TLC extended (secondary) GPIB Talk address.

2r LA Listener Active Bit

LA is set whenever the TLC has been addressed or programmed as a GPIB Listener; that is, the TLC is in the Listener Active State (LACS) or the Listener Addressed State (LADS). The TLC can be addressed to listen either by sending its own listen or extended listen address while it is Controller-In-Charge (CIC) or by receiving its listen address from an external CIC. It can also be programmed to listen using the lon bit in the Address Mode Register (ADMR).

If the TLC is addressed to Listen, it is automatically unaddressed to Talk. LA is cleared by pon or by issuing the Chip Reset auxiliary command.

1r TA Talker Active Bit

TA is set whenever the TLC has been addressed or programmed as the GPIB Talker; that is, the TLC is in the Talker Active State (TACS) the Talker Addressed State (TADS) or the Serial Poll Active State (SPAS). The TLC can be addressed to talk either by sending its own talk or extended talk address while it is CIC or by receiving its talk address from an external CIC. It can also be programmed to talk using the ton bit in the Address Mode Register (ADMR).

If the TLC is addressed to talk, it is automatically unaddressed to listen. TA is cleared by pon or by issuing the Chip Reset auxiliary command.

0r MJMN Major-Minor Bit

The MJMN bit is used to determine whether the information in the other ADSR bits applies to the TLC major or minor Talker/Listener function. MJMN is set to 1 when the TLC GPIB minor Talk address or minor Listen address is received. MJMN is cleared on receipt of the TLC major Talk or major Listen address.

Note: Only one Talker/Listener can be active at any one time. Thus, the

MJMN bit indicates which, if either, of the TLC Talker/Listener functions is addressed or active. MJMN is always zero unless a dual primary addressing mode (Mode 1 or Mode 3) is enabled (see Address Mode Register later in this section).

GPIB-1014P User Manual 4-22 © National Instruments Corporation

Section Four Register Bit Descriptions

Address Mode Register (ADMR)

VMEbus Address: Base Address + 9 (hex) Attributes: Write Only

7 654 321

ton 1on TRM1 TRM0 0 0 ADM1 ADM0

Bit Mnemonic Description

7w ton Talk Only Bit

Setting ton programs the TLC to be a GPIB Talker. If ton is set, the lon, ADM1, and ADM0 bits must be cleared. This method must be used in place of the addressing method when the TLC will be only a Talker.

Note: Clearing ton does not by itself take the TLC out of GPIB Talker

Active state (TACS). It is also necessary to execute the Chip Reset or Immediate Execute pon auxiliary command.

6w lon Listen Only Bit

Setting lon programs the TLC to be a GPIB Listener. If lon is set, ton, ADM1, and ADM0 should be cleared.

Note: Clearing lon does not by itself take the TLC out of Listener Active

state (LACS). It is also necessary to execute the Chip Reset or Immediate Execute pon auxiliary command.

5-4w TRM[1-0] Transmit/Receive Mode Bits 1 through 0

TRM1 and TRM0 control the function of the TLC T/R2 and T/R3 output pins in the following manner:

TRM1 TRM0 T/R2 T/R3

0 0 EOI OE TRIG 0 1 CIC TRIG 1 0 CIC EOI OE 1 1 CIC P E

Bit Mnemonic Description

Key EOI OE = GPIB EOI signal output enable

CIC = Controller-In-Charge TRIG = Trigger PE = Pull-up Enable

For proper operation, set both TRM1 and TRM0 (which selects T/R2 = CIC and T/R3 = PE).

3-2w 0 Reserved Bits

Write zeros to these bits.

1-0w ADM[1-0] Address Mode Bits 1 through 0

These bits state the addressing mode currently in effect–that is, the manner in which the information in ADR0 and ADR1 is interpreted (see Address Register 0 and Address Register 1 later in this section). If both bits are zero then the TLC does not respond to GPIB address commands. Instead, the ton and lon bits are used to program the Talker and Listener functions, respectively. The ton and lon bits must be cleared if mode 1, 2, or 3 addressing is selected, and the AMD[1-0] bits must be cleared if either of the bits ton or lon are set.

Mode ADM1 ADM0 Title

0 0 0 ton/lon 1 0 1 Normal dual addressing 2 1 0 Extended single addressing 3 1 1 Extended dual addressing

In mode 1 ADR0 and ADR1 contain the major and minor addresses, respectively, for dual primary GPIB address applications; that is, the TLC responds to two GPIB addresses: a major address and a minor address. The MJMN bit in the ADSR indicates which address was received. In applications where the TLC needs to respond to only one address, the major Talker and Listener function is used and the minor Talker and Listener function should be disabled. The minor Talker and Listener function can be disabled by setting the Disable Talker (DT) and Disable Listener (DL) bits in ADR1 (set ADR and ADR1).

In mode 2 (ADM1=1, ADM0=0), the TLC recognizes two sequential GPIB address bytes, a primary followed by a secondary. Both GPIB address bytes must be received in order to enable the TLC to talk or listen. In this manner, mode 2 addressing uses the Extended Talker and Extended Listener functions as defined in IEEE- 488, without requiring computer program intervention. In mode 2, ADR0 and ADR1 contain the TLC primary and secondary GPIB addresses, respectively.

GPIB-1014P User Manual 4-24 © National Instruments Corporation

Section Four Register Bit Descriptions

Bit Mnemonic Description

In mode 3 (ADM1=1, ADM0=1), the TLC handles addressing just as it does in mode 1, except that each major or minor GPIB primary address must be followed by a secondary address. All secondary GPIB

addresses must be verified by computer program when mode 3 is used. When the TLC is in Talker Primary Addressed State (TPAS) or Listener Primary Addressed State (LPAS) and a secondary address byte is on the GPIB DIO lines, the APT bit of ISR2 is set and the secondary GPIB address may be inspected in the CPTR. The TLC Acceptor Handshake is held up in the Accept Data State (ACDS) until the Valid or Non-Valid auxiliary command is written to the AUXMR, signaling a valid or invalid secondary address, respectively, to the TLC.

ADM0 and ADM1 must be cleared when either of the two programmable bits ton or lon is set.

Command Pass Through Register (CPTR)

VMEbus Address: Base Address + B (hex) Attributes: Read Only

7 654 3210

CPT7 CPT6 CPT5 CPT4 CPT3 CPT2 CPT1 CPT0

Bit Mnemonic Description

7-0r CPT[7-0] Command Pass Through Bits 7 through 0

These bits are used to transfer undefined multiline GPIB command messages from the GPIB DIO lines to the computer. When the CPT feature is enabled (CPT ENAB=1, AUXRB[0]w), any GPIB Primary Command Group (PCG) message not decoded by the TLC is treated as an undefined command. The multiline GPIB commands recognized by the µPD7210 are listed in Table 4-3. All GPIB Secondary Command Group (SCG) messages following an undefined GPIB PCG message are also treated as undefined. In such a case, when an undefined GPIB message is encountered, it is held in the CPTR and the TLC Acceptor Handshake function is held off (in ACDS) until the Valid auxiliary command is written to the AUXMR. The CPTR is also used to inspect secondary addresses when mode 3 addressing is used. The TLC Acceptor Handshake function is held off (in ACDS) until the Valid or Non-Valid auxiliary command is written to the AUXMR.

Table 4-3. Multiline GPIB Commands Recognized by the µPD7210

Hex Number Message Description

01 GTL Go To Local

04 SDC Selected Device Clear

05 PPC Parallel Poll Configure

08 GET Group Execute Trigger

(continues)

GPIB-1014P User Manual 4-26 © National Instruments Corporation

Section Four Register Bit Descriptions

Table 4-3. Multiline GPIB Commands Recognized by the µPD7210

(continued)

Hex Number Message Description

09 TCT Take Control

11 LLO Local Lockout

14 DCL Device Clear

15 PPU Parallel Poll Unconfigure

18 SPE Serial Poll Enable

19 SPD Serial Poll Disable

20-3E MLA My Listen Address

3F UNL Unlisten

40-5E MTA My Talk Address

5F UNT Untalk

60-6F MSA,PPE My Secondary Address or Parallel

Poll Enable

70-7E MSA,PPD My Secondary Address or Parallel

Poll Disable

The CPTR is read during a TLC-initiated Parallel Poll operation to fetch the Parallel Poll response. The PPR message is latched into the CPTR when CPPS is set, until CIDS is set, or until a command byte is sent over the GPIB.

Auxiliary Mode Register (AUXMR)

VMEbus Address: Base Address + B (hex) Attributes: Write Only,

Permits Access to Hidden Registers

7 654 321

CNT1 CNT0CNT2 COM4 COM3 COM2 COM1 COM0

The AUXMR is used to issue auxiliary commands. It is also used to program the five hidden registers:

• Auxiliary Register A (AUXRA)

• Auxiliary Register B (AUXRB)

• Parallel Poll Register (PPR)

• Auxiliary Register E (AUXRE)

• Internal Counter Register (ICR) Table 4-2 shows the control and command codes used.

Bit Mnemonic Description

7-5w CNT[2-0] Control Code Bits 2 through 0

These bits specify the control code (that is, the manner in which the information in bits COM[4-0] is to be used). If CNT[2-0] are all zero, then the special command selected by COM[4-0] is executed; otherwise, the hidden register selected by CNT[2-0] is loaded with the data from COM[4-0].

GPIB-1014P User Manual 4-28 © National Instruments Corporation

Section Four Register Bit Descriptions

Bit Mnemonic Description

4-0w COM[4-0] Command Code bits 4 through 0

These bits specify the command code of the special function if the control code is 000. Table 4-4 is a summary of the implemented special functions. Table 4-5 explains the details of each special function. If the control code is not 000, then these bits are written to one of the hidden registers (indicated by the control code in CNT[2-0]).

Table 4-4. Auxiliary Command Summary

Function Code* (COM4-COM0)

Hex

4 3 2 1 0 Code** Auxiliary Command

0 0 0 0 0 00 Immediate Execute pon

0 0 0 1 0 02 Chip Reset

0 0 0 1 1 03 Finish Handshake

0 0 1 0 0 04 Trigger

0 0 1 0 1 05 Retur n to Local

0 0 1 1 0 06 Send EOI

0 0 1 1 1 07 Non-Valid Secondary Command or Address

0 1 1 1 1 0F Valid Secondary Command or Address

0 0 0 0 1 01 Clear Paralle l Poll Flag 0 1 0 0 1 09 Set Paralle l Poll Flag

1 0 0 0 1 11 Take Control Asynchronously (Pulsed) 1 0 0 1 0 12 Take Control Synchronously 1 1 0 1 0 1A Take Control Synchronously on End

(continues)

Table 4-4. Auxiliary Command Summary (continued)

Function Code* (COM4-COM0)

Hex

4 3 2 1 0 Code** Auxiliary Command

1 0 0 0 0 10 Go To Standby

1 0 0 1 1 13 Listen 1 1 0 1 1 1B Listen in Continuous Mode 1 1 1 0 0 1C Local Unlisten

1 1 1 0 1 1D Execute Parallel Poll

1 1 1 1 0 1E Set IFC 1 0 1 1 0 16 Clear IFC

1 1 1 1 1 1F Set REN 1 0 1 1 1 17 Clear REN

1 0 1 0 0 14 Disable System Control

* CNT[2-0] set to 000 binary ** Represents all eight bits of the Auxiliary Mode Register

Section Four Register Descriptions

Table 4-5 shows the functions that are executed when the AUXMR Control Code (CNT[2-0]) is loaded with 000 (binary) and the Command Code (COM[4-0]) is loaded.

Table 4-5. Auxiliary Commands Detailed Description

Command Code (COM4-COM0) 4 3 2 1 0 Description

0 0 0 0 0 Immediate Execute Pon

This command generates a local pon message that places the following GPIB interface functions into these idle states:

AIDS Acceptor Idle State CIDS Controller Idle State LIDS Listener Idle State LOCS Local State LPIS Listener Primary Idle State NPRS Negative Poll Response State PPIS Parallel Poll Idle State PUCS Parallel Poll to Unaddressed to Configure State SIDS Source Idle State SIIS System Control Interface Clear Idle State SPIS Serial Poll Idle State SRIS System Control Remote Enable Idle State TIDS Talker Idle State TPIS Talker Primary Idle State

If the command is sent while a pon message is already active (by either an external reset pulse or the Chip Reset auxiliary command) the local pon message becomes false.

0 0 0 1 0 Chip Reset

The Chip Reset command resets the TLC in the same way as an external reset pulse. The System Controller bit is also cleared. The TLC is reset to the following conditions:

• The local pon message is set and the interface functions are placed in their idle states.

• All bits of the SPMR are cleared.

• The EOI bit is cleared.

• All bits of the AUXRA, AUXRB, and AUXRE are cleared.

• The Parallel Poll Flag and RSC local message are cleared.

• The contents of the ICR is set to eight (F3 set to 1; F2, F1, and F0 set to 0).

• The TRM0 bit and the TRM1 bit are cleared.

(continues)

Table 4-5. Auxiliary Commands: Detailed Description (continues)

Command Code (COM4-COM0) 4 3 2 1 0 Description

The interface functions are held in their idle states until released by an Immediate Execute pon command. Between these commands, the TLC writable bits may be programmed to their desired states.

0 0 0 1 1 Finish Handshake (FH)

The Finish Handshake command finishes a GPIB Handshake that was stopped because of a Holdoff on RFD or DAC.

0 0 1 0 0 Trigger

Note: Trigger cannot be used with the GPIB-1014P. The Trigger command generates a high pulse on the TRIG pin

(T/R3 pin when TRM1=0) of the TLC. The Trigger command performs the same function as if the DET (Device Trigger) bit (ISR1[5]r) were set. (The DET bit is not set by issuing the Trigger command.)

0 0 1 0 1 Return to Local (rtl) 0 1 1 0 1 Return to Local (rtl)

The two Return to Local commands implement the rtl message as defined by IEEE-488. When COM3 is zero, the message is generated in the form of a pulse. When COM3 is one, the rtl command is set in the standard manner.

0 0 1 1 0 Send EOI (SEOI)

The Send EOI command causes the GPIB End Or Identify (EOI) line to go true with the next byte transmitted. The EOI line is then cleared upon completion of the Handshake for that byte. The TLC recognizes the Send EOI command only if TA=1 (that is, the TLC is addressed as the GPIB Talker).

(continues)

Section Four Register Descriptions

Table 4-5. Auxiliary Commands: Detailed Description (continues)

Command Code (COM4-COM0) 4 3 2 1 0 Description

0 0 1 1 1 Non-Valid Secondary Command or Address

The Non-Valid command releases the GPIB DAC message held off by the Address Pass Through (APT). The TLC is permitted to operate as if an Other Secondary Address (OSA) message has been received.

0 1 1 1 1 Valid Secondary Command or Address

The Valid command releases the GPIB DAC message held off by APT and allows the TLC to function as if a My Secondary Address (MSA) message had been received. The DAC message is released at the time of Command Pass Through (CPT). DAC is also released if DCAS or DTAS is in Holdoff state.

0 0 0 0 1 Clear Parallel Poll Flag 0 1 0 0 1 Set Parallel Poll Flag

These commands set the Parallel Poll Flag to the value of COM3. The value of the Parallel Poll Flag is used as the local message ist when bit four of Auxiliary Register B is zero. The value of SRQS is used as the ist when ISS=1.

1 0 0 0 0 Go To Standby

The Go To Standby command sets the local message gts if the TLC is in Controller Active State (CACS) or when it enters CACS. When the TLC leaves CACS, gts is cleared.

1 0 0 0 1 Take Control Asynchronously

The Take Control Asynchronously command pulses the local message tca.

(continues)

Table 4-5 Auxiliary Commands: Detailed Description (continues)

Command Code (COM4-COM0) 4 3 2 1 0 Description

1 0 0 1 0 Take Control Synchronously

The Take Control Synchronously command sets the local message tcs. The local message tcs is effective only when the TLC is in Controller Standby State (CSBS) or Controller Synchronous Wait State (CSWS). The local message tcs is cleared when the TLC enters Controller Active State (CACS).

1 1 0 1 0 Take Control Synchronously on END

The Take Control Synchronously on END command sets the local message tcs when the data block transfer End message (END bit equal to one) is generated at CSBS. The tcs message is cleared when the TLC enters CACS.

1 0 0 1 1 Listen

The listen command generates the local message ltn in the form of a pulse.

1 1 0 1 1 Listen in Continuous Mode

The Listen in Continuous Mode command generates the local message ltn in the form of a pulse and places the TLC in continuous mode.

In continuous mode, the local message rdy is issued when the Acceptor Not Ready State (ANRS) is initiated unless data block transfer end is detected (END RX bit equals one). When END is detected, the TLC is placed in the RFD Holdoff state, preventing generation of the rdy message. In continuous mode, the DI bit is not set when a data byte is received. The continuous mode caused by the Listen in Continuous Mode command is released when the Listen auxiliary command is issued or the TLC enters the Listener Idle State (LIDS).

1 1 1 0 0 Local Unlisten

The Local Unlisten command generates the local message lun in the form of a pulse.

(continues)

Section Four Register Descriptions

Table 4-5 Auxiliary Commands: Detailed Description (continued)

Command Code (COM4-COM0) 4 3 2 1 0 Description

1 1 1 0 1 Execute Parallel Poll

The Execute Parallel Poll command sets the local message Request Parallel Poll (rpp). The rpp message is cleared when the TLC enters either Controller Parallel Poll State (CPPS) or Controller Idle State (CIDS). The transition of the TLC interface function is not guaranteed if the local messages rpp and Go To Standby (gts) are issued simultaneously when the TLC is in Controller Active State (CACS) and Source Transfer State (STRS) or Source Delay State (SDYS).

1 1 1 1 0 Set IFC 1 0 1 1 0 Clear IFC

These commands generate the local message request system control (rsc) and set Interface Clear (IFC) to the value of COM3. These commands should only be issued if the GPIB-1014P is the System

Controller (SC). In order to meet the IEEE-488 requirements, you must not issue

the Clear IFC command until IFC has been held true for at least 100 µsec.

1 1 1 1 1 Set REN 1 0 1 1 1 Clear REN

These commands generate the local message rsc and set REN to the value in COM3. These commands should only be issued if the GPIB-1014P is the System Controller (SC). In order to meet IEEE-488 requirements, you must not issue the Set REN command until REN has been held false for at least 100 µsec.

1 0 1 0 0 Disable System Control

The Disable System Control command clears the local message rsc.

Hidden Registers

The hidden registers are loaded through the Auxiliary Mode Register (AUXMR). AUXMR[7-5] is loaded with the hidden register number, and AUXMR[4-0] is loaded with the data to be transferred to the hidden register. The hidden registers cannot be read, and in some cases the contents can only be set; that is, they can be cleared or reset to initialized conditions only by issuing the Chip Reset auxiliary command, or by a pon. Figure 4-2, earlier in this section, shows the five hidden registers and illustrates how they are loaded with data from the AUXMR.

Internal Counter Register (ICR)

VMEbus Address: Base Address + B (hex) AUXMR Control Code: 001 (Binary, Bits 7 - 5) Attributes: Write Only,

Accessed through AUXMR

4321 0

0 CLK3 CLK2 CLK1 CLK0

Bit Mnemonic Description

4w 0 Reserved Bit

Write zero to this bit.

3-0w CLK[3-0] Clock Bits 3 though 0

The contents of the ICR are used to divide internal counters that generate TLC state change delay times used by the IEEE-488 specification. The most familiar of these times, T1, is the minimum delay between placing the data or command bytes on the GPIB DIO lines and asserting DAV. These delay times vary depending on the type of transfer in progress and the value of the AUXRB bit TRI.

For proper operation, ICR should be set to eight because the TLC is clocked at 8 MHz.

Section Four Register Descriptions

Parallel Poll Register (PPR)

VMEbus Address: Base Address + B (hex) AUXMR Control Code: 011 (Binary, Bits 7 - 5) Attributes: Write Only,

Accessed through AUXMR

4321 0

U S P3 P2 P1

Writing to the Parallel Poll Register is done via the AUXMR. Writing the binary value 011 into the Control Code (CNT[2-0]) and a bit pattern into the command code portion (COM[4-0]) of the AUXMR causes the command code to be written to the Parallel Poll Register (PPR). When COM[4-0] is written to the PPR, the bits are named as shown above. This 5-bit command code determines the manner in which the TLC responds to a Parallel Poll.

When using the remote Parallel Poll Configure (IEEE-488 capability code PP1), do not write to the PPR. The TLC implements remote configuration fully and automatically without software assistance. The hardware recognizes, interprets, and responds to Parallel Poll Configure (PPC), Parallel Poll Enable (PPE), Parallel Poll Disable (PPD), and Identify (IDY) messages. The user need only set or clear the individual status (ist) message (using Set/Clear Parallel Poll Flag auxiliary commands) according to pre-established system protocol convention. Writing to the PPR after it is remotely configured will corrupt the configuration.

When using the local PPC (capability code PP2), a valid PPE or PPD message should be written to the PPR in advance of the poll.

Bit Mnemonic Description

4w U Parallel Poll Unconfigure Bit

The U bit determines whether or not the TLC participates in a Parallel Poll. If U=0, the TLC participates in Parallel Polls and responds in the manner defined by PPR[3] through PPR[0] and by ist. If U=1, the TLC does not participate in a Parallel Poll.

The U bit is equivalent to the local message lpe* (local poll enable, active low). When U=0, S and P3-1 mean the same as the bit of the same name in the PPE message, and the I/O write operation (to the PPR) is the same as the receipt of the PPE message from the GPIB Controller. When U=1, S and P3-1 do not carry any meaning, but they must be cleared.

Bit Mnemonic Description

3w S Status Bit Polarity Bit

The S bit is used to indicate the polarity of the TLC local ist (individual status) message. If S=1, the status is in phase, meaning that if, during a Parallel Poll response, S=ist=1 and U=0, the TLC responds to the Parallel Poll by driving one of the eight GPIB DIO lines low, thus asserting it to a logic one. If S=1 and ist=0, the TLC does not drive the DIO line.

If S=0, the status is in reverse phase, meaning that if, during a Parallel Poll, ist=0, and U is 0, the TLC responds to the Parallel Poll by driving one of the eight GPIB DIO lines low. If S=0 and ist=1, the TLC does not drive the DIO line.

Refer to the description of AUXRB and the Set/Clear auxiliary commands for more information.

3w P[3-1] Parallel Poll Response Bits 3 through 1

PPR bits 3 through 1, designated P[3-1], contain an encoded version of the Parallel Poll Response. P[3-1] indicate which of the eight DIO lines is asserted during a Parallel Poll (equal to N-1). The GPIB-1014P normally drives the GPIB DIO lines using three-state drivers. During Parallel Poll responses, however, the drivers automatically convert to Open Collector mode, as required by IEEE-488. For example, if P[31]=010 (binary), GPIB DIO line DIO3* is driven low (asserted) if the GPIB-1014P is parallel polled (and S=ist).

Some examples of configuring the Parallel Poll Register are as follows:

Written to the AUXMR

7 6 5 4 3 2 1 0 Result 01110000 Unconfigures PPR 01100000 0 0 0 0 0 is written to the PPR. GPIB-1014P participates in a

Parallel Poll, asserting the DIO1 line if ist is 0. Otherwise, the GPIB-1014P does not participate.

01101001 0 1 0 0 1 is written to the PPR. GPIB-1014P participates in a

Parallel Poll, asserting the DIO2 line if ist is 1. Otherwise, the GPIB-1014P does not participate.

Section Four Register Descriptions

Auxiliary Register A (AUXRA)

VMEbus Address: Base Address + B (hex) AUXMR Control Code: 100 (Binary, Bits 7 - 5) Attributes: Write Only,

Accessed through AUXMR

4321 0

BIN

XEOS

REOS HLDE HLDA

Writing to Auxiliary Register A (AUXRA) is done via the AUXMR. Writing the binary value 100 into the Control Code (CNT[2-0]) and a bit pattern into the Command Code portion (COM[4-0]) of the AUXMR causes the Command Code to be written to AUXRA. When the data is written to AUXRA, the bits are denoted by the mnemonics shown above. This 5-bit code controls the data transfer messages Holdoff and EOS/END.

Bit Mnemonic Description

4w BIN Binary Bit

The BIN bit selects the length of the EOS message. Setting BIN causes the End of String Register (EOSR) to be treated as a full 8-bit byte. When BIN=0, the EOSR is treated as a 7-bit register (for ASCII characters) and only a 7-bit comparison is done with the data on the GPIB.

3w XEOS Transmit END with EOS Bit

The XEOS bit permits or prohibits automatic transmission of the GPIB END message at the same time as the EOS message when the TLC is in Talker Active State (TACS). If XEOS is set and the byte in the CDOR matches the contents of the EOSR, the EOI line is sent true along with the data.

2w REOS END on EOS Received Bit

The REOS bit permits or prohibits setting the END bit (ISR1[4]r) at reception of the EOS message when the TLC is in Listener Active State (LACS). If REOS is set and the byte in the DIR matches the byte in the EOSR, the END bit (ISR1[4]r) is set.

Bit Mnemonic Description

1-0w HLDE Holdoff on END Bit

HLDA Holdoff on All Bit

HLDE and HLDA together determine the GPIB data receiving mode. The four possible modes are as follows:

HLDE HLDA Data Receiving Mode

0 0 Normal handshake 0 1 RFD holdoff on All Data 1 0 RFD holdoff on END 1 1 Continuous

In Normal Handshake mode, the local message rdy is generated when data is received from the GPIB. When the received data is read from the DIR, rdy is generated in Acceptor Not Ready State (ANRS), the RFD message is transmitted, and the GPIB handshake continues.

In RFD Holdoff on All Data (HLDA) mode, RFD is not sent true after data is received until the Finish Handshake (FH) auxiliary command is issued. Unlike Normal Handshake mode, the RFD HLDA mode does not generate the rdy message even if the received data is read through the DIR; that is, the GPIB RFD message is not generated.

In RFD Holdoff on End mode, operation is the same as the RFD HLDA, but only when the end of the data block (EOS or END message) is detected; that is, the END message is received or, if REOS is set, the EOS character received. Handshake holdoff is released by the FH auxiliary command.

In continuous mode, the rdy message is generated when in ANRS until the end of the data block is detected. A Holdoff is generated at the end of a data block. The FH auxiliary command must be issued to release the Holdoff. The continuous mode is useful for monitoring the data block transfer without actually participating in the transfer (no data reception). In continuous mode, the DI bit (ISR1[0]r) is not set by the reception of a data byte.

Section Four Register Descriptions

Auxiliary Register B (AUXRB)

VMEbus Address: Base Address + B (hex) AUXMR Control Code: 101 (Binary, Bits 7 - 5) Attributes: Write Only,

Accessed through AUXMR

4321 0

ISS

INV

TRI SPEOI

CPT

ENABLE

Writing to Auxiliary Register B (AUXRB) is done via the AUXMR. Writing the value 101 into the Control Code (CNT[2-0]) and a bit pattern into the Command Code portion (COM[4-0]) of the AUXMR causes the Command Code to be written to AUXRB. When the data is written to AUXRB, the bits are denoted as shown in the register bit map above. This 5-bit code affects several interface functions, as described in the following paragraphs.

Bit Mnemonic Description

4w ISS Individual Status Select Bit

The ISS bit determines the value of the TLC ist message. When ISS=1, ist becomes the same value as the TLC Service Request State (SRQS). (The TLC is asserting the GPIB SRQ message when it is in SRQS.) When ISS=0, ist takes on the value of the TLC Parallel Poll Flag. The Parallel Poll Flag is set and cleared using the Set Parallel Poll Flag and Clear Parallel Poll Flag auxiliary commands.

3w INV Invert Bit

The INV bit affects the polarity of the TLC INT pin. Setting INV causes the polarity of the Interrupt (INT) pin on the TLC to be active low. As implemented on the GPIB-1014P, configuring the INT pin to active low results in interrupt request errors. Consequently, INV should always be clear and should never be set.

INV = 0 : INT pin is active high INV = 1 : INT pin is active low

2w TRI Three-State Timing Bit

The TRI bit determines the TLC GPIB Source Handshake Timing, T1, as defined in the IEEE-488 specifications. TRI can be set to enable highspeed data transfers when three-state GPIB drivers are used. (The GPIB1014P uses three-state GPIB drivers except during Parallel Poll responses, in which case the GPIB drivers automatically switch to Open

Bit Mnemonic Description

Collector.) Setting TRI enables timing during the GPIB Source Handshake function after transmission of the first byte. Clearing TRI sets the T1 timing to low speed in all cases.

1w SPEOI Send Serial Poll EOI Bit

The SPEOI bit permits or prohibits the transmission of the END message in Serial Poll Active State (SPAS). If SPEOI is set, EOI is sent true when the TLC is in SPAS; otherwise, EOI is sent false in SPAS.

0w CPT ENABLE Command Pass Through Enable Bit

The CPT ENABLE bit permits or prohibits the detection of undefined GPIB commands and permits or prohibits the setting of the CPT bit (ISR1[7]r) on receipt of an undefined command. When CPT ENAB is set and an undefined command has been received, the DAC message is held and the Handshake stops until the Valid auxiliary command is issued. The undefined command can be read from the CPTR and processed by the software.

Section Four Register Descriptions

Auxiliary Register E (AUXRE)

VMEbus Address: Base Address + B (hex) AUXMR Control Code: 110 (Binary, Bits 7 - 5) Attributes: Write Only,

Accessed through AUXMR

4321 0

0 DHDC DHDT

Writing to Auxiliary Register E (AUXRE) is done via the AUXMR. Writing the binary value 110 into the Control Code (CNT[2-0]) and a bit pattern into the lower five bits (COM[4-0]) of the AUXMR causes the two lowest order bits to be written to AUXRE. The 2-bit code, DHDC and DHDT, determines how the TLC uses DAC Holdoff.

Bit Mnemonic Description

4-2w 0 Reserved Bits

Write zeros to these bits.

1w DHDC DAC Holdoff on DCAS Bit

Setting DHDC enables DAC holdoff when the TLC enters Device Clear Active State (DCAS). Clearing DHDC disables DAC Holdoff on DCAS. Issuing the Finish Handshake auxiliary command releases the Holdoff.

0w DHDT DAC Holdoff on DTAS Bit

Setting DHDT enables DAC holdoff when the TLC enters Device Trigger Active State (DTAS). Clearing DHDT disables DAC Holdoff on DTAS. Issuing the Finish Handshake auxiliary command releases the Holdoff.

Address Register 0 (ADR0)

VMEbus Address: Base Address + D (hex) Attributes: Read Only

76543210

X DT0 DL0 AD5-0 AD4-0 AD3-0 AD2-0 AD1-0

ADR0 reflects the internal GPIB address status of the TLC as configured using the ADMR. In addressing Mode 2, ADR0 indicates the address and enable bits for the primary GPIB address of the TLC. In dual primary addressing (Modes 1 and 3) ADR0 indicates the TLC major primary GPIB address. (Refer to description of ADMR for information on addressing modes).

Bit Mnemonic Description

7r X Don't Care Bit

Reads as a zero or one.

6r DT0 Disable Talker 0

If DT0 is set it indicates that the mode 2 primary (or mode 1 and 3 major) Talker is not enabled; that is, the TLC does not respond to a GPIB talk address matching AD[5-0–1-0]. If DT0=0, the TLC responds to a GPIB talk address matching bits AD[5-0–1-0].

5r DL0 Disable Listener 0 Bit

If DL0 is set, it indicates that the mode 2 primary (or mode 1 and 3 major) Listener is not enabled; that is, the TLC does not respond to a GPIB Listen address matching bits AD[5-0–1-0]. If DL0=0, the TLC responds to a GPIB listen address matching bits AD[5-0–1-0].

4-0r AD5-0 Mode 2 Primary GPIB Address Bits 5-0 through 1-0

through AD1-0 These are the lower five bits of the TLC GPIB primary (or major)

address. (The primary talk address is formed by adding octal 100 to AD5-0 through AD1-0, while the listen address is formed by adding octal 40.)

Section Four Register Descriptions

Address Register (ADR)

VMEbus I/O Address: Base Address + D (hex) Attributes: Write Only, Internal to TLC

76543210

ARS DT DL AD5 AD4 AD3

AD2 AD1

The Address Register (ADR) is used to load the internal registers ADR0 and ADR1. Both ADR0 and ADR1 must be loaded for all addressing modes.

Bit Mnemonic Description

7w ARS Address Register Select Bit

ARS is 0 or 1 to select whether the seven lower-order bits of ADR must be loaded into internal registers ADR0 or ADR1, respectively.

6w DT Disable Talker Bit

DT must be set if recognition of the GPIB talk address formed from AD5 through AD1 (ADR[4-0]w) is not to be enabled.

5w DL Disable Listener Bit

DL must be set if recognition of the GPIB Listen address formed from AD[5-1] is not to be enabled.

4-0w AD5-1 Address Bit

These bits specify the five low-order bits of the GPIB address that is to be recognized by the TLC. (The corresponding GPIB Talk address is formed by adding octal 100 to AD[5-1], while the corresponding GPIB listen address is formed by adding octal 40.) The value written to AD[51] must not be all ones; otherwise, the corresponding talk and listen addresses would conflict with the GPIB Untalk (UNT) and Unlisten (UNL) commands.

Address Register 1 (ADR1)

VMEbus Address: Base Address + F (hex) Attributes: Read Only

76543210

EOI

DT1 DL1 AD5-1 AD4-1 AD3-1 AD2-1

AD1-1

Address Register 1 (ADR1) indicates the status of the GPIB address and enable bits for the secondary address of the TLC if mode 2 addressing is used, or the minor primary address of the TLC if dual-primary addressing is used (modes 1 and 3). If mode 1 addressing is used and only a single-primary address is needed, both the talk and listen addresses disable in this register. If mode 2 addressing is used, the talk and listen disable bits in this register must match those in ADR0.

Bit Mnemonic Description

7r EOI End or Identify Bit

EOI indicates the value of the GPIB EOI line latched when a data byte is received by the TLC GPIB Acceptor Handshake (AH) function. If EOI=1, the EOI line was asserted with the received byte. EOI is cleared by pon or by using the Chip Reset auxiliary command.

6r DT1 Disable Talker 1 Bit

If DT1 is set, the mode 2 secondary (or mode 1 and 3 minor.) Talker is not enabled; that is, the TLC does not respond to a secondary address (or minor primary talk address) formed from bits AD5-1 to AD1-1. If DT1 is cleared (DT1 = 0) and the TLC received its primary talk address (that is, is in TPAS), the secondary address is checked.

5r DL1 Disable Listener 1 Bit

If DL1=1, the mode 2 secondary (or mode 1 and 3 minor) listen function is not enabled; that is, the TLC cannot be addressed to listen at the address specified by AD5-1 through AD1-1. If DL1 is cleared (DL1 = 0) and the TLC received its primary listen address (that is, is in LPAS), the secondary address is checked.

4-0r AD[5-1 – 1-1] Mode 2 Secondary TLC GPIB Address Bits 5-1 through 1-1

These are the lower five bits of the TLC secondary or minor address. The secondary address is formed by adding hex A0 to bits AD[5-1 – 1-1]. The minor talk address is formed by adding hex 40 to AD[5-1 – 11], while the listen address is formed by adding a hex 20.

Section Four Register Descriptions

End Of String Register (EOSR)

VMEbus Address: Base Address + F (hex) Attributes: Write Only

7 654 3210

EOS7

EOS6 EOS5 EOS4 EOS3 EOS2 EOS1 EOS0

The End of String Register (EOSR) holds the byte used by the TLC to detect the end of a GPIB data block transfer. A 7- or 8-bit byte (ASCII or binary) can be placed in the EOSR to be used in detecting the end of a block of data. The length of the EOS byte to be used in the comparison is selected by the BIN bit in AUXRA (AUXRA[4]w).

If the TLC is a Listener and bit REOS of AUXRA is set, the END bit is set in ISR1 whenever the byte in the DIR matches the EOSR. If the TLC is a Talker and the data is being transmitted, and XEOS bit of AUXRA is set, the END message (GPIB EOI* line asserted low) is sent along with the data byte whenever the contents of the CDOR matches the EOSR.

Bit Mnemonic Description

7-0w EOS7- End of String Bits 7 through 0

EOS0

Section Five Programming Considerations

This section explains important considerations for programming the GPIB-1014P.

Initialization

On power-up (pon), the VMEbus system typically issues a system reset (SYSRESET*) that drives the GPIB-1014P RESET* signal active and initializes the following circuitry:

• Timing State Machine

• Interrupter

• µPD7210 TLC The NEC µPD7210 Talker/Listener/Controller (TLC) integrated circuit is initialized as follows:

• The local message pon is set and the interface functions are placed in their idle states (SIDS, AIDS, TIDS, SPIS, TPIS, LIDS, LPIS, NPRS, LOCS, PPIS, PUCS, CIDS, SRIS, SIIS).

• All bits of the Serial Poll Mode Register (SPMR) are cleared.

• End Or Identify (EOI) bit is cleared.

• All bits of the Auxiliary Registers A, B, and E (AUXRA, AUXRB, and AUXRE) are cleared.

• The Parallel Poll Flag and Request System Control (RSC) local message are cleared.

• The Internal Clock Register (ICR) is set to a count of eight.

• The Transmit Receive Mode 0 (TRM0) and Transmit Receive Mode 1 (TRM1) bits in the Address Mode Register (ADMR) are cleared.

All other TLC register contents should be considered as undefined while the RESET* is asserted and after RESET* has been cleared. All Auxiliary Mode Register (AUXMR) commands are cleared and cannot be executed. All other TLC registers can be programmed while the TLC internal signal pon is set. When pon is released or cleared (by issuing an Immediate Execute pon auxiliary command to the TLC), the interface functions are released from the pon state and the auxiliary commands can be executed.

Programming Considerations Section Five

A typical programmed initialization sequence for the GPIB-1014P might include the following steps:

1.Set pon by issuing the Chip Reset auxiliary command to place the GPIB-1014P in a known,

quiescent state.

2.Set or clear the desired interrupt enable bits in Interrupt Mask Register 1 (IMR1) and Interrupt

Mask Register 2 (IMR2) of the TLC.

3.Load the TLC primary GPIB address in Address Register 0 (ADR0) and Address Register 1

(ADR1).

4.Enable or disable the GPIB Talker and Listener functions and addressing mode using the ADMR.

5.Load the Serial Poll response in the SPMR.

6.Load the Parallel Poll response in the Parallel Poll Register (PPR) if local configuration is used. If

using remote configuration, clear the PPR.

7.Clear power on (pon) by issuing the Immediate Execute pon auxiliary command to the TLC to

bring TLC on-line.

8.Execute the desired TLC auxiliary commands.

The GPIB-1014P as GPIB Controller

The GPIB-1014P Controller function is generally in one of two modes: idle or in charge. When in charge, the Controller function is either active (asserting ATN) or standby (not asserting ATN). The following paragraphs discuss the various transitions between these two modes.

Becoming Controller-In-Charge (CIC) and Active Controller

The TLC can become CIC either by being the System Controller and taking control (by issuing the Set IFC auxiliary command) or by being passed control of the GPIB from the current Active Controller.

To take control, issue the Set IFC auxiliary command, wait for a minimum of 100 µsec, and then issue the Clear IFC auxiliary command. The ensuing GPIB IFC message initializes the GPIB interface functions of all devices on the bus. As soon as any existing CIC goes to idle (dropping ATN if it was active) the TLC becomes CIC and Active Controller and asserts the GPIB ATN line.

In addition to asserting IFC, the Set IFC auxiliary command also causes the GPIB transceivers for IFC* and REN* to be configured as GPIB line drivers, thus allowing the IFC and REN lines from the GPIB-1014P to be driven to the GPIB. The transceivers remain configured as drivers until a system reset is received or the Disable System control auxiliary command is issued, which causes the transceivers to be reconfigured as receivers. If the GPIB-1014P is not the System Controller, the initialization sequence should include issuing the Disable System Control auxiliary command to ensure that the transceivers are configured as receivers.

Section Five Programming Considerations

Another Active Controller passes control to the GPIB-1014P by sending the TLC GPIB talk address (MTA) followed by the GPIB Take Control (TCT) message. The TLC, upon receiving these two messages (MTA and TCT), automatically becomes CIC when ATN is dropped. The exact sequence of events is as follows:

1. The TLC receives the My Talk Address (MTA). The TLC then enters into Talker Addressed State (TADS). This operation can be transparent to a program. The Talker Active (TA) bit in the Address Status Register (ADSR) is set when the TLC receives its GPIB talk address.

2. The TLC receives the GPIB TCT message. Note: Normally, a program does not have to read or respond to the TCT command message,

but it can read the TCT message in the Command Pass Through Register (CPTR) in response to the assertion of the CPT status bit in Interrupt Status Register 1 (ISR1), assuming that the CPT ENABLE bit of AUXRB has been previously set.

3. The current Active Controller sees the completed handshake, goes to idle, and unasserts ATN.

4. As soon as the ATN line on the GPIB is unasserted, the TLC automatically becomes CIC and asserts ATN.

As soon as the TLC becomes CIC, the CIC bit in the ADSR, and the Command Output (CO) bit in Interrupt Status Register 2 (ISR2) are set. Using these two bits, the program can unambiguously determine that the TLC is the GPIB Active Controller and can send remote messages.

Sending Remote Multiline Messages (Commands)

The GPIB-1014P sends commands as Active Controller simply by writing to the Command/Data Out Register (CDOR) in response to the CO status bit in ISR2.

The TLC recognizes any commands applicable to itself, such as its own talk or listen address. To make the TLC a Listener, write its listen address to the CDOR.

Going from Active to Standby Controller

If the TLC is GPIB Active Controller, the Controller Standby State (CSBS) is entered upon reception of the Go To Standby auxiliary command. The ATN line is unasserted as soon as the TLC enters CSBS. Even though the TLC GPIB Controller state machine is in standby, the CIC bit in the ADSR is still set. Do not issue the Go To Standby auxiliary command unless the CO bit in ISR2 is set.

There are three cases to consider when going to standby: Case 1: The TLC becomes the GPIB Talker when ATN is unasserted. To do this, wait for CO to

be set, send the TLC GPIB Talk Address (MTA), wait for CO to be set again, and then issue the Go To Standby auxiliary command.

Programming Considerations Section Five

Case 2: The TLC becomes a GPIB Listener when ATN is unasserted. To do this, wait for CO to

be set, issue the TLC GPIB Listen Address (MLA), wait for CO to be set again, and then issue the Go To Standby auxiliary command.

Case 3. The TLC is neither GPIB Talker nor Listener. In this case, issue the listen in continuous

mode auxiliary command or set the Holdoff on End (HLDE) and Holdoff on All (HLDA) bits in AUXRA before going to standby. This puts the TLC in the continuous mode. Once this mode is enabled, the TLC participates in the GPIB handshake without setting the Data In (DI) bit. Then issue gts. When Holdoff occurs, the TLC can take control synchronously. This means that the Talker must finish its transmission with the END or EOS message. It can then take control synchronously when necessary.

Note: The Take Control Synchronously on End (tcse) auxiliary command can be

issued after gts, thereby causing the TLC to automatically take control synchronously on holdoff.

Going from Standby to Active Controller

The manner in which the TLC resumes GPIB Active Control depends on how it went to standby. Consider the three cases:

Case 1: The TLC, as a Talker, takes control upon receipt of the Take Control Asynchronously

auxiliary command. Do not issue the Take Control Asynchronously auxiliary command until there are no more bytes to send and the DO bit is set).

Case 2: The TLC, as a Listener, takes control upon receipt of the Take Control Synchronously

auxiliary command. If programmed I/O is used, the Take Control Synchronously auxiliary command should be issued between seeing a DI status bit and reading the last byte from the DIR.

Case 3: The TLC, as neither Talker nor Listener, takes control synchronously with the Take

Control Synchronously auxiliary command after detecting the END RX bit set in ISR1. This indicates that a holdoff is in progress

When the Take Control Synchronously auxiliary command is used, the TLC takes control of the GPIB only at the end of a data transfer. This implies that one transfer must follow or be in progress when the Take Control Synchronously auxiliary command is issued. If this is not the case, the Take Control Asynchronously auxiliary command must be used. Of course, the Take Control Asynchronously auxiliary command may be used in place of the Take Control Synchronously auxiliary command when the possibility of disrupting an in-progress GPIB handshake (before all GPIB Listeners have accepted the data byte) is acceptable.

In Cases 2 and 3, the END IE bit in IMR1 can also be set to indicate to the program that the TLC (functioning as a GPIB Listener) has received its last byte.

In all cases, a CO status indicates that the GPIB-1014P is now Active Controller.

Section Five Programming Considerations

Going from Active to Idle Controller

Going from Active to Idle GPIB Controller, also known as passing control, requires that the TLC be the Active Controller initially (in order to send the necessary GPIB command messages). After the TLC has become the GPIB Active Controller, it must complete the following procedures to pass control:

1. Write the GPIB Talk address of the device being passed control to the CDOR.

2. In response to the next CO status, write the GPIB TCT message to the CDOR.

3. As soon as the TCT command message is accepted by all devices on the GPIB, the TLC automatically unasserts ATN and the new Controller asserts ATN.

The GPIB-1014P as GPIB Talker and Listener

The TLC can be either GPIB Talker or Listener, but not both simultaneously. Either function is deactivated automatically if the other is activated. The TA, LA, and ATN* bits in the ADSR together indicate the specific state of the TLC:

ATN* TA LA

0 1 0 Addressed Talker–cannot send data

1 1 0 Active Talker–can send data 0 0 1 Addressed Listener–cannot receive data 1 0 1 Active Listener–can receive data

The status bits Address Status Change (ADSC), Command Output (CO), Address Pass Through (APT), Data Out (DO), and Data In (DI) are used to prompt the program (possibly with an interrupt request) when a change of state occurs.

The following paragraphs discuss several aspects of data transfers.

Programmed Implementation of Talker and Listener

When there is no Controller in the GPIB system, the ton and lon address modes (refer to the description of the ADMR) are used to activate the TLC GPIB Talker and Listener functions. If used, ton or lon should be set during TLC initialization.

When the TLC is GPIB Active Controller, the Listen and Local Unlisten programmed auxiliary commands are used to activate and de-activate the TLC GPIB Listener function.

Addressed Implementation of the Talker and Listener

The TLC, when GPIB Active Controller, can address itself by sending its own GPIB Talk or Listen address using the CO bit and the CDOR. When another device on the GPIB is acting as Controller, the TLC is addressed with GPIB command messages to become a Talker or Listener.

Programming Considerations Section Five

Address Mode 1

If the TLC ADMR has been configured for Address Mode 1, the TLC responds to the reception of two primary GPIB addresses: major and minor. Upon receipt of its major or minor MTA or its major or minor MLA from the GPIB Active Controller, the TLC is addressed as Talker or Listener. If the TLC has received its GPIB Talk Address, the TA bit in the ADSR is set, the ADSC bit in ISR2 is set, and the DO bit in ISR1 is set. If the TLC has received its GPIB Listen address, the LA bit in the ADSR is set, the ADSC bit in ISR2 is set, and the DI bit in ISR1 is set when the first GPIB data byte is received.

Address Mode 2

Address Mode 2 is used when Talker Extended (TE) or Listener Extended (LE) functions are to be used. TE and LE functions require receipt of two addresses (primary and secondary) before setting TA or LA. The TLC GPIB primary address is specified by the byte written to ADR0. The secondary address is specified by the byte written to ADR1. Upon receipt of both the primary and secondary GPIB addresses the TLC becomes an addressed Talker or Listener. If the TLC has received its primary GPIB talk address, the Talker Primary Addressed State (TPAS) bit in the ADSR is set. If the TLC receives its secondary GPIB talk address before receiving another GPIB Primary Command Group (PCG) message that is not its MTA, the TA bit in the ADSR, the ADSC bit in the ISR2, and the DO bit in the ISR1 are set. If the MC-GPIB has received its primary GPIB listen address, the Listener Primary Addressed State (LPAS) bit in the ADSR is set. If the TLC receives its secondary GPIB listen address before receiving another GPIB Primary Command Group (PCG) message that is not its MLA, the LA bit in the ADSR is set, the ADSC bit in ISR2 is set, and the DI bit in ISR1 is set when the first GPIB data byte is received. The Major-Minor (MJMN) bit in the ADSR indicates whether the address status refers to the major or minor address.

Address Mode 3

Address Mode 3, like Address Mode 2, is used to implement Extended GPIB Talk and Listen address recognition. However, unlike Address Mode 2, Address Mode 3 provides for both major and minor primary addresses, and your program must identify the secondary address by reading the CPTR. Proper operation using Address Mode 3 is listed as follows:

1. During initialization of the TLC, enable Address Mode 3 (and optionally set the APT IE bit in IMR1 to enable an interrupt request on receipt of a secondary GPIB address). Write the TLC major GPIB primary address to ADR0 and the TLC minor GPIB primary address to ADR1.

2. Receipt of the TLC major or minor primary GPIB Talk Address (MTA) or major or minor primary GPIB Listen Address (MLA) sets TPAS or LPAS, indicating that the primary address has been received.

3. If the next GPIB command following the primary address is a secondary address, the APT bit is set and a DAC handshake holdoff is activated (the GPIB DAC message is held false).

4. In response to APT, the program must:

• Determine whether the command just received is a listen, talk, major, or minor address by

reading the LPAS, TPAS, and MJMN bits of the ADSR.

• Read the secondary address in the CPTR and determine whether or not it is the address of

the TLC.

Section Five Programming Considerations

5. If it is not the TLC address, issue the Non-Valid auxiliary command. If it is the TLC address, issue the Valid auxiliary command.

6. When the Valid auxiliary command is issued, the TLC assumes that the My Secondary Address (MSA) message has been received, which causes:

• The LA bit to be set and the TA bit to be cleared (LADS=TIDS=1) if LPAS was set, or the

TA bit to be set and the LA bit to be cleared (TADS=LIDS=1) if TPAS was set.

• The GPIB DAC message to be sent true, and the GPIB handshake to be finished.

7. When the Non-Valid auxiliary command is issued, the TLC assumes that the Other Secondary Address (OSA) message has been received, which causes:

• The TLC Talker or Listener function to go to its idle state (TIDS=1 or LIDS=1) if the either

the TPAS or LPAS bit was set.

• The GPIB DAC message to be sent true, and the handshake to be finished.

Until a GPIB Primary Command Group (PCG) message is received (that is, as long as the subsequent messages are secondary addresses), the APT bit is set and a DAC holdoff is in effect each time a GPIB secondary address is received. In this way, the GPIB CIC can address several devices having the same primary address without repeating the primary address each time. If a PCG message is received before a secondary address is received, the TPAS and LPAS bits are cleared.

Sending/Receiving Messages

When the GPIB-1014P is a GPIB Talker or Listener, data (device-dependent messages) can be sent or received.

To send data, wait until the GPIB-1014P has been programmed or addressed to talk and the CDOR is empty. When this occurs, the DO bit in the ISR1 is set, indicating that it is safe to write a byte to the CDOR. The DO bit is set again once the byte has been received by all GPIB Listeners.

To receive data, wait until the GPIB-1014P has been programmed or addressed to listen and the DIR is full. When this occurs, the DI bit in the ISR1 is set indicating that the GPIB Talker has written a byte to the DIR. Once that byte has been read, the DI bit will be set again when a new byte is received from the GPIB Talker.

Determining when the CDOR is empty or the DIR is full can be done by polling the ISR1 until the DO or DI status first appears or by allowing a program interrupt to occur on the respective event. Remember, however, that the status bits and interrupt signals are cleared when the ISR1 is read, so the absence of a true DO or DI status does not indicate that the CDOR is still full or that the DIR is still empty.

Programming Considerations Section Five

Sending/Receiving END or EOS

The GPIB END message is sent by issuing the Send EOI auxiliary command just before writing the last data byte to the CDOR. The GPIB EOS message is sent simply by making the last byte written to the CDOR the End Of String (EOS) code.

The END status bit or interrupt is used to inform the program of the receipt of an END or EOS message.

Interrupts

The interrupt circuitry of the GPIB-1014P allows the board to interrupt the CPU to request service. Prior to use, the following three characteristics of the interrupter must be set (see Interrupt Request Line Selection in Section Three for details):

• The interrupt request (IRQ) line is selected via a hardware jumper.

• The interrupt priority is determined by three switches.

• The encoded value of the switches must match the interrupt request line.

• A Status/ID byte is set by an 8-switch DIP. This byte is used by the operating system to determine the appropriate interrupt handler.

The µPD7210 TLC is the only source of interrupts on the GPIB-1014P. The TLC generates interrupts on any of the 13 conditions specified by the ISR1 and ISR2 bits. For one of these conditions to drive the selected IRQ line, the following criteria must be satisfied:

• The interrupt condition must be true.

• The interrupt condition must be enabled (bits in IMR1 and IMR2).

• The µPD7210 interrupt signal must be programmed to be active high (see Auxiliary Register B in Section Four).

After an interrupt is generated, the operating system will ask the interrupting source for a Status/ID byte so that it can branch to the appropriate interrupt handler. The status of the TLC interrupt is then found by reading the appropriate TLC status registers.

The status bits in ISR1 or ISR2 are all automatically cleared when the register is read, even if the conditions are still true. If two conditions are true at the same time (that is, more than one bit in ISR1 or ISR2 is set), software copy of the register must be maintained if the program is going to analyze the conditions one at a time.

Serial Polls

Conducting Serial Polls

The TLC, as CIC, serially polls other devices as described in the IEEE-488 specification. From the programming point of view, the TLC must first become Active Controller to send the addressing and enabling commands to the device being polled, make itself a GPIB Listener by issuing the Listen auxiliary command, and then go to standby with the Go To Standby auxiliary command in order to read the status byte.

Section Five Programming Considerations

Responding to a Serial Poll

The CIC can conduct Serial Polls to determine which device is asserting the GPIB SRQ signal to request service.

Before requesting the service, the recommended practice is to wait until the PEND bit in the SPSR is zero, indicating that the TLC is not presently in the middle of a Serial Poll (SPAS=0). If PEND=0, write the desired Status Byte (STB) into the SPMR with the rsv bit set. At that time, PEND sets and remains set until the Serial Poll completes.

Once rsv is set, the TLC waits until any current Serial Poll is complete and then asserts the GPIB SRQ signal. In response to that signal, the CIC starts the poll addressing the TLC to talk. When the CIC unasserts ATN, the TLC unasserts SRQ and transfers the STB message onto the GPIB data bus with DIO7 (the RQS signal) asserted.

While the Serial Poll is in progress (SPAS=1), the CIC normally reads the STB only once; however, it can read it any number of times provided that it asserts ATN between each one byte read. RQS is set only during the first read. After the first read, rsv also is cleared. PEND is cleared when the CIC asserts ATN to terminate the poll.

The GPIB EOI line is asserted along with the status byte (that is, the END message is sent) during the serial poll if bit B1 of the AUXRB is set.

Programming Considerations Section Five

Parallel Polls

Parallel Polls are used by the GPIB Active Controller to check the status of several devices simultaneously. The meaning of the status returned by the devices being polled is devicedependent. There are two general ways in which Parallel Polls are useful:

• When the GPIB Controller sees SRQ asserted in a system with several devices, it can quickly determine which one needs to be serially polled usually using only one Parallel Poll.

• In systems in which the Controller response time requirement to service a device is low and the number of devices is small, Parallel Polls can replace Serial Polls entirely, provided that the Controller polls frequently.

Although the Controller can obtain a Parallel Poll response quickly and at any time, there can be considerable front-end overhead during initialization to configure the devices to respond appropriately. This is contrasted with Serial Polls, where the overhead, in the form of addressing and enabling command messages, occurs with each poll.

Conducting a Parallel Poll

The TLC as Active Controller has the capability to conduct a Parallel Poll. When the Execute Parallel Poll auxiliary command is issued and the TLC internal local message rpp is set, the Parallel Poll is executed (that is, the GPIB message IDY is sent true) as soon as the TLC Controller interface function is placed in the proper state (CAWS or CACS). The Parallel Poll Response (PPR) is automatically read from the GPIB DIO lines into the CPTR and the rpp local message is cleared. A program can determine that the Parallel Poll operation is complete based on the condition of CO (CO=1 when the poll is complete). The response can be obtained by reading the contents of the CPTR. The response is held in the CPTR until a GPIB command is transmitted or the TLC Controller function becomes inactive.

In response to IDY, each device participating in the Parallel Poll drives one and only one GPIB DIO line (its Parallel Poll response or PPRn) active true or passive false, while it drives the other lines passive false.

Since there are eight data lines, and for each line there can be one response (true or false) for each device (2 lines/device), there are 16 possible responses. The line that a device uses and how that device drives the line depends on how it was configured and whether its local individual status message (ist) is one or zero. Thus, each device on the GPIB can be configured to drive its assigned DIO line true if ist=1 and to drive the DIO line false if ist=0; or it can be configured to do exactly the opposite; that is, to drive the DIO line true if ist=0 and false if ist=1. (The meaning of the value of ist, whether one or zero, is system-dependent or device-dependent.)

Because the data lines are driven Open Collector during Parallel Polls, more than one device can respond on each line. The device or devices asserting the line true overrides any device asserting the line false. The Controller must know in advance whether a true response means the local ist message of the device is one or zero. To do this, the device must be configured to respond in the desired way. Two methods can be used to accomplish this:

• Local configuration (Parallel Poll function subset PP2) involves assigning a response line and sense from the device side in a manner similar to assigning the device GPIB address. Thus, one device might be assigned to respond with remote message PPR1 (driving DIO1), while a

Section Five Programming Considerations

second device might be assigned to respond with the remote message PPR3 (driving DIO3), both positive (that is, true response if ist=1). Local configuration is static in that it does not change after the system is integrated (that is, hardware configured and installed).

• Remote configuration (Parallel Poll function subset PP1) involves the dynamic assigning of the response line and sense to devices on the GPIB. This is accomplished using Parallel Poll Enable (PPE) and Parallel Poll Disable (PPD) commands, which are issued by the Active Controller. The sequence for remotely configuring devices on the GPIB is as follows:

1. Become Active Controller.

2. Send the GPIB UNL message to unaddress all GPIB Listeners.

3. Send the listen address of the first device to be configured.

4. Send the GPIB PPC message to all devices followed by the PPE message for that device.

5. Repeat from the second step (UNL) for each additional device.

The same procedure should be followed to disable polling with PPD (for example, when changing responses during reconfiguration).

Responding To a Parallel Poll

Before the GPIB-1014P can be polled by the CIC, the TLC must be configured either locally by your program at initialization time or remotely by the CIC. Configuration involves the following:

• Enabling the TLC to participate in polls

• Selecting the sense or polarity of the response

• Selecting the GPIB data line on which the response will be asserted when the CIC issues the IDY message

With remote configuration (PP1), the TLC interprets the configuration commands received from the CIC, without any software assistance or interpretation from your program. With local configuration (PP2), the three actions listed must be explicitly handled in the software by writing the appropriate values to the U, S, and P3 to P1 bits of the PPR. Refer to the PPR description in Section Four for more information.

Once the PPR is configured, all that remains for your program is determining the source and value of the local individual status (ist) message. If the ISS bit in the AUXRB is zero, ist is set and cleared via the Set and Clear Parallel Poll auxiliary commands. If ISS is one, ist is set if the TLC's Service Request function is in the Service Request State (SRQS) and the TLC is asserting the GPIB SRQ signal line and cleared otherwise. Consequently, setting ISS ties the Parallel Poll function to the Service Request function and also to the Serial Poll process.

The particular response sent by the GPIB-1014P during a Parallel Poll is determined by the value of ist and the configuration of the GPIB-1014P. The value of ist and the actual configuration must be decided by the GPIB system integrator. The response can be changed dynamically during program execution by changing the value of ist and, when remote configuration is used, by reconfiguration.

Section Six Theory of Operation

This section discusses the major elements of the GPIB-1014P in detail with references to signals and circuits shown in the schematic diagrams in Appendix B. However, a brief description of the GPIB-1014P interface with a functional block diagram is provided in Section Two (see Figure 2-4).

Signal names in the following discussion are referenced in terms of logic value (true or false, and asserted or not asserted), and also in terms of logic level (TTL high or low). Both positive and negative logic symbols are used in the schematic diagram. The terms clear, negate, unassert, reset, and set false are synonymous as are set, assert, and set true. Since in the circuit implementation some positive true signals are derived from the inverted output of flip-flops, these terms are not synonymous with the device signals CLR (clear) and PR (preset).

VMEbus Interface

Low-power Schottky Transistor Transistor Logic (LSTTL), Advance Low-power Schottky Transistor Transistor Logic (ALSTTL), or Fast Transistor Transistor Logic (FTTL) logic devices buffer address, data, control, and status signals to or from the VMEbus. All drivers drive the proper amount of current as required by the VMEbus specification, and all receivers meet the bus loading limits as called out by the VMEbus specification.

Data Lines

An F245 octal bus transceiver connects VMEbus data lines D00 through D07 to the GPIB-1014P. During interrupter Status/ID cycles or read cycles to the GPIB-1014P, the F245 is directed to allow the GPIB-1014P to drive the data bus. During write cycles, the direction of the F245 is reversed to allow the Talker, Listener, Controller (TLC) registers to receive data from the VME data bus. The F245 transceiver is enabled when either the EV or the STB signal is high. The EV signal is asserted to allow the interrupter to drive the data bus with a Status/ID byte while the STB signal is asserted to enable the F245 during a data transfer cycle.

Control Signals

Note: An asterisk implies that the signal is active low.

The GPIB-1014P receives the VMEbus control signals DTACK*, DSO*, IACKIN*, and WRITE* with LS240 buffers, while an ALS244 buffer receives DS1*, WRITE*, and AS*. The slave monitors DTACK* to make certain the VME data bus has been released before beginning a data transfer.

FTTL gates drive IRQ1* through IRQ7*, DTACK*, and IACKOUT*. The DTACK* and IRQ* drivers have open-collector outputs. The GPIB-1014P does not drive the other control signals.

Theory of Operation Section Six

Two onboard signals, LDTACK* and IDTACK*, determine the control of DTACK*. The Read/Write State Machine drives LDTACK* which is used during read and write cycles, while the interrupter circuitry controls IDTACK* which is used during Status/ID cycles. DTACK* is asserted when either of these signals is true; DTACK* is released when both LDTACK* and IDTACK* are false and DSO* and DS1* are both high.

Since the GPIB-1014P does not request control of the bus, the VMEbus daisy chain bus grant signals BG0IN* through BG3IN* are connected directly to the corresponding BG0OUT* through BG3OUT* lines.

Address Lines

Two LS2521 comparators receive VMEbus address lines A04 through A15, and the address modifier lines AM4, AM3, AM1, and AM0 for decoding. An FTTL gate receives AM5, AM2 , and LWORD* which are also used in decoding.

An ALS244 buffer receives address lines A01 through A03. These addresses are latched when AS goes high, provided the GPIB-1014P is not active in a data transfer cycle by holding MDTACK* low. The GPIB-1014P holds MDTACK* true while it is driving the VMEbus signal DTACK*. Latching these addresses assures that the proper address will be present at the TLC for internal decoding when addresses are pipelined.

Address Decoding

The GPIB-1014P occupies a 16-byte space; you determine the base address by setting the switches on U28 and U29 (see Section Three, Configuration and Installation). The GPIB-1014P only responds if the address modifier codes indicate 16-bit addressing. This code is either 29 or 2D depending on whether you choose supervisory or non-privileged access. An onboard jumper selects the access mode (see Access Mode.in Section Three).

An F20 NAND gate, an S02 NOR gate, and two LS2521 8-bit comparators decode the GPIB1014P base address and address modifier codes. When the base address is matched, the address modifier codes indicate 16-bit addressing (AM0 through AM5 = 29 or 2D), and LWORD* and IACK* are both high; then both LS2521 outputs become true, and the D input of flip-flop U24 becomes high. If one of these conditions is not met, then the D input is low.

The signal AS-25 clocks the result of the decoding circuitry. AS-25 is the address strobe signal delayed 25 nsec. The delay assures that the decoding has been completed and the result is valid. The clocked output signal is labeled MCYC. If MCYC is false, the GPIB-1014P is prevented from taking any action until a new address cycle begins. If MCYC is true, the GPIB-1014P is able to respond if DS0* goes low. DS1* is not monitored for the purpose of distinguishing 16-bit transfers from 8-bit transfers, so the GPIB-1014P responds to BYTE (0-1) or BYTE (2-3) accesses. The upper byte is not used during a write cycle and returns a hex value of FF during a read cycle. When the master releases AS*, MCYC is cleared and the GPIB-1014P is ready for a new data transfer cycle.

Section Six Theory of Operation

Clock and Reset Circuitry

An LS240 receives the 16 MHz utility SYSCLK provided on the VMEbus. The Read/Write State Machine uses the 16 MHz clock to control the timing of the signal DTACK* and the TLC inputs RD* and WR* (see Timing Control Logic). This clock is divided to 8 MHz for the CLOCK signal used by the TLC. The VMEbus signal SYSRESET* initializes the TLC, the interrupter, and the timing control circuitry.

Timing Control Logic

When the GPIB-1014P is addressed (see Address Decoding in this section), AS-25 clocks the local signal MCYC true. If another module is asserting DTACK* when MCYC becomes true (that is, the address is pipelined to the GPIB-1014P), the GPIB-1014P waits for DTACK* to be released and for DS0* to be asserted. The GPIB-1014P then asserts STRT after delaying a minimum of 85 nsec in order to meet the TLC address set-up time.

If DS0* is never asserted, the cycle is an Address-Only (ADO) cycle. In this case, MCYC is cleared when AS* goes high, and the GPIB-1014P takes no further action. For more information on ADO cycles, see IEEE Standard for a Versatile Backplane Bus: VMEbus.

An LS74A D-type flip-flop and an LS393 dual 4-bit counter implement a state machine to control the timing during Read/Write cycles. The timing control begins when STRT becomes true. If the VMEbus signal WRITE* is false, indicating a read cycle, the TLC RD* signal is driven true and the data bus drivers are enabled immediately. The state machine then uses the VMEbus utility SYSCLK to count a minimum delay of 250 nsec, which corresponds to the read access time of the TLC. At this time, the local signal LDTACK* becomes true, signaling the DTACK* assert/release circuitry to drive the VMEbus signal DTACK* low. This indicates that valid data is present on the data bus. The data remains valid until DS0* is released, at which time the signals DEN* and LDTACK* go high. The DTACK* assert/release circuitry releases DTACK* once it sees that the bus driver has been released (DEN* is high) and that DS1 is high. The state machine then delays for a recovery time of 250 nsec.

The timing control for a write operation is similar to a read operation. When STRT and the VMEbus signal WRITE* are true, the TLC WR* is driven true, and the data bus receivers are enabled immediately. The state machine counts a data setup time of 250 nsec before driving the WR* signal false and asserting LDTACK* (thus asserting DTACK*). Data is latched into the TLC on the trailing edge of the WR* signal. The DTACK* signal remains asserted until the bus master releases DS0* and DS1* and the F245 releases the VME data bus. After a recovery time of 250 nsec, the state machine is ready to begin the next operation. Accesses to the GPIB-1014P during this recovery time are recognized, but are delayed until the recovery time has elapsed.

Interrupter Logic

The interrupter circuitry permits the GPIB-1014P to request service. The circuitry consists of four flip-flops, an F85 4-bit magnitude comparator, three 25 nsec digital delay gates, and some miscellaneous gates.

Theory of Operation Section Six

When the TLC drives its INT line, the interrupter immediately pulls one of the interrupt request lines low (see VMEbus Interrupt Request Line in Section Three). The F85 comparator compares the address lines A01 through A03 with the priority you select on U28 and sets the A=B output high if there is a match during an interrupt acknowledge cycle.

Note: The priority you select must match the interrupt request line (see Interrupt Request Priority

in Section Three).

The VME signal AS is delayed 25 nsec to allow the comparator output to stabilize. This delayed signal then clocks the result of the comparison. AS is delayed an additional 25 nsec before asserting IACKOUT* or responding with a STATUS/ID byte. This additional delay assures that the output of the flip-flop will be stable before the logic selects to either pass the interrupt of the comparison or respond with a status byte.

If the output of the flip-flop is latched true, the interrupter is set to respond with a STATUS/ID byte. The interrupter waits for IACKIN and DS0 to become true, as well as for the signal AS that has been delayed 50 nsec, and makes certain that the VME signal DTACK* has been released. At this time, an enable vector signal, EV, is latched in order to enable the data bus transceiver for the entire transfer cycle. The complement, EV*, enables an F244 to drive the VME data bus with a STATUS/ID byte (which you determine by setting onboard switches as described in Interrupt Status/ID Byte in Section Three). Two inverters delay EV* to allow for data set-up on the VMEbus; EV* then signals the DTACK* Asset/Release circuitry, via IDTACK*, to drive DTACK* true.

EV and EV* are held true until the interrupt handler releases DS0*. The rise of EV* releases the IRQ* line. Therefore, the GPIB-1014P is a Release On AcKnowledge (ROAK) interrupter.

Note: Even though the VMEbus interrupt request line is no longer driven, the TLC INT line

remains asserted until it is cleared in the interrupt service routine by reading the appropriate interrupt status register (ISR1 or ISR2). The appropriate interrupt status register must be read to enable further interrupts from the GPIB-1014P.

The DTACK* assert/release circuitry releases DTACK* after the F245 ceases driving the data bus (DEN*=1), IDTACK* is high, and DS1* is released.

If the address lines A01 through A03 do not match the indicated priority of the GPIB-1014P, the Q* output of the flip-flop is latched high, indicating that IACKOUT* is to be asserted. After IACKIN and the delayed AS are received high, the VMEbus signal IACKOUT* is driven low. IACKOUT* is released within 30 nsec of AS* being released.

GPIB Interface

The GPIB-1014P is interfaced to the GPIB using an NEC µPD7210 Talker/Listener/Controller (TLC) large scale integrated circuit. The TLC contains most of the logic circuitry needed to program, control, and monitor the GPIB interface functions that are implemented by the GPIB1014P. Access to these functions is through eight read-only registers and 13 write-only registers, five of which are indirectly addressed. These registers occupy a block of 16 memory addresses (eight consecutive odd addresses).

Section Six Theory of Operation

The TLC is enabled during the TLC CS* pulse, and the IEEE-1014 bus address signals A1 through A3 are decoded internally to access the appropriate register. Data on the IEEE-1014 bus are strobed into write-only registers at the trailing edge of WR*. Data in the read-only registers are placed on the IEEE-1014 bus in a minimum access time after TLC CS* and RD* are both true.

Most of the TLC GPIB interface functions can be implemented or activated from either side; that is, the TLC can be programmed to do these functions by the VMEbus master or it can be addressed to do them by the GPIB Controller. In terms of the IEEE-488 standard, the distinction between these two modes of operation is generally the same as that between local and remote interface messages, respectively.

The ADSR is the primary register for monitoring the current status of the TLC; that is, to determine if it is a GPIB Talker, GPIB Listener, GPIB Active Controller, or in GPIB remote or local mode. The CPTR provides a means to read the GPIB data bus directly and is used to recognize interface messages that are not automatically decoded and implemented by the TLC.

The Address Register (ADR) is used to program two address registers, ADR0 and ADR1, which contain the GPIB addresses (recognized by the TLC) and Talker and Listener disabling bits. The manner in which the TLC uses these registers depends on the address mode established in the ADMR. A bit in ADR1 indicates if END was set on the last byte received.

IMR1 and IMR2 are interrupt mask registers for enabling and disabling the interrupt from the TLC on the occurrence of 13 specific GPIB conditions or events. The status of these conditions can be read from the ISR1 and ISR2 registers. The status bits in these registers function independently of the corresponding mask bits; that is, they are set and cleared regardless of whether an interrupt request is enabled for the condition. An important fact to remember is that ISR1 and ISR2 are always cleared when read, even if the condition which caused the bit to be initially set remains true.

Data to and from the GPIB is pipelined through the CDOR and DIR respectively. An 8 MHz clock is used as the CLOCK input to the TLC. For proper GPIB timing, the internal counter register must be programmed to eight. The TLC RESET pin is driven by the GPIB-1014 RESET signal.

The AUXMR is used to issue special commands to the TLC and write to the five hidden registers. The Parallel Poll Register (PPR) locally configures the TLC for polling. Auxiliary Registers A, B, and E (AUXRA/B/E) provide a means to control a variety of diverse functions, such as enabling handshake holdoffs, transmitting END when the EOS byte is sent, setting the END RX bit when EOS is received, and enabling high speed transfers.

Two special purpose transceivers, a 75160 for the data signals and a 75162 for the handshake and interface management signals, interface the TLC to the GPIB. Three signals from the TLC (T/R1 through T/R3) and the SC signal from the System Controller Select logic control signal direction of these two transceivers. Controlling the direction of the data, handshake, and EOI signals, T/R1 is high when the TLC is a Talker or Active Controller, and low when it is a Listener. Controlling the direction of the ATN and SRQ signals, T/R2 is high when the TLC is Controller-In-Charge (CIC) and low otherwise. T/R3 is high when the three-state driver mode is active and low when the open collector mode is active. When the GPIB-1014P is parallel polled, the transceiver switches to open collector mode. SC is set whenever the System Controller Select logic senses that the TLC has received the Set IFC auxiliary command; SC is cleared when the TLC receives the Release System Control auxiliary command. SC controls the direction of the IFC and REN signals, driving the GPIB when SC is high and receiving from the GPIB when it is low.

National Instruments Corporation GPIB-1014P User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

National Instruments Corporate Headquarters

Limited Warranty

Copyright

Trademarks

FCC/DOC Radio Frequency Interference Compliance

Preface

Organization of the Manual

Abbreviations Used in This Manual

Related Documents

Customer Communication

Contents

Figures

Tables

Section One General Information

What Your Kit Should Contain

Optional Equipment

Unpacking

Section Two General Description

Physical Characteristics

Electrical Characteristics

Table 2-1. GPIB-1014P Signals

VMEbus Characteristics

VMEbus Slave-Addressing

VMEbus Slave-Data

Interrupter

VMEbus Modules Not Provided

Diagnostic Aids

Data Transfer Features

GPIB-1014P Functional Description

Figure 2-1. GPIB-1014P with a VMEbus Computer

Figure 2-2. GPIB-1014P in a Multiprocessor Application

Figure 2-3. GPIB-1014P Block Diagram

Table 2-3. GPIB-1014P IEEE-488 Interface Capabilities

Table 2-4. GPIB-1014P IEEE-1014 Compliance Levels

Section Three Configuration and Installation

Configuration

Access Mode

Figure 3-2. Access Selection

VMEbus Base Address

Figure 3-3. Configuration for VMEbus Base Address 1000 hex (default setting)

VMEbus Interrupt Configuration

Interrupt Request Line Selection

Figure 3-4. VMEbus Interrupt Line Selection

Note: An asterisk implies that the signal is active low. Interrupt Priority Code

Figure 3-5. VMEbus Interrupt Priority Code Selection

Interrupt Status/ID Vector Selection

Figure 3-6. Status/ID Byte 1A hex

GPIB Cable Shield Grounding

Figure 3-7. GPIB Cable Shield Grounding

Installation

Verification of System Compatibility

Table 3-1. GPIB-1014P Pin Assignment on VMEbus Connector P1

Verification Testing

Cabling

Figure 3-8. GPIB Cable Connector

Section Four Register Bit Descriptions

Register Map

Table 4-1. GPIB-1014P Register Map

Register Sizes

Register Description Format

Terminology

Table 4-2. Clues to Understanding Mnemonics

Interface Registers

Figure 4-2. Writing to the Hidden Registers

Data In Register (DIR)

Command/Data Out Register (CDOR)

Interrupt Status Register 1 (ISR1)

Interrupt Mask Register 1 (IMR1)

Interrupt Status Register 2 (ISR2)

Interrupt Mask Register 2 (IMR2)

Serial Poll Status Register (SPSR)

Serial Poll Mode Register (SPMR)

Address Status Register (ADSR)

Address Mode Register (ADMR)

Command Pass Through Register (CPTR)

Auxiliary Mode Register (AUXMR)