National Instruments ZYNQ XC7Z020-1CLG484C User Manual

USER MANUAL

NI Digital System Development
Board

The Digital System Development Board (DSDB) is an NI ELVIS add-on board featuring a
Zynq 7020 All Programmable SoC (AP SoC) that was designed by Digilent for National
Instruments. When paired with the NI ELVIS platform, it becomes an ideal lab installation for
classes centered on digital and analog circuits. The DSDB also has the ability to be used as a
standalone Zynq development platform, independent of NI ELVIS.

Contents

Contents .................................................................................................................................... 1

Features..................................................................................................................................... 3

Hardware Components .............................................................................................................5

Power Supplies ......................................................................................................................... 6

I

nput Power Monitoring ................................................................................................... 9

User Power Supplies......................................................................................................... 9

User Power Supplies Monitoring .

Zynq AP SoC Architecture....................................................................................................... 11

Zynq Configuration .................................................................................................................. 15

microSD Boot Mode...........

Quad-SPI Boot

JTAG Boot Mode ..........................

Connecting to NI ELVIS ..........................................................................................................16

SPI Flash................................................................................................................................... 18

DDR3 Memory ......................................................................................................................... 19

USB UART Bridge (Serial Port) .............................................................................................. 20

microSD Slot ............................................................................................................................ 20

USB HID Host.......................................................................................................................... 21

HID Controller.......................................................................................................................... 21

Keyboard .................................................................................................................................. 22

Mouse ....................................................................................................................................... 24

Ethernet..................................................................................................................................... 25

OLED........................................................................................................................................ 26

VGA Port.................................................................................................................................. 29

VGA System Timing ................................................................................................................ 29

HDMI Source/Sink Port ...........................................................................................................33

Touchscreen Display ................................................................................................................ 34

LCD Display...

Capacitive Touchscreen....

Mode ....................................................................................................... 16

..................................................................................................................34

................................................................................................ 36

.................................................................................... 10

.............................................................................................. 16

................................................................................... 16

Clock Sources ........................................................................................................................... 39

Basic I/O ................................................................................................................................... 39

Seven-Segment Display ............................................................................................................ 40

Audio ........................................................................................................................................ 42

Reset Sources ............................................................................................................................43

Power-on Reset .
Program Push B
Processor Sub

................................................................................................................43

utton Switch............................................................................................44

system Reset...............................................................................................44

User IO Protection .................................................................................................................... 44

Pmod Connectors ......................................................................................................................44

Stan

dard Pmod..................................................................................................................45

MIO Pmod ..............

..........................................................................................................45

MXP Connector ........................................................................................................................46

Breadboards .............................................................................................................................. 47

NI ELVIS Analog Breadboard .

FPGA Digital IO Breadboard ....................................................................

Power

Breadboard.............................................................................................................48

........................................................................................48

.......................48

DSDB Programming Guide ...................................................................................................... 48

Programming in LabVIEW FPGA ..

Pr

ogramming in Multisim.................................................................................................53

.................................................................................48

Installation and Setup................................................................................................................ 62

Wh

at You Need to Get Started .........................................................................................62

Installation and

Setup Instructions....................................................................................63

2 | ni.com | NI Digital System Development Board User Manual

Features

Figure 1. The Digital System Development Board

The DSDB includes the following features:

ZYNQ XC7Z020-1CLG484C

• 650 Mhz dual-core Cortex-A9 processor

• DDR3 memory controller with 8 DMA channels

• High-bandwidth peripheral controllers: 1G Ethernet, SDIO

• Low-bandwidth peripheral controller: SPI, UART, CAN, I2C

• On-chip analog-to-digital converter (XADC) Programmed using JTAG, Quad-SPI Flash, or
microSD

•

Reprogrammable logic equivalent to Artix-7 FPGA

• 13,300 logic slices, each with four 6-input LUTs and eight flip-flops

• 560 KB of fast block RAM

• Four clock management tiles, each with a phase-locked loop (PLL) and mixed-mode

clock manager (MMCM)

• 220 DSP slices

• Internal clock speeds exceeding 450 MHz

NI Digital System Development Board User Manual | © National Instruments | 3

System Features

• 512 MB DDR3 with a 32-bit bus @ 1050 MHz

• 16 MB quad-SPI flash

• microSD socket for additional storage

• USB-JTAG programming circuitry

• Current and voltage monitoring on expansion connectors

• Powered from the NI ELVIS connector or 5 V barrel jack input

System Connectivity

• 16-bit VGA output

• Dual-role (source/sink) HDMI port

• NI ELVIS add-on connector

• 24-bit audio codec with headphone, line out, line in, and microphone jacks

• 10/100/1000 Mbps ethernet

• USB-UART bridge

Interaction and Sensory Devices

• 800 × 480 5-in. LCD display with capacitive touchscreen

• 128 × 32 monochrome OLED Display

• Four-digit 7-segment display

• USB HID connector for mice and keyboards

• Eight FPGA-connected LEDs

• One processor-connected LED

• Four push buttons

• Eight slide switches

Expansion Connectors

• MXP Connector

• Breadboard with analog I/O from NI ELVIS and digital I/O from Zynq

• Two Pmod connectors with eight FPGA I/O each

• One Pmod connector with eight Processor I/O

The DSDB is compatible with Xilinx’s new high-performance Vivado Design Suite as well as
the ISE/EDK toolset. These toolsets meld FPGA logic design with embedded ARM software
development into an easy to use, intuitive design flow. They can be used for designing systems
of any complexity, from a complete operating system running multiple server applications in
tandem, down to a simple bare-metal program that controls some LEDs.

4 | ni.com | NI Digital System Development Board User Manual

Hardware Components

NI ELVIS II Series

Figure 2. The NI Digital System Development Board

11

ELVIS ANALOG

A12

A11

A12

A11

++–

–+–

++–

MXP

+–

9

8

7

6

5

LINE IN

MIC IN

LINE OUT

HPH OUT

1

5

10

ABCD E FGHI J

1

5

10

DISP2

AIGND

15

15

–+–

AO1

AIGND

AO0

AISNS

AO0

AISNS

AO1

AIGND

20

25

20

25

FPGA DIGITAL IO POWER

A10

A10

AIGND

3V3

5 <Y15>

6 <K15>

7 <L16>

GND

3 <W18>

AIGND

4 <W17>

30

35

30

35

2 <Y16>

1 <AB14>

0 <AA13>

40

40

–

+

VPS

VPS

GND

3V3

45

45

GND

ELVIS

15V–15V

–

ELVIS/

EXT

GND

GND

GND

+15V

+15V

+5V

+15V

50

50

131210

14

ON

EXT POWER

+5V

+5V

OFF

PGOOD

+–

55

60

55

ABCDE FGHI J

60

15

16

designed by

for National Instruments

DISP1

17

4

18

3

LD15

2

1

MI07

Digital Systems

Development Board

for

NI ELVIS II Series

25

1 One Processor-Connected LED
2Micro SD Card
3 10/100/1000 Mbps Ethernet
4 Dual-Role (Sink/Source) HDMI
5 16-Bit VGA Output
6 Headphone
7 Line Out
8 Microphone
9 24-Bit Audio Codec Line In
10 MXP Connector
11 NI ELVIS II/II+ Connector
12 Breadboard with Analog I/O from

NI ELVIS II/II+ and Digital I/O from
the Zynq APSoC

13 5V Input Power Jack

LD7

LD6

LD5

LD4

LD3

LD2

LD1

LD0

<Y8>

<U8>

<W11>

<W12>

<V10>

<W7>

24

<Y9>

<U7>

J13

23

22

14 Power Switch
15 Four-Digit, Seven-Segment Display
16 128  32 Monochrome OLED Display
17 800  480 5” LCD Display with Capacitive

Touchscreen
18 Zynq XC7Z020-1CLG484C with included Heat Sink
19 512 MB DDR3 with a 32-Bit Bus @1050 MHz,

16 MB Quad-SPI Flash
20 USB HID Connector
21 USB-JTAG Programming Circuitry USB-UART Bridge
22 Eight FPGA-Connected LEDs
23 Four Push Buttons
24 Eight Slide Switches
25 Three PMOD Connectors (Two Routed to FPGA and

One Routed to Processor)

19

20

21

NI Digital System Development Board User Manual | © National Instruments | 5

Power Supplies

The DSDB is powered from the NI ELVIS platform or an external power supply connected to
J17 (when used as a standalone platform). Connector J17 is placed in a way which doesn't allow
the connection of an external supply when the board is plugged into the NI ELVIS platform. This
was done to prevent the user from incorrectly attaching an external supply while the NI ELVIS
is powering the DSDB.

The NI ELVIS platform can deliver maximum 2 A of current on the 5 V output according to the
specifications. This should provide enough power for typical use. A typical application
represents a Zynq configuration that uses all on-board peripherals, 0.2 A load on each of the two
user supplies (5 V and 3.3 V), mouse connected to the USB HID port (J9), and analog outputs
in the MXP connector (J4) left floating. If more features are intended to be used, for example
drawing more power from the user supplies, a power demanding FPGA configuration, or
connecting a USB device that needs more than 100 mA, the DSDB board should be used as
standalone with an external power supply.

When used as a standalone platform an external power supply should be used by plugging into
the power jack (J17). The supply must use a coax, center-positive 2.1 mm internal-diameter
plug, and deliver 4.6 VDC to 5.5 VDC and at least 2 A of current (that is, at least 12.5 W of
power) for typical use cases and 4 A (20 W of power) for power demanding applications.
Suitable supplies can be purchased from the Digilent website or through catalog vendors like
DigiKey. Power supply voltages outside the above range will prevent the board from powering
up, while voltages above 18 V will cause permanent damage.

All on-board power supplies are enabled or disabled by the power switch (SW9). The power
indicator LED (LD14) is on when all the supply rails reach their nominal voltage. An overview
of the power circuit is shown in Figure 3.

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Figure 3. Power Circuit Overview

Voltage regulator circuits from Analog Devices create the required 3.3 V, 1.8 V, 1.5 V, and 1.0 V
supplies from the main power input. Table 1 provides additional information (typical currents
depend strongly on FPGA configuration and the values provided are typical of medium
size/speed designs).

NI Digital System Development Board User Manual | © National Instruments | 7

Table 1. DSDB Power Supplies

Supply Circuits Device

Current

(max/typical)

5.125 V User Voltage, Analog Reference,
Buffers for User IO

3.3 V FPGA I/O, USB ports, Clocks,
Ethernet, SD slot, Flash, HDMI, User

IC53:
ADP1613

IC55#1:
ADP5052

Voltage, LCD, touch panel, OLED

1.0 V FPGA, Ethernet Core IC55#2:

ADP5052

1.8 V FPGA Auxiliary, Ethernet I/O, USB
OTG

IC55#3:
ADP5052

1.5 V DDR3 IC55#4:

ADP5052

1.8 V XADC Analog IC26#5:

ADP5052

3.3 V Audio Analog IC6:

ADP150

10 V Analog Output Stage D28, C351,

C349

1 A/0.02 to 0.5 A

2.5 A/0.1 A to
2A

4 A/0.2 A to 4 A

1.2 A/0.1 A to

0.5 A

1.2 A/0.1 A to

1.2 A

200 mA/20 mA

150 mA/50 mA

15 mA/2 mA

-5 V Analog Output Stage D29, C355,

C356

1.25 V XADC Precision Reference IC27:

ADR127

2.5 V Reference for DAC and ADC IC61:

ADR3425

19.2 V LCD Backlight IC54:

FP6745

4.28 V Digital User IO Buffers IC19:

ADP123

5V User Voltage IC46:

ADP123

User Voltage IC49:

TPS2553

15 mA/2 mA

5mA/50A

10 mA/50 A

40 mA/0 to
40 mA

0.3 A/2 mA

0.3 A/0 to 0.3 A

0.3 A/0 to 0.3 A

8 | ni.com | NI Digital System Development Board User Manual

The supply rails are daisy-chained to follow the Xilinx-recommended start-up sequence.
Flicking the power switch (SW9) will enable the 5.125 V (IC53) rail, which enables the 1 V
digital supply rail, which in turn enables the supply rails 1.8 V, 3.3 V, and 1.5 V. The 1.25 V
reference, 1.8 V analog supply and 10V, -5V charge pumps ramp together with the 3.3 V rail.
Once all the channels of the ADP5052 (IC55) supply reach regulation, the PGOOD signal will
assert, enabling the 3.3 V audio supply, lighting up the power LED (LD14), enabling user
supplies (IC46, IC49) and power supply for user IO buffers (IC19) and de-asserting the
Power-On Reset signal (PS_POR_B) of the Zynq.

Each power supply uses a soft-start ramp of 1-10ms to limit in-rush current. There is an
additional delay of at least 130ms after the power rails reach regulation and before the Power-On
Reset signal de-assert to allow for the PS_CLK (IC22) to stabilize.

Input Power Monitoring

The DSDB includes a TPS25940i power monitoring switch placed on the 5 V input power rail.
This circuit provides input over and under voltage protection, fast response short-circuit
protection, and slew rate controlled startup to limit inrush current. In case the input supply
voltage is outside the operating range of 4.6 V to 5.5 V, or if the current consumption exceeds

4.4 A, the TPS25940 will turn off the board power.

User Power Supplies

The DSDB provides two user power supplies, 5 V and 3.3 V. The 5 V user supply is available
at the MXP connector, while the 3.3 V is accessible at the PMODs (JA, JB, JC), MXP connector
(J4) and in the digital breadboard (BB3). Each of these two power supplies are able to source up
to 0.3 A and provide the following protection features:

• Short-circuit protection

• 0.3 A current limitation

• Reverse current protection

• Zener protection from accidental shorts to a higher voltage

• Protection from accidental shorts to a reverse polarity voltage

Both of these user supplies turn on automatically after the 5.125 V and FPGA supplies (3.3 V,
1 V, 1.8 V, 1.5 V) are in regulation and the PGOOD signal is asserted. As soon as the PGOOD
signal is deactivated, these user supplies turn off. Alternatively, the user has the ability to disable
these outputs from the FPGA by driving the USER_POWER_EN signal low.

Besides disabling user supplies the USER_POWER_EN signal will also deactivate, the 4.28 V
voltage, which is powering the buffers on the digital IOs that go to PMODs (JA, JB, JC), MXP
(J4) and digital breadboard. This way, the communication between FPGA and the above
mentioned expansion connectors is interrupted.

NI Digital System Development Board User Manual | © National Instruments | 9

User Power Supplies Monitoring

The users have the ability to monitor the power of the two user supplies (3.3 V and 5 V) using
the dual channel analog-to-digital converter inside the Zynq (XADC). Both current and voltage
information from the two user supplies are routed to auxiliary analog inputs to the XADC as
differential pairs.

Table 2. Analog Input Pinout

Signal XADC port FPGA pin

XADC_5V0_USER_CURRENT+ AD5P E21

XADC_5V0_USER_CURRENT- AD5N D21

XADC_5V0_USER_VOLTAGE+ AD4P D20

XADC_5V0_USER_VOLTAGE- AD4N C20

XADC_3V3_USER_CURRENT+ AD6P G19

XADC_3V3_USER_CURRENT- AD6N F19

XADC_3V3_USER_VOLTAGE+ AD14P E19

XADC_3V3_USER_VOLTAGE- AD14N E20

The XADC core within the Zynq is a dual channel 12-bit analog-to-digital converter capable of
operating at 1 MSPS. Either channel can be driven by any of the auxiliary analog input pairs.
The XADC core is controlled and accessed from the PL via the Dynamic Reconfiguration Port
(DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s
power rails, and a temperature sensor that is internal to the FPGA. For more information on using
the XADC core, refer to the Xilinx document 7 Series FPGAs and Zynq-7000 All Programmable
SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter. It is also possible to access the
XADC core directly using the PS via the PS-XADC interface. This interface is described in full
in chapter 30 of the Zynq Technical Reference Manual.

The 3.3 V/5 V user voltages are sensed directly at the output through a 1/6 voltage divider. Note
that in case the user power supplies are disabled, the measurement signals
XADC_3V3_USER_VOLTAGE+/-, XADC_5V0_USER_VOLTAGE+/- are disconnected and
the XADC will read 0.The equation below shows how to compute voltage from the XADC
number:

10 | ni.com | NI Digital System Development Board User Manual

The current information is collected across 0.1  sense resistors (R431, R445) placed in front of
the circuits that generate the user voltages (IC46, IC49). Since both of these circuits are linear
devices, the input current matches the current on the output. The voltage across the sense resistor
is fed into a current sense amplifier with a gain of 50, INA216A2, and divided by 5 before it is
connected to the XADC inputs. The equation below shows how to compute current from the
XADC number:

Zynq AP SoC Architecture

The Zynq AP SoC is divided into two distinct subsystems: The Processing System (PS), and the
Programmable Logic (PL). Figure 4 shows an overview of the Zynq AP SoC architecture, with
the PS colored light green and the PL in yellow. Note that the PCIe Gen2 controller and
Multi-gigabit transceivers are not available on the device found on this board.

NI Digital System Development Board User Manual | © National Instruments | 11

Figure 4. Zynq AP SoC Architecture

The PL is nearly identical to a Xilinx 7-series Artix FPGA, except that it contains several
dedicated ports and buses that tightly couple it to the PS. The PL also does not contain the same
configuration hardware as a typical 7-series FPGA, and it must be configured either directly by
the processor or via the JTAG port.

The PS consists of many components, including the Application Processing Unit (APU, which
includes 2 Cortex-A9 processors), Advanced Microcontroller Bus Architecture (AMBA)
Interconnect, DDR3 Memory controller, and various peripheral controllers with their inputs and
outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO pins). Peripheral
controllers that do not have their inputs and outputs connected to MIO pins can instead route
their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are

12 | ni.com | NI Digital System Development Board User Manual

connected to the processors as slaves via the AMBA interconnect, and contain readable/writable
control registers that are addressable in the processors’ memory space. The programmable logic
is also connected to the interconnect as a slave, and designs can implement multiple cores in the
FPGA fabric that each also contain addressable control registers. Furthermore, cores
implemented in the PL can trigger interrupts to the processors (connections not shown in
Figure 4) and perform DMA accesses to DDR3 memory.

There are many aspects of the Zynq AP SoC architecture that are beyond the scope of this
document. For a complete and thorough description, refer to the Zynq Technical Reference
Manual, available at www.xilinx.com. Table 3 depicts the external components connected to the
MIO pins of the DSDB.

Table 3. MIO Pinout

MIO 500 3.3 V Peripherals Peripherals Peripherals

Pin Pmod SPI Flash GPIO

0 JC9

1 CS

2 DQ0

3 DQ1

4 DQ2

5 DQ3

6 SCLK

7 LED15

8 SLCK FB

9 JC8

10 JC4

11 JC2

12 JC3

13 JC1

14 JC7

15 JF10

NI Digital System Development Board User Manual | © National Instruments | 13

MIO 501 1.8 V Peripherals

Pin ENET 0 SDIO 0

16 TXCK

17 TXD0

18 TXD1

19 TXD2

20 TXD3

21 TXCTL

22 RXCK

23 RXD0

24 RXD1

25 RXD2

26 RXD3

27 RXCTL

28-39 Unconnected

40 CCLK

41 CMD

42 D0

43 D1

44 D2

45 D3

46 Unconnected

47 CD

48-51 Unconnected

52 MDC

53 MDIO

14 | ni.com | NI Digital System Development Board User Manual

Zynq Configuration

Unlike Xilinx FPGA devices, AP SoC devices such as the Zynq-7020 are designed around the
processor, which acts as a master to the programmable logic fabric and all other on-chip
peripherals in the processing system. This causes the Zynq boot process to be more similar to
that of a microcontroller than an FPGA. This process involves the processor loading and
executing a Zynq Boot Image, which includes a First Stage Bootloader (FSBL), a bitstream for
configuring the programmable logic (optional), and a user application. The boot process is
broken into three stages:

Stage 0

After the DSDB is powered on or the Zynq is reset (in software or by pressing either the red
button labeled PS-SRSTB or PS-PORB), one of the processors (CPU0) begins executing an
internal piece of read-only code called the BootROM. If and only if the Zynq was just powered
on or the reset was triggered with the PS-PORB button, the BootROM will first latch the state
of the mode pins into the mode register (the mode pins are attached to SW8 on the DSDB). If
the BootROM is being executed due to a software or PS-SRSTB triggered reset event, then the
mode pins are not latched and the previous state of the mode register is used. This means that
the DSDB needs a power cycle to register any change in the programming mode switch (SW8).
Next, the BootROM copies an FSBL from the form of non-volatile memory specified by the
mode register to the 256 KB of internal RAM within the APU (called On-Chip Memory, or
OCM). The FSBL must be wrapped up in a Zynq Boot Image in order for the BootROM to
properly copy it. The last thing the BootROM does is hand off execution to the FSBL in OCM.

Stage 1

During this stage, the FSBL first finishes configuring the PS components, such as the DDR
memory controller. Then, if a bitstream is present in the Zynq Boot Image, it is read and used to
configure the PL. Finally, the user application is loaded into memory from the Zynq Boot Image,
and execution is handed off to it.

Stage 2

The last stage is the execution of the user application that was loaded by the FSBL. This can be
any sort of program, from a simple “Hello World” design, to a Second Stage Boot loader used
to boot an operating system like Linux. For a more thorough explanation of the boot process,
refer to Chapter 6 of the Zynq Technical Reference Manual.

The DSDB supports three different boot modes: microSD, Quad-SPI Flash, and JTAG. The boot
mode is selected using the Mode switch (SW8), which affects the state of the Zynq configuration
pins after power-on.

The three boot modes are described in the following sections.

NI Digital System Development Board User Manual | © National Instruments | 15

microSD Boot Mode

The DSDB supports booting from a microSD card inserted into connector J15. The following
procedure will allow you to boot the Zynq from microSD:

1. Format the microSD card with a FAT32 file system.

2. Copy the Zynq Boot Image created with Xilinx SDK to the microSD card.

3. Rename the Zynq Boot Image on the microSD card to BOOT.bin.

4. Eject the microSD card from your computer and insert it into connector J15 on the DSDB.

5. Set SW8 to

6. Turn the board on. The board will now boot the image on the microSD card.

SD.

Quad-SPI Boot Mode

The DSDB has an onboard 128-Mbit Quad-SPI serial Flash that the Zynq can boot from. Vivado
and Xilinx SDK can be used to generate a Zynq boot image and program it into the Quad-SPI
flash using the USB-JTAG port. Once a boot image has been programmed into the Quad-SPI
flash, do the following to boot the DSDB:

1. Set SW8 to QSPI.

2. Turn the board on. The board will now boot the image stored in the Quad-SPI flash.

JTAG Boot Mode

When placed in JTAG boot mode, the processor will wait until software is loaded by a host
computer using the Xilinx tools. After software has been loaded, it is possible to either let the
software begin executing, or step through it line by line using Xilinx SDK.

It is also possible to directly configure the PL over JTAG, independent of the processor. This can
be done using iMPACT or the Vivado Hardware Server.

The DSDB is configured to boot in Cascaded JTAG mode, which allows the PS to be accessed
via the same JTAG port as the PL. It is also possible to boot the DSDB in Independent JTAG
mode by loading a jumper in JP1 and shorting it. This will cause the PS to not be accessible from
the onboard JTAG circuitry, and only the PL will be visible in the scan chain. To access the PS
over JTAG while in independent JTAG mode, users will have to route the signals for the PJTAG
peripheral over EMIO, and use an external device to communicate with it.

Connecting to NI ELVIS

The DSDB is fully integrated with the NI ELVIS platform, which features 12 of the most
commonly used instruments in the laboratory including an oscilloscope, digital multimeter,
function generator, variable power supplies, digital reader/writer, two- and three-wire
current-voltage analyzers, and a Bode analyzer. Integration with the NI ELVIS platform gives
students the ability to build comprehensive test benches and analog mixed-signal circuits that
can be designed and tested in one platform. The DSDB is also capable of running standalone
when the advanced functionality of the NI ELVIS is not required.

16 | ni.com | NI Digital System Development Board User Manual

The signals from the NI ELVIS edge connector are routed to the Power breadboard header, the
NI ELVIS Analog breadboard header, and the programmable logic of the Zynq. The connections
are described in Tables 4 and 5 below. NI ELVIS pins not listed in the tables below are not
connected to any device on the DSDB. Note that +5 V from this connector is also used to power
the entire board. The GND pins of the NI ELVIS connector, the ground plane of the DSDB, and
the pins labeled GND on the breadboard headers are all connected. For further information on
the functionality of the pins on the NI ELVIS connector, please refer to the NI ELVIS
documentation.

Table 4. NI ELVIS breadboard connections

NI ELVIS Pin Zynq Pin

DIO0 Y20

DIO1 AA16

DIO2 Y19

DIO3 AB16

DIO4 AA18

DIO5 AB15

DIO6 Y18

DIO7 AA14

DIO8 T19

DIO9 AA19

DIO10 U20

DIO11 AB19

DIO12 U10

DIO13 AA17

DIO14 W20

DIO15 AB17

PFI8 N19

PFI9 AB20

PFI12 R21

NI Digital System Development Board User Manual | © National Instruments | 17

Table 5. NI ELVIS Zynq Connections

NI ELVIS Pin Breadboard Header Breadboard Pin

+15V Power +15V

-15V Power -15V

+5V Power +5V

VPS+ Power VPS+

VPS- Power VPS-

AIGND Analog AIGND

AISENSE Analog AISNS

AO0 Analog AO0

AO1 Analog AO1

AI0+ Analog AI0+

AI0- Analog AI0-

AI1+ Analog AI1+

AI1- Analog AI1-

AI2+ Analog AI2+

AI2- Analog AI2-

SPI Flash

The DSDB features a Quad-SPI serial flash device, the Spansion S25FL128S. The Multi-I/O SPI
Flash memory is used to provide non-volatile code and data storage. It can be used to initialize
the PS subsystem as well as configure the PL subsystem (bitstream).

The relevant device attributes are:

• 128 Mbit

• x1, x2, and x4 support

• Speeds up to 94 MHz. In Quad-SPI mode, this translates to 376 Mbps

• Powered from 3.3 V

The SPI Flash connects to the Zynq-7000 AP SoC supporting up to Quad-I/O SPI interface. This
requires connection to specific pins in MIO Bank 0/500, specifically MIO[1:6,8] as outlined in
the Zynq datasheet. Quad-SPI feedback mode is used, thus qspi_sclk_fb_out/MIO[8] is left to
freely toggle and is connected only to a 20K pull-up resistor to 3.3 V. This allows a QSPI clock
frequency greater than FQSPICLK2.

18 | ni.com | NI Digital System Development Board User Manual

DDR3 Memory

The DSDB includes two Micron MT41J128M16JT-125 or MT41K128M16JT-125 DDR3
memory components creating a single rank, 32-bit wide interface and a total of 512MiB of
capacity. The DDR3 is connected to the hard memory controller in the Processor Subsystem
(PS), as outlined in the Xilinx Zynq TRM (ug585).

The PS incorporates an AXI memory port interface, a DDR3 controller, the associated PHY, and
a dedicated I/O bank. Interface speeds of up to 525MHz/1050 Mbps are supported.

DDR3 uses 1.5 V SSTL15 single-ended and DIFF_SSTL15 differential signaling. Address and
control signals are routed in a tree topology with minimal stubs and series termination scheme.
Data signals follow a point-to-point scheme and benefit from on-die termination (ODT) on both
ends.

The target trace impedance is 40  (±10%) for single-ended signals, and 80  (±10%) for
differential. A feature called DCI (Digitally Controlled Impedance) is used to match the drive
strength and termination impedance of the PS pins to the trace impedance. On the memory side,
each chip calibrates its on-die termination and drive strength using a 240  resistor on the ZQ
pin.

Due to layout reasons, the two lower data byte groups (DQ[0-7], DQ[8-15]) were swapped. To
the same effect, the data bits inside byte groups were swapped as well. These changes are
transparent to the user. Appropriate Xilinx PCB guidelines were followed during design.

Both the memory chips and the PS DDR bank are powered from the 1.5 V supply. The mid-point
reference of 0.75 V is created with a simple resistor divider and is available to the Zynq as
external reference.

For proper operation it is essential that the PS memory controller is configured properly. Settings
range from memory timings to the board trace delays. For your convenience, the Zynq preset file
for the DSDB is provided on the Digilent DSDB Resource Center and can be used to
automatically configure the correct parameters.

For best DDR3 performance, DRAM training is enabled for write leveling, read gate, and read
data eye options in the PS Configuration Tool in Xilinx tools. Training is done dynamically by
the controller to account for board delays, process variations, and thermal drift. Optimum
starting values for the training process are the board delays (propagation delays) for certain
memory signals. process variations, and thermal drift. Optimum starting values for the training
process are the board delays (propagation delays) for certain memory signals.

Board delays are specified for each of the data byte groups in absolute terms and then relative to
CLK. These parameters are board-specific and were calculated from the PCB trace length
reports.

For more details on memory controller operation, refer to the Xilinx Zynq TRM (ug585).

NI Digital System Development Board User Manual | © National Instruments | 19