National Instruments VXI-MIO User Manual

VXI-MIO Series
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User Manual
Multifunction I/O Modules for VXIbus
Copyright 1996 National Instruments Corporation. All Rights Reserved.
August 1996 Edition
Part Number 321246A-01
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Important Information

Warranty

Copyright

Trademarks

The VXI-MIO Series boards are warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
The media on which you receive National Instruments software are warranted not to fail to execute programming instructions, due to defects in materials and workmanship, for a period of 90 days from date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period. National Instruments does not warrant that the operation of the software shall be uninterrupted or error free.
A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work. National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty.
National Instruments believes that the information in this manual is accurate. The document has been carefully reviewed for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition. The reader should consult National Instruments if errors are suspected. In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it.
XCEPT AS SPECIFIED HEREIN
E
SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
C
USTOMER’S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL
I
NSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA, PROFITS, USE OF PRODUCTS, OR INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY THEREOF
Instruments will apply regardless of the form of action, whether in contract or tort, including negligence. Any action against National Instruments must be brought within one year after the cause of action accrues. National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control. The warranty provided herein does not cover damages, defects, malfunctions, or service failures caused by owner’s failure to follow the National Instruments installation, operation, or maintenance instructions; owner’s modification of the product; owner’s abuse, misuse, or negligent acts; and power failure or surges, fire, flood, accident, actions of third parties, or other events outside reasonable control.
Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical, including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part, without the prior written consent of National Instruments Corporation.
LabVIEW, NI-DAQ, ComponentWorks, DAQ-STC, MANTIS, MITE, NI-PGIA, NI-VISA, NI-VXI,
, and VirtualBench are trademarks of National Instruments Corporation.
SCXI Product and company names listed are trademarks or trade names of their respective companies.
, N
ATIONAL INSTRUMENTS MAKES NO WARRANTIES, EXPRESS OR IMPLIED, AND
. N
ATIONAL INSTRUMENTS
. This limitation of the liability of National
.
WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS
National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the part of the user or application designer. Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel, and all traditional medical safeguards, equipment, and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used. National Instruments products are NOT intended to be a substitute for any form of established process, procedure, or equipment used to monitor or safeguard human health and safety in medical or clinical treatment.
About This Manual
Organization of This Manual ........................................................................................xi
Conventions Used in This Manual ................................................................................xii
National Instruments Documentation ...........................................................................xiii
Related Documentation .................................................................................................xiv
Customer Communication ............................................................................................xiv
Chapter 1 Introduction
About the VXI-MIO Series ...........................................................................................1-1
What You Need to Get Started ......................................................................................1-2
Software Programming Choices ...................................................................................1-2
National Instruments Application Software ...................................................1-2
NI-DAQ Driver Software ...............................................................................1-3
VXI
plug&play
Optional Equipment ......................................................................................................1-5
Custom Cabling .............................................................................................................1-6
Unpacking .....................................................................................................................1-6
Table
of
Contents
Instrument Drivers .................................................................1-4
Chapter 2 Configuration and Installation
Module Configuration ...................................................................................................2-1
VXIbus Logical Address ................................................................................2-1
SIMM Size ......................................................................................................2-5
Load USER/FACTORY Configuration ..........................................................2-7
Protect/Change Factory Configuration ...........................................................2-8
Hardware Installation ....................................................................................................2-8
Software Installation .....................................................................................................2-9
National Instruments Corporation v VXI-MIO Series User Manual
Table of Contents
Chapter 3 Hardware Overview
Analog Input ................................................................................................................. 3-3
Input Mode ..................................................................................................... 3-3
Input Polarity and Input Range ...................................................................... 3-4
Dither .............................................................................................................. 3-7
Multichannel Scanning Considerations .......................................................... 3-8
Analog Output .............................................................................................................. 3-10
Analog Output Reference Selection ............................................................... 3-10
Analog Output Polarity Selection .................................................................. 3-10
Analog Output Reglitch Selection ................................................................. 3-11
Analog Trigger ............................................................................................................. 3-11
Digital I/O ..................................................................................................................... 3-14
Timing Signal Routing ................................................................................................. 3-15
Programmable Function Inputs ...................................................................... 3-16
Module and Timebase .................................................................................... 3-16
VXIbus Triggers ............................................................................................. 3-17
Chapter 4 Signal Connections
I/O Connector ...............................................................................................................4-1
I/O Connector Signal Descriptions ................................................................ 4-3
Analog Input Signal Connections ................................................................................. 4-9
Types of Signal Sources ...............................................................................................4-11
Floating Signal Sources .................................................................................. 4-11
Ground-Referenced Signal Sources ............................................................... 4-11
Input Configurations ..................................................................................................... 4-12
Differential Connection Considerations (DIFF Input Configuration) ........... 4-14
Single-Ended Connection Considerations ...................................................... 4-18
Common-Mode Signal Rejection Considerations .......................................... 4-20
Analog Output Signal Connections .............................................................................. 4-20
Digital I/O Signal Connections ....................................................................................4-22
Considerations for Selecting Input Ranges ...................................... 3-6
Differential Connections for Ground-Referenced
Signal Sources ................................................................................4-15
Differential Connections for Nonreferenced or Floating
Signal Sources ................................................................................4-16
Single-Ended Connections for Floating Signal Sources
(RSE Configuration) ...................................................................... 4-19
Single-Ended Connections for Grounded Signal Sources
(NRSE Configuration) ................................................................... 4-19
VXI-MIO Series User Manual vi
National Instruments Corporation
Table of Contents
Power Connections ........................................................................................................4-23
Timing Connections ......................................................................................................4-23
Programmable Function Input Connections ...................................................4-24
Data Acquisition Timing Connections ...........................................................4-25
SCANCLK Signal ............................................................................4-26
EXTSTROBE* Signal ......................................................................4-26
TRIG1 Signal ...................................................................................4-27
TRIG2 Signal ...................................................................................4-28
STARTSCAN Signal .......................................................................4-30
CONVERT* Signal ..........................................................................4-32
AIGATE Signal ................................................................................4-33
SISOURCE Signal ...........................................................................4-34
Waveform Generation Timing Connections ...................................................4-34
WFTRIG Signal ...............................................................................4-36
UPDATE* Signal .............................................................................4-36
UISOURCE Signal ...........................................................................4-37
General-Purpose Timing Signal Connections ................................................4-38
GPCTR0_SOURCE Signal ..............................................................4-38
GPCTR0_GATE Signal ...................................................................4-39
GPCTR0_OUT Signal ......................................................................4-40
GPCTR0_UP_DOWN Signal ..........................................................4-40
GPCTR1_SOURCE Signal ..............................................................4-41
GPCTR1_GATE Signal ...................................................................4-41
GPCTR1_OUT Signal ......................................................................4-42
GPCTR1_UP_DOWN Signal ..........................................................4-43
FREQ_OUT Signal ..........................................................................4-44
Field Wiring Considerations .........................................................................................4-45
Chapter 5 Calibration
Loading Calibration Constants ......................................................................................5-1
Self-Calibration .............................................................................................................5-2
External Calibration ......................................................................................................5-2
Other Considerations .....................................................................................................5-3
National Instruments Corporation vii VXI-MIO Series User Manual
Table of Contents
Appendix A Specifications
VXI-MIO-64E-1 ........................................................................................................... A-1
VXI-MIO-64XE-10 ...................................................................................................... A-10
Appendix B Optional Cable Connector Descriptions
Appendix C Common Questions
Appendix D Customer Communication
Glossary
Index

Figures

Figure 1-1. The Relationship between the Programming Environment, Your
Instrument Driver, and Your VXI-DAQ Hardware .............................. 1-5
Figure 2-1. VXI-MIO-64E-1 Parts Locator Diagram ................................................ 2-3
Figure 2-2. VXI-MIO-64XE-10 Parts Locator Diagram ........................................... 2-4
Figure 2-3. VXI-MIO-64XE-10 Logical Address Selection ...................................... 2-5
Figure 2-4. SIMM Size Configuration ....................................................................... 2-6
Figure 2-5. Load User/Factory Configuration ........................................................... 2-8
Figure 2-6. Protect/Change Factory Configuration .................................................... 2-8
Figure 3-1. VXI-MIO Series Block Diagram ............................................................ 3-2
Figure 3-2. Dither ....................................................................................................... 3-8
Figure 3-3. Analog Trigger Block Diagram ............................................................... 3-12
Figure 3-4. Below-Low-Level Analog Triggering Mode .......................................... 3-12
Figure 3-5. Above-High-Level Analog Triggering Mode ......................................... 3-13
Figure 3-6. Inside-Region Analog Triggering Mode ................................................. 3-13
Figure 3-7. High-Hysteresis Analog Triggering Mode .............................................. 3-13
Figure 3-8. Low-Hysteresis Analog Triggering Mode .............................................. 3-14
Figure 3-9. CONVERT* Signal Routing ................................................................... 3-15
Figure 3-10. VXIbus Trigger Utilization .....................................................................3-17
VXI-MIO Series User Manual viii
National Instruments Corporation
Table of Contents
Figure 4-1. I/O Connector Pin Assignment for the VXI-MIO-64E-1 and
VXI-MIO-64XE-10 ................................................................................4-2
Figure 4-2. VXI-MIO Series PGIA ............................................................................4-10
Figure 4-3. Summary of Analog Input Connections ..................................................4-13
Figure 4-4. Differential Input Connections for Ground-Referenced Signals .............4-15
Figure 4-5. Differential Input Connections for Nonreferenced Signals .....................4-16
Figure 4-6. Single-Ended Input Connections for Nonreferenced or Floating
Signals.....................................................................................................4-19
Figure 4-7. Single-Ended Input Connections for Ground-Referenced Signal ............4-20
Figure 4-8. Analog Output Connections .....................................................................4-21
Figure 4-9. Digital I/O Connections ...........................................................................4-22
Figure 4-10. Timing I/O Connections ..........................................................................4-24
Figure 4-11. Typical Posttriggered Acquisition ...........................................................4-25
Figure 4-12. Typical Pretriggered Acquisition .............................................................4-26
Figure 4-13. SCANCLK Signal Timing .......................................................................4-26
Figure 4-14. EXTSTROBE* Signal Timing ................................................................4-27
Figure 4-15. TRIG1 Input Signal Timing .....................................................................4-28
Figure 4-16. TRIG1 Output Signal Timing ..................................................................4-28
Figure 4-17. TRIG2 Input Signal Timing .....................................................................4-29
Figure 4-18. TRIG2 Output Signal Timing ..................................................................4-29
Figure 4-19. STARTSCAN Input Signal Timing .........................................................4-30
Figure 4-20. STARTSCAN Output Signal Timing ......................................................4-31
Figure 4-21. CONVERT* Input Signal Timing ...........................................................4-32
Figure 4-22. CONVERT* Output Signal Timing .........................................................4-33
Figure 4-23. SISOURCE Signal Timing ......................................................................4-34
Figure 4-24. WFTRIG Input Signal Timing .................................................................4-35
Figure 4-25. WFTRIG Output Signal Timing ..............................................................4-35
Figure 4-26. UPDATE* Input Signal Timing ..............................................................4-37
Figure 4-27. UPDATE* Output Signal Timing ............................................................4-37
Figure 4-28. UISOURCE Signal Timing ......................................................................4-38
Figure 4-29. GPCTR0_SOURCE Signal Timing .........................................................4-39
Figure 4-30. GPCTR0_GATE Signal Timing in Edge-Detection Mode .....................4-40
Figure 4-31. GPCTR0_OUT Signal Timing ................................................................4-40
Figure 4-32. GPCTR1_SOURCE Signal Timing .........................................................4-41
Figure 4-33. GPCTR1_GATE Signal Timing in Edge-Detection Mode .....................4-42
Figure 4-34. GPCTR1_OUT Signal Timing ................................................................4-43
Figure 4-35. GPCTR Timing Summary .......................................................................4-43
Figure B-1. 68-Pin MIO Connector Pin Assignments ................................................B-2
Figure B-2. 68-Pin Extended Analog Input Connector Pin Assignments ...................B-3
National Instruments Corporation ix VXI-MIO Series User Manual
Table of Contents

Tables

Table 2-1. VXI-MIO Series DRAM Configuration .................................................. 2-6
Table 3-1. Available Input Configurations for the VXI-MIO Series ....................... 3-3
Table 3-2. Actual Range and Measurement Precision .............................................. 3-4
Table 3-3. Actual Range and Measurement Precision, VXI-MIO-64XE-10 ........... 3-6
Table 4-1. VXI-MIO-64E-1 I/O Signal Summary .................................................... 4-6
Table 4-2. VXI-MIO-64XE-10 I/O Signal Summary ............................................... 4-8
VXI-MIO Series User Manual x
National Instruments Corporation
This manual describes the electrical and mechanical aspects of each module in the VXI-MIO Series product line and contains information concerning their installation, operation, and programming. Unless otherwise noted, text applies to all modules in the VXI-MIO Series.
The VXI-MIO Series includes the following modules:
VXI-MIO-64E-1
VXI-MIO-64XE-10 The VXI-MIO Series modules are high-performance multifunction
analog, digital, and timing I/O modules for VXIbus.

Organization of This Manual

The
VXI-MIO Series User Manual
Chapter 1, lists what you need to get started, describes the optional software and optional equipment, and explains how to unpack your VXI-MIO Series module.
Chapter 2, configure and install your VXI-MIO Series module.
Chapter 3, hardware functions on your VXI-MIO Series module.
Chapter 4, Signal Connections output signal connections to your VXI-MIO Series module via the module I/O connector.
Chapter 5, your VXI-MIO Series module.
Appendix A, module in the VXI-MIO Series.
Appendix B, connectors on the optional cables for the VXI-MIO Series modules.
Introduction
Configuration and Installation
Hardware Overview
Calibration,
Specifications
Optional Cable Connector Descriptions
About
About
This
This
Manual
Manual
is organized as follows:
, describes the VXI-MIO Series modules,
, explains how to
, presents an overview of the
, describes how to make input and
discusses the calibration procedures for
, lists the specifications for each
, describes the
National Instruments Corporation xi VXI-MIO Series User Manual
About This Manual
Appendix C, questions and their answers relating to usage and special features of your VXI-MIO Series module.
Appendix D, to request help from National Instruments or to comment on our products.
The
The
Glossary
used in this manual, including acronyms, abbreviations, metric prefixes, mnemonics, and symbols.
Index
including the page where you can find the topic.
Common Questions
Customer Communication
contains an alphabetical list and description of terms
alphabetically lists topics covered in this manual,

Conventions Used in This Manual

The following conventions are used in this manual.
< > Angle brackets containing numbers separated by an ellipsis represent a
bold
bold italic
italic
NI-DAQ NI-DAQ refers to the NI-DAQ software for PC compatibles unless
SCXI SCXI stands for Signal Conditioning eXtensions for Instrumentation
The ♦ indicates that the text following it applies only to specific
VXI-MIO Series modules.
range of values associated with a bit, port, or signal name (for example, ACH<0..7> stands for ACH0 through ACH7).
Bold text denotes parameters. Bold italic text denotes a note, caution, or warning.
Italic text denotes emphasis on a specific module in the VXI-MIO Series or on other important information, a cross reference, or an introduction to a key concept.
otherwise noted.
and is a National Instruments product line designed to perform front-end signal conditioning for National Instruments plug-in DAQ boards.
, contains a list of commonly asked
, contains forms you can use
The
Glossary
mnemonics, symbols, and terms.
VXI-MIO Series User Manual xii
lists abbreviations, acronyms, metric prefixes,
National Instruments Corporation

National Instruments Documentation

The
VXI-MIO Series User Manual
for your VXI-DAQ system. You could have any of several types of manuals depending on the hardware and software in your system. Use the manuals you have as follows:
Getting Started with SCXI
manual you should read. It gives an overview of the SCXI system and contains the most commonly needed information for the modules, chassis, and software.
Your SCXI hardware user manuals—If you are using SCXI, read these manuals next for detailed information about signal connections and module configuration. They also explain in greater detail how the module works and contain application hints.
Your VXI-DAQ hardware user manuals—These manuals have detailed information about the VXI-DAQ hardware that plugs into or is connected to your system. Use these manuals for hardware installation and configuration instructions, specification information about your VXI-DAQ hardware, and application hints.
Software documentation—You may have both application software and driver software documentation. National Instruments application software includes ComponentWorks, LabVIEW, LabWindows/CVI, Measure, and VirtualBench. National Instruments driver software includes NI-DAQ and VXI instrument drivers. After you set up your hardware system, use either your application or driver software documentation to help you write your application. If you have a large and complicated system, it is worthwhile to look through the software documentation before you configure your hardware.
Accessory installation guides or manuals—If you are using accessory products, read the terminal block and cable assembly installation guides. They explain how to physically connect the relevant pieces of the system. Consult these guides when you are making your connections.
SCXI chassis manuals—If you are using SCXI, read these manuals for maintenance information on the chassis and installation instructions.
is one piece of the documentation set
—If you are using SCXI, this is the first
About This Manual
plug&play
National Instruments Corporation xiii VXI-MIO Series User Manual
About This Manual

Related Documentation

The following National Instruments document contains information you may find helpful:
Application Note 025,
Analog Signals

Customer Communication

National Instruments wants to receive your comments on our products and manuals. We are interested in the applications you develop with our products, and we want to help if you have problems with them. To make it easy for you to contact us, this manual contains comment and configuration forms for you to complete. These forms are in Appendix D,
Customer Communication
Field Wiring and Noise Considerations for
, at the end of this manual.
VXI-MIO Series User Manual xiv
National Instruments Corporation
Chapter
Introduction
This chapter describes the VXI-MIO Series modules, lists what you need to get started, describes the optional software and optional equipment, and explains how to unpack your VXI-MIO Series module.

About the VXI-MIO Series

Thank you for buying a National Instruments VXI-MIO Series module. The VXI-MIO Series modules are completely VXI compatible multifunction analog, digital, and timing I/O modules for VXIbus. This family of modules features 12-bit and 16-bit ADCs with 64 analog inputs, 12-bit and 16-bit DACs with voltage outputs, eight lines of TTL-compatible digital I/O, and two 24-bit counter/timers for timing I/O.
The VXI-MIO Series modules use the National Instruments DAQ-STC system timing controller for timer-related functions. The DAQ-STC consists of three timing groups that control analog input, analog output, and general-purpose counter/timer functions. These groups include a total of seven 24-bit and three 16-bit counters and a maximum timing resolution of 50 ns.
1
plug&play
-
A common problem with other VXI modules is that you cannot easily synchronize several measurement functions to a common trigger or timing event. The VXI-MIO Series modules solve this problem by using VXIbus triggers to synchronize measurements on several VXI-MIO Series modules.
You can interface the VXI-MIO Series modules to an SCXI signal conditioning and multiplexing system to acquire over 3,000 analog signals from thermocouples, RTDs, strain gauges, voltage sources, and current sources. You can also acquire or generate digital signals for communication and control.
Detailed specifications of the VXI-MIO Series modules are in Appendix A,
National Instruments Corporation 1-1 VXI-MIO Series User Manual
Specifications
.
Chapter 1 Introduction

What You Need to Get Started

To set up and use your VXI-MIO Series module, you will need the following:
One of the following modules:
VXI-MIO-64E-1 VXI-MIO-64XE-10
VXI-MIO Series User Manual
One or more of the following software packages and documentation:
ComponentWorks LabVIEW for Windows LabWindows/CVI Measure NI-DAQ for PC Compatibles VirtualBench VXI
plug&play
instrument driver
Your VXIbus system

Software Programming Choices

There are several options to choose from when programming your National Instruments VXI-DAQ hardware. You can use LabVIEW, LabWindows/CVI, Measure, ComponentWorks, VirtualBench, or other application development environments with either NI-DAQ or the VXI
plug&play
instrument drivers access the VXI-DAQ hardware through the VISA driver software.

National Instruments Application Software

ComponentWorks contains tools for data acquisition and instrument control built on NI-DAQ driver software. ComponentWorks provides a higher-level programming interface for building virtual instruments through standard OLE controls and DLLs. With ComponentWorks, you can use all of the configuration tools, resource management utilities, and interactive control utilities included with NI-DAQ.
VXI-MIO Series User Manual 1-2
instrument driver. Both NI-DAQ and the VXI
plug&play
National Instruments Corporation
Chapter 1 Introduction
LabVIEW features interactive graphics, a state-of-the-art user interface, and a powerful graphical programming language. The LabVIEW Data Acquisition VI Library, a series of VIs for using LabVIEW with National Instruments DAQ hardware, is included with LabVIEW. The LabVIEW Data Acquisition VI Library is functionally equivalent to the NI-DAQ software.
LabWindows/CVI features interactive graphics, a state-of-the-art user interface, and uses the ANSI standard C programming language. The LabWindows/CVI Data Acquisition Library, a series of functions for using LabWindows/CVI with National Instruments DAQ hardware, is included with the NI-DAQ software kit. The LabWindows/CVI Data Acquisition Library is functionally equivalent to the NI-DAQ software.
VirtualBench features VIs that combine DAQ products, software, and your computer to create a standalone instrument with the added benefit of the processing, display, and storage capabilities of your computer. VirtualBench instruments load and save waveform data to disk in the same forms that can be used in popular spreadsheet programs and word processors. VirtualBench features report generation and printing capabilities.
Using ComponentWorks, LabVIEW, LabWindows/CVI, or VirtualBench software will greatly reduce the development time for your data acquisition and control application.

NI-DAQ Driver Software

The NI-DAQ driver software is included at no charge with all National Instruments DAQ hardware. NI-DAQ is not packaged with signal conditioning or accessory products. NI-DAQ has an extensive library of functions that you can call from your application programming environment. These functions include routines for analog input (A/D conversion), buffered data acquisition (high-speed A/D conversion), analog output (D/A conversion), waveform generation (timed D/A conversion), digital I/O, counter/timer operations, SCXI, triggering, calibration, messaging, and acquiring data to extended memory.
NI-DAQ has both high-level DAQ I/O functions for maximum ease of use and low-level DAQ I/O functions for maximum flexibility and performance. Examples of high-level functions are streaming data to disk or acquiring a certain number of data points. An example of a low-level function is writing directly to registers on the DAQ device. NI-DAQ does not sacrifice the performance of National Instruments
National Instruments Corporation 1-3 VXI-MIO Series User Manual
Chapter 1 Introduction
VXI
plug&play
DAQ devices because it lets multiple devices operate at their peak performance.
NI-DAQ also internally addresses many of the complex issues between the computer and the DAQ hardware such as programming interrupts and DMA controllers. NI-DAQ maintains a consistent software interface between its different versions so that you can change platforms with minimal modifications to your code.
Instrument Drivers
National Instruments distributes VXI of charge. VXI NI-DAQ device driver and contain high-level software functions whose architecture is specified by the VXI VXI
plug&play
and ensure that drivers are designed and presented in a consistent fashion that facilitates ease of use. Refer to Figure 1-1 to see the relationship between your software components.
plug&play
standards increase interoperability with other vendors,
instrument drivers are one level above the
plug&play
plug&play
instrument drivers free
Systems Alliance. The
VXI-MIO Series User Manual 1-4
National Instruments Corporation
Chapter 1 Introduction
Figure 1-1.

Optional Equipment

National Instruments offers a variety of products to use with your VXI-MIO Series module, including cables, connector blocks, and other accessories, as follows:
Cables and cable assemblies, shielded and ribbon
Connector blocks
SCXI modules and accessories for isolating, amplifying, exciting, and multiplexing signals for relays and analog output. With SCXI you can condition and acquire up to 3072 channels.
Low channel count signal conditioning modules, boards, and accessories, including conditioning for strain gauges and RTDs, simultaneous sample and hold, and relays
LabVIEW or
LabWindows/CVI
VXI
plug&play
Instrument Driver
NI-DAQ Driver Software
VISA
VXI-DAQ Hardware
The Relationship between the Programming Environment, Your
Instrument Driver, and Your VXI-DAQ Hardware
Other Application
Development Environments
For more specific information about these products, refer to your National Instruments catalogue or call the office nearest you.
National Instruments Corporation 1-5 VXI-MIO Series User Manual
Chapter 1 Introduction

Custom Cabling

Mating connectors and a backshell kit for making custom 96-pin cables for your VXI-MIO Series module are available from National Instruments.
If you want to develop your own cable, however, the following guidelines may be useful:
For the analog input signals, shielded twisted-pair wires for each
You should route the analog lines separately from the digital lines.
When using a cable shield, use separate shields for the analog and

Unpacking

Your VXI-MIO Series module is shipped in an antistatic package to prevent electrostatic damage to the module. Electrostatic discharge can damage several components on the module. To avoid such damage in handling the module, take the following precautions:
Ground yourself via a grounding strap or by holding a grounded
Touch the antistatic package to a metal part of your VXIbus chassis
Remove the module from the package and inspect the module for
signal yields the best results, assuming that you use differential inputs. Tie the shield for each signal pair to the ground reference at the source.
digital halves of the cable. Failure to do so results in noise coupling into the analog signals from transient digital signals.
object.
before removing the module from the package.
loose components or any other sign of damage. Notify National Instruments if the module appears damaged in any way. install a damaged module into your VXIbus chassis.
Never
touch the exposed pins of connectors.
Do not
VXI-MIO Series User Manual 1-6
National Instruments Corporation
Configuration and
Chapter
Installation
This chapter explains how to configure and install your VXI-MIO Series module.

Module Configuration

The VXI-MIO Series modules are software-configurable, except for the VXIbus logical address. You must perform two types of configuration on the VXI-MIO Series modules—bus-related configuration and data acquisition-related configuration. Bus-related configuration includes setting the VXIbus logical address, VXIbus address space (
A32
), VXIbus interrupt levels, and amount of VXIbus address space required. Data acquisition-related configuration, explained in Chapter 3, polarity and range, analog output reference source, and other settings.

VXIbus Logical Address

Each module in a VXIbus system is assigned a unique number between 0 and 254. This 8-bit number, called the logical address, defines the base address for the VXIbus configuration registers located on the module. With unique logical addresses, each VXIbus module in the system is assigned 64 bytes of configuration space in the upper 16 KB of the A16 address space.
Hardware Overview
2
A24
versus
, includes such settings as analog input
Logical address 0 is reserved for the Resource Manager in the VXIbus system. Because the VXI-MIO Series modules cannot act as a Resource Manager, do not configure the VXI-MIO Series modules with a logical address of 0. The factory-default logical address for the VXI-MIO-64E-1 is 3 and for the VXI-MIO-64XE-10 is 2.
Some VXIbus modules have dynamically configurable logical addresses. These modules have an initial logical address of hex FF or decimal 255, which indicates that they can be dynamically configured.
National Instruments Corporation 2-1 VXI-MIO Series User Manual
Chapter 2 Configuration and Installation
Your VXI-MIO Series module does not support dynamic configuration of its logical address.
Ensure that no other statically configurable VXIbus modules have the same logical address as the VXI-MIO Series module. If they do, change the logical address setting of either the VXI-MIO Series module or the other module so that every module in the system has a different associated logical address.
To change the logical address of the VXI-MIO Series modules, modify the setting of the 8-bit DIP switch labeled LOGICAL ADDRESS SWITCH (U3 for the VXI-MIO-64E-1 and U73 for the VXI-MIO-64XE-10). The down position of the DIP switch corresponds to a logic value of 0 and the up position corresponds to a logic value of 1.
See Figures 2-1 and 2-2 for the VXI-MIO Series parts locator diagrams.
VXI-MIO Series User Manual 2-2
National Instruments Corporation
Chapter 2 Configuration and Installation
4
3 2
5
1 1
6 7 8
9
1011
1 DRAM 2 Product Name 3 Assembly Number
National Instruments Corporation 2-3 VXI-MIO Series User Manual
4P3
5 Serial Number
6S1
Figure 2-1.
7S2 8S3 9 Logical Address Switch
VXI-MIO-64E-1 Parts Locator Diagram
10 P1 11 P2
Chapter 2 Configuration and Installation
3 2
1 1
4
5 6
7 8
1 DRAM 2 Product Name 3 Assembly Number
4P3
5S1
6S2
Figure 2-2.
Figure 2-3 shows the VXI-MIO-64XE-10 switch settings for logical address 2 and 192.
VXI-MIO Series User Manual 2-4
10 911
7S3 8 Logical Address Switch (U73) 9 Serial Number
VXI-MIO-64XE-10 Block Diagram
National Instruments Corporation
10 P1 11 P2
Chapter 2 Configuration and Installation
Logical Address
Switch
Push up for logic 1
Push down for logic 0
P1 Connector U73 VXI-MIO-64XE-10 Module
a. Switch Set to Logical Address 2 (Default)
Push up for logic 1
Push down for logic 0
12345678
LSB MSB
Logical Address
Switch
12345678
MSBLSB
P1 Connector U73 VXI-MIO-64XE-10 Module
b. Switch Set to Logical Address 192
Figure 2-3.
VXI-MIO-64XE-10 Logical Address Selection

SIMM Size

Each VXI-MIO module can accommodate up to two 1.35 in. DRAM SIMMs. Table 2-1 lists the SIMMS you can use. You can use 32-bit or 36-bit SIMMS since DRAM parity is not required. Because the VXI-MIO module supports only one organization at a time, all SIMMs installed must be of the same type. Use bank 0 first when installing the SIMMs, so that you can install up to 64 MB. The VXI-MIO module supports DRAM speeds of 80 ns or faster.
Use switch S3 to select the size of each SIMM. The SIMM sockets are accessible only by removing the component right side cover, but S3 is
National Instruments Corporation 2-5 VXI-MIO Series User Manual
Chapter 2 Configuration and Installation
accessible with the cover on. To access the SIMM sockets, perform the following steps:
1. Remove the four screws on the top, the four screws on the bottom,
and the three screws on the right-side cover of the metal enclosure.
2. If the SIMMs are 4 MB x 32 bit or larger, set S3 as shown in
Figure 2-4a.
3. For SIMMs smaller than 4 MB x 32 bit, set S3 as shown in
Figure 2-4b.
SIMM Size
(Factory Default)
SIMM Size
(Factory Default)
S3 S3
Bank 0
256 KB x 32 bit or 256 KB x 36 bit
256 KB x 32 bit or 256 KB x 36 bit
512 KB x 32 bit or 512 KB x 36 bit
512 KB x 32 bit or 512 KB x 36 bit
a. 4 MB X 32 bit or larger
Figure 2-4.
b. Smaller than 4 MB X 32 bit
SIMM Size Configuration
Refer to Table 2-1 to properly adjust the switch (ON or OFF) for all supported DRAM configurations. Many of the DRAM options are available from National Instruments.
Table 2-1.
Bank 1 Total
VXI-MIO Series DRAM Configuration
National
DRAM
Instruments Option
Switch Setting
of S3
0 — — 1 MB ON
256 KB x 32 bit or
2 MB ON
256 KB x 36 bit
2 MB ON
512 KB x 32 bit or
4 MB ON
512 KB x 36 bit
VXI-MIO Series User Manual 2-6
National Instruments Corporation
Chapter 2 Configuration and Installation
Bank 0
1 MB x 32 bit or 1 MB x 36 bit
1 MB x 32 bit or 1 MB x 36 bit
2 MB x 32 bit or 2 MB x 36 bit
2 MB x 32 bit or 2 MB x 36 bit
4 MB x 32 bit or 4 MB x 36 bit
4 MB x 32 bit or 4 MB x 36 bit
8 MB x 32 bit or 8 MB x 36 bit
Table 2-1.
VXI-MIO Series DRAM Configuration (Continued)
Bank 1 Total
4 MB Yes ON
1 MB x 32 bit or 1 MB x 36 bit
8 MB Yes ON
2 MB x 32 bit or 2 MB x 36 bit
16 MB Yes OFF
4 MB x 32 bit or 4 MB x 36 bit
32 MB Yes OFF
DRAM
National
Instruments Option
Switch Setting
of S3
8 MB ON
16 MB ON
32 MB OFF
8 MB x 32 bit or 8 MB x 36 bit
8 MB x 32 bit or 8 MB x 36 bit
64 MB Yes OFF

Load USER/FACTORY Configuration

The VXI-MIO module has an onboard EEPROM, which stores default register values that are loaded at power-on. The EEPROM is divided into two halves—a factory-configuration half, and a user-configuration half. Both halves were factory configured with the same configuration values so you can modify the user-configurable half, while the factory­configured half stores a back-up of the factory settings.
Use switch S2 to control the operation of the EEPROM. The switch causes the VXI-MIO module to boot off the factory-configured half instead of the user-modified settings. This is useful in the event that the user-configured half of the EEPROM becomes corrupted in such a way that the VXI-MIO module boots to an unusable state. Refer to Figure 2-5 for configuration settings.
National Instruments Corporation 2-7 VXI-MIO Series User Manual
Chapter 2 Configuration and Installation
Load User
Configuration
Figure 2-5.

Protect/Change Factory Configuration

Use switch S1 to change the factory-default configuration settings by permitting writes to the factory settings section of the EEPROM. This switch serves as a safety measure and should not be needed under normal circumstances. When this switch is off (its default setting) the factory configuration of the EEPROM is protected, so any writes to the factory area will be ignored. Refer to Figure 2-6 for configuration settings.
Protect Factory
Configuration
Load Factory
Configuration
S2 S2
Load User/Factory Configuration
Change Factory
Configuration
S1 S1
Figure 2-6.

Hardware Installation

This section contains general installation instructions for the VXI-MIO Series modules. Consult your VXIbus mainframe user manual or technical reference manual for specific instructions and warnings.
1. Plug in your mainframe before installing your VXI module. The
power cord grounds the mainframe and protects it from electrical damage while you install the module. mainframe.
Warning:
VXI-MIO Series User Manual 2-8
To protect yourself and your mainframe from electrical hazards, DO turn the mainframe on until you are finished installing your VXI-MIO Series module.
Protect/Change Factory Configuration
Do not
turn on the
National Instruments Corporation
NOT
Chapter 2 Configuration and Installation
2. Remove or open any doors or covers blocking access to the
mainframe slots.
3. If you are installing your VXI-DAQ module into a D-size
mainframe, first install an appropriate support for C-size modules in D-size mainframes.
4. Insert the VXI-DAQ module in the slot you have selected:
a. Align the top and bottom of the module with the card-edge
guides inside the mainframe.
b. Slowly push the VXI-DAQ module straight into the slot until
its plug connectors are resting on the backplane receptacle connectors.
c. Using evenly distributed pressure, slowly press the VXI-DAQ
module straight in until it seats in the expansion slot.
d. Make sure the front panel of the VXI-DAQ module is even
with the front panel of the mainframe.
5. Tighten the retaining screws on the top and bottom edges of the
front panel.
6. Replace or close any doors or covers to the mainframe.

Software Installation

Regardless of your programming methodology, proper operation of
your VXI-MIO module depends on the correct installation of VISA on your VXIbus controller.
If VISA is not installed, you must get this information from your
VXIbus controller manufacturer. If you have a National Instruments VXIbus controller, contact our sales department for information on obtaining the NI-VISA software at no charge.
If you are using NI-DAQ, refer to your release notes. Find the
installation section for your operating system and follow the instructions given there.
If you are using LabVIEW, refer to your LabVIEW release notes to
install your application software. After you have installed LabVIEW, refer to the NI-DAQ release notes and follow the instructions given there for your operating system and LabVIEW.
National Instruments Corporation 2-9 VXI-MIO Series User Manual
Chapter 2 Configuration and Installation
If you are using LabWindows/CVI, refer to your LabWindows/CVI
release notes to install your application software. After you have installed LabWindows/CVI, refer to the NI-DAQ release notes and follow the instructions given there for your operating system and LabWindows/CVI.
If you are using ComponentWorks, Measure, or VirtualBench
application software, refer to your documentation for installation instructions.
VXI-MIO Series User Manual 2-10
National Instruments Corporation
Chapter
Hardware Overview
This chapter presents an overview of the hardware functions on your
VXI-MIO Series module.
Figure 3-1 shows the block diagram for the VXI-MIO Series modules.
3
National Instruments Corporation 3-1 VXI-MIO Series User Manual
Chapter 3 Hardware Overview
Address Data Control Signals
VXI
Transceivers
Interrupts
Arbitration Signals
Utility Signals
P1 MANTIS
VXI Bus
N.V. RAM
VXI Triggers
MODIO Lines
P2 MANTIS
Logical
Switch
Address
ECL Triggers
CLK10 +/-
ECL Triggers (TTL Level)
CLK10
Circuitry
and Clock
VXI Trigger
VXI Local Bus
Voltage
Analog Bus
IO Data Lines
AI Control
Memory
Configuration
IO Control
DMA
Interface
Control
EEPROM
Input
Analog
Control
Circuit
Analog
Trigger
DACS
Trigger Level
IO Address Lines
Bus
EPF8282
DAQ-STC
DMA/
Interrupt
Request
Analog Input
Timing/Control
Trigger
External Trigger
Amplifier
Switches
0-3
Banks
ACH 16:31
EEPROM
ACH 0:15
IO Control
IO Address Lines
IO Control, IRQ, and DMA Lines
IO Data Lines
AD Control
Bank
Select
VXI
Port
MITE
I/O Port
MXI
Port
ADC
FIFO
Ref
Buffer
DACs
Calibration
REF
Cal/Aux
2
3
+
Analog
ACH 48:63
A/D
Converter
Programmable
Gain
Selection
Mux Mode
Muxes
ACH 32:47
IO Data Lines
Interface
Configuration
Interface
EPROM
Interface
Analog
Output Control
Bus
Interface
DAQ - STC
Counter/
Timing I/O
Timing
IO Control
IO Address Lines
Config
EPROM
Interface
RTSI Bus
Analog Output
Timing/Control
Digital I/O
Digital I/O (8)
IO Data LinesIO Data Lines
RITSI Bus
RITSI Bus
Optional
AD Control
DRAM Control Signals
DRAM
Circuitry
IO Data Lines
DAC
FIFOS
DAC0
Calibration
DAC1
DACS
VXI Local Bus
Signal
Conditioning
Control Circuitry
I/O Connector
Figure 3-1.
VXI-MIO Series User Manual 3-2
VXI-MIO Series Block Diagram
National Instruments Corporation

Analog Input

Input Mode

Chapter 3 Hardware Overview
The analog input section of each VXI-MIO Series module is software
configurable. You can select different analog input configurations through application software designed to control the VXI-MIO Series modules. The following sections describe in detail each of the analog input categories.
The VXI-MIO Series modules have three different input modes—
nonreferenced single-ended (NRSE) input, referenced single-ended (RSE) input, and differential (DIFF) input. The single-ended input configurations use up to 64 channels. The DIFF input configuration uses up to 32 channels. Input modes are programmed on a per channel basis for multimode scanning. For example, you can configure the circuitry to scan 48 channels—16 differentially-configured channels and 32 single-ended channels. Table 3-1 describes the three input configurations.
Table 3-1.
Configuration
DIFF
RSE A channel configured in RSE mode uses one analog
NRSE A channel configured in NRSE mode uses one
Available Input Configurations for the VXI-MIO Series
Description
A channel configured in DIFF mode uses two analog input channel lines. One line connects to the positive input of the module programmable gain instrumentation amplifier (PGIA), and the other connects to the negative input of the PGIA.
input channel line, which connects to the positive input of the PGIA. The negative input of the PGIA is internally tied to analog input ground (AIGND).
analog input channel line, which connects to the positive input of the PGIA. The negative input of the PGIA connects to the analog input sense (AISENSE) input.
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Chapter 3 Hardware Overview
For more information about the three types of input configuration, refer
to the
Analog Input Signal Connections
Connections
, which contains diagrams showing the signal paths for the
three configurations.

Input Polarity and Input Range

VXI-MIO-64E-1
This module has two input polarities—unipolar and bipolar. The VXI-MIO-64E-1 has a unipolar input range of 10 V (0 to 10 V) and a bipolar input range of 10 V (±5 V). You can program polarity and range settings on a per channel basis so that you can configure each input channel uniquely.
The software-programmable gain on this module increases its overall flexibility by matching the input signal ranges to those that the ADC can accommodate. The VXI-MIO-64E-1 has gains of 0.5, 1, 2, 5, 10, 20, 50, and 100 and is suited for a wide variety of signal levels. With the proper gain setting, you can use the full resolution of the ADC to measure the input signal. Table 3-2 shows the overall input range and precision according to the configuration and gain used.
section in Chapter 4,
Signal
Table 3-2.
Range
Configuration
0 to +10 V
VXI-MIO Series User Manual 3-4
Actual Range and Measurement Precision
Gain Actual Input Range Precision
1.0
2.0
5.0
10.0
20.0
50.0
100.0
0 to +10 V
0 to +5 V 0 to +2 V
0 to +1 V 0 to +500 mV 0 to +200 mV 0 to +100 mV
National Instruments Corporation
2.44 mV
1.22 mV
488.28 µV
244.14 µV
122.07 µV
48.83 µV
24.41 µV
1
Chapter 3 Hardware Overview
Table 3-2.
Range
Actual Range and Measurement Precision (Continued)
Gain Actual Input Range Precision
Configuration
-5 to +5 V 0.5
1.0
2.0
5.0
10.0
20.0
50.0
100.0
1
The value of 1 LSB of the 12-bit ADC; that is, the voltage
-10 to +10 V
-5 to +5 V
-2.5 to +2.5 V
-1 to +1 V
-500 to +500 mV
-250 to +250 mV
-100 to +100 mV
-50 to +50 mV
4.88 mV
2.44 mV
1.22 mV
488.28 µV
244.14 µV
122.07 µV
48.83 µV
24.41 µV
increment corresponding to a change of one count in the ADC 12-bit count.
Note:
VXI-MIO-64XE-10
See Appendix A ratings
.
, Specifications,
for absolute maximum
This module has two input polarities—unipolar and bipolar. The VXI-MIO-64XE-10 has a unipolar input range of 10 V (0 to 10 V) and a bipolar input range of 20 V (±10 V). You can program polarity and range settings on a per channel basis so that you can configure each input channel uniquely.
1
Note:
You can calibrate your VXI-MIO-64XE-10 analog input circuitry for either a unipolar or bipolar polarity. If you mix unipolar and bipolar channels in your scan list and you are using NI-DAQ, then NI-DAQ will load the calibration constants appropriate to the polarity for which analog input channel 0 is configured.
The software-programmable gain on this module increases its overall flexibility by matching the input signal ranges to those that the ADC can accommodate. The VXI-MIO-64XE-10 has gains of 1, 2, 5, 10, 20, 50, and 100. These gains are suited for a wide variety of signal levels. With the proper gain setting, you can use the full resolution of the ADC to measure the input signal. Table 3-3 shows
National Instruments Corporation 3-5 VXI-MIO Series User Manual
Chapter 3 Hardware Overview
the overall input range and precision according to the configuration and gain used.
Table 3-3.
Range
Actual Range and Measurement Precision, VXI-MIO-64XE-10
Gain Actual Input Range Precision
Configuration
0 to +10 V
1.0
2.0
5.0
10.0
20.0
50.0
100.0
-10 to +10 V 1.0
2.0
5.0
10.0
20.0
50.0
100.0
1
The value of 1 LSB of the 12-bit ADC; that is, the voltage
0 to +10 V
0 to +5 V
0 to +2 V
0 to +1 V 0 to +500 mV 0 to +200 mV
0 to 100 mV
-10 to +10 V
-5 to +5 V
-2 to +2 V
-1 to +1 V
-500 to +500 mV
-200 to +200 mV
-100 to +100 mV
152.59 µV
76.29 µV
30.52 µV
15.26 µV
7.63µV
3.05 µV
1.53 µV
305.18 µV
152.59 µV
61.04 µV
30.52 µV
15.26 µV
6.10 µV
3.05 µV
increment corresponding to a change of one count in the ADC 12-bit count.
Note:
See Appendix A ratings.
, Specifications,
for absolute maximum
1
Considerations for Selecting Input Ranges
Which input polarity and range you select depends on the expected range of the incoming signal. A large input range can accommodate a large signal variation but reduces the voltage resolution. Choosing a smaller input range improves the voltage resolution but may result in the input signal going out of range. For best results, you should match the input range as closely as possible to the expected range of the input signal. For example, if you are certain the input signal will not be negative (below 0 V), unipolar input polarity is best. However, if the signal is negative or equal to zero, using unipolar input polarity will yield inaccurate readings.
VXI-MIO Series User Manual 3-6
National Instruments Corporation

Dither

Chapter 3 Hardware Overview
When you enable dither, you add approximately 0.5 LSB rms of white Gaussian noise to the signal to be converted by the ADC. This addition is useful for applications involving averaging to increase the resolution of your VXI-MIO Series module, as in calibration or spectral analysis. In such applications, noise modulation is decreased and differential linearity is improved by the addition of the dither. When taking DC measurements, such as when checking the module calibration, you should enable dither and average about 1,000 points to take a single reading. This process removes the effects of quantization and reduces measurement noise, resulting in improved resolution. For high-speed applications not involving averaging or spectral analysis, you may want to disable the dither to reduce noise. You enable and disable the dither circuitry through software.
Figure 3-2 illustrates the effect of dither on signal acquisition. Figure 3-2a shows a small (±4 LSB) sine wave acquired with dither off. The quantization of the ADC is clearly visible. Figure 3-2b shows what happens when 50 such acquisitions are averaged together; quantization is still plainly visible. In Figure 3-2c, the sine wave is acquired with dither on. There is a considerable amount of noise visible. But averaging about 50 such acquisitions, as shown in Figure 3-2d, eliminates both the added noise and the effects of quantization. Dither has the effect of forcing quantization noise to become a zero-mean random variable rather than a deterministic function of the input signal.
National Instruments Corporation 3-7 VXI-MIO Series User Manual
Chapter 3 Hardware Overview
LSBs
LSBs
6.0
6.0
4.0
4.0
2.0
2.0
0.0
0.0
-2.0
-2.0
-4.0
-4.0
-6.0
-6.0 100 200 300 4000 500
100 200 300 4000 500
a. Dither disabled; no averaging b. Dither disabled; average of 50 acquisitions
LSBs
LSBs
6.0
6.0
4.0
4.0
2.0
2.0
0.0
0.0
-2.0
-2.0
-4.0
-4.0
-6.0
-6.0
100 200 300 4000 500
100 200 300 4000 500
c. Dither enabled; no averaging
LSBs
LSBs
6.0
6.0
4.0
4.0
2.0
2.0
0.0
0.0
-2.0
-2.0
-4.0
-4.0
-6.0
-6.0
LSBs
LSBs
6.0
6.0
4.0
4.0
2.0
2.0
0.0
0.0
-2.0
-2.0
-4.0
-4.0
-6.0
-6.0
100 200 300 4000 500
100 200 300 4000 500
100 200 300 4000 500
100 200 300 4000 500
d. Dither enabled; average of 50 acquisitions
You cannot disable dither on the VXI-MIO-64XE-10. This is because the ADC resolution is so fine that the ADC and the PGIA inherently produce almost 0.5 LSB rms of noise. This is equivalent to having a dither circuit that is always enabled.

Multichannel Scanning Considerations

All of the VXI-MIO Series modules can scan multiple channels at the same maximum rate as their single-channel rate; however, you should pay careful attention to the settling times for each of the modules. Refer to Appendix A, for each of the VXI-MIO Series modules.
When scanning among channels at various gains, the settling times may increase. When the PGIA switches to a higher gain, the signal on the previous channel may be well outside the new, smaller range. For instance, suppose a 4 V signal is connected to channel 0 and a 1 mV
VXI-MIO Series User Manual 3-8
Specifications
Figure 3-2.
Dither
, for a complete listing of settling times
National Instruments Corporation
Chapter 3 Hardware Overview
signal is connected to channel 1, and suppose the PGIA is programmed to apply a gain of one to channel 0 and a gain of 100 to channel 1. When the multiplexer switches to channel 1 and the PGIA switches to a gain of 100, the new full-scale range is 100 mV (if the ADC is in unipolar mode).
The approximately 4 V step from 4 V to 1 mV is 4,000% of the new full-scale range. For a 12-bit module to settle within 0.012% (120 ppm or 1/2 LSB) of the 100 mV full-scale range on channel 1, the input circuitry has to settle to within 0.0003% (3 ppm or 1/80 LSB) of the 4 V step. It may take as long as 100 µs for the circuitry to settle to this accuracy. For a 16-bit module to settle within 0.0015% (15 ppm or 1 LSB) of the 100 mV full-scale range on channel 1, the input circuitry has to settle within 0.00004% (0.4 ppm or 1/400 LSB) of the 4 V step. It may take as long as 200 µs for the circuitry to settle to this accuracy. In general, this extra settling time is not needed when the PGIA is switching to a lower gain.
Settling times can also increase when scanning high-impedance signals due to a phenomenon called
charge injection
, where the analog input multiplexer injects a small amount of charge into each signal source when that source is selected. If the impedance of the source is not low enough, the effect of the charge—a voltage error—will not have decayed by the time the ADC samples the signal. For this reason, you should keep source impedances under 1 kΩ to perform high-speed scanning.
Multichannel scanning is not recommended unless sampling rates are low enough or it is necessary to sample several signals as near to simultaneously as possible. Single-channel scanning yields more accurate settling times. The data is much more accurate and channel-to-channel independent if you acquire data from each channel independently (for example, 100 points from channel 0, then 100 points from channel 1, then 100 points from channel 2, and so on).
National Instruments Corporation 3-9 VXI-MIO Series User Manual
Chapter 3 Hardware Overview

Analog Output

VXI-MIO-64E-1
This module supplies two channels of analog output voltage at the I/O connector. The reference and range for the analog output circuitry is software-selectable. The reference can be either internal or external, whereas the range can be either bipolar or unipolar.
VXI-MIO-64XE-10
This module supplies two channels of analog output voltage at the I/O connector. The range is bipolar or unipolar.

Analog Output Reference Selection

VXI-MIO-64E-1
You can connect each D/A converter (DAC) to this module’s internal reference of 10 V or to the external reference signal connected to the external reference (EXTREF) pin on the I/O connector. This signal applied to EXTREF should be between -10 and +10 V. You do not need to configure both channels for the same mode.

Analog Output Polarity Selection

Selecting a bipolar range for a particular DAC means that any data written to that DAC will be interpreted as two’s complement format. In two’s complement mode, data values written to the analog output channel can be either positive or negative. If you select unipolar range, data is interpreted in straight binary format. In straight binary mode, data values written to the analog output channel range must be positive.
VXI-MIO-64E-1
You can configure each analog output channel for either unipolar or bipolar output. A unipolar configuration has a range of 0 to V at the analog output. A bipolar configuration has a range of -V +V
at the analog output. V
ref
the DACs in the analog output circuitry and can be either the +10 V onboard reference or an externally supplied reference between -10 and +10 V. You do not need to configure both channels for the same range.
VXI-MIO Series User Manual 3-10
is the voltage reference used by
ref
National Instruments Corporation
ref
ref
to
VXI-MIO-64XE-10
You can configure each analog output channel for either unipolar or bipolar output. A unipolar configuration has a range of 0 to 10 V at the analog output. A bipolar configuration has a range of -10 to +10 V at the analog output. You do not need to configure both channels for the same range.

Analog Output Reglitch Selection

VXI-MIO-64E-1
In normal operation, a DAC output will glitch whenever it is updated with a new value. The glitch energy differs from code to code and appears as distortion in the frequency spectrum. Each analog output of this module contains a reglitch circuit that generates uniform glitch energy at every code rather than large glitches at the major code transitions. This uniform glitch energy appears as a multiple of the update rate in the frequency spectrum. Notice that this reglitch circuit only makes them more uniform in size. Reglitching is normally disabled at startup and can be independently enabled for each channel through software.
VXI-MIO-64XE-10
This module does not require reglitch selection.
does not
Chapter 3 Hardware Overview
eliminate the glitches; it

Analog Trigger

In addition to supporting internal software triggering and external digital triggering to initiate a data acquisition sequence, the VXI-MIO-64E-1 and VXI-MIO-64XE-10 also support analog triggering. You can configure the analog trigger circuitry to accept either a direct analog input from the PFI0/TRIG1 pin on the I/O connector or a postgain signal from the output of the PGIA, as shown in Figure 3-3. The trigger-level range for the direct analog channel is
±
10 V in 78 mV steps for the VXI-MIO-64E-1, and ±10 V in 4.9 mV steps for theVXI-MIO-64XE-10. The range for the post-PGIA trigger selection is simply the full-scale range of the selected channel, and the resolution is that range divided by 256 for the VXI-MIO-64E-1, and divided by 4,096 for the VXI-MIO-64XE-10.
National Instruments Corporation 3-11 VXI-MIO Series User Manual
Chapter 3 Hardware Overview
Note:
The PFI0/TRIG1 pin is a high-impedance input. Therefore, it is susceptible to cross-talk from adjacent pins, which can result in false triggering when the pin is left unconnected. To avoid false triggering, make sure this pin is connected to a low-impedance signal source (less than 10 kΩ source impedance) if you plan to enable this input via software.
Analog Input Channels
PFI0/TRIG1
+
PGIA
-
Figure 3-3.
ADC
Analog
Mux
Analog Trigger Block Diagram
Trigger Circuit
DAQ-STC
There are five analog triggering modes available, as shown in
Figures 3-4 through 3-8. You can set
lowValue
and
highValue
independently in software.
In below-low-level analog triggering mode, the trigger is generated
when the signal value is less than
lowValue
Trigger
Figure 3-4.
In above-high-level analog triggering mode, the trigger is generated
when the signal value is greater than
VXI-MIO Series User Manual 3-12
lowValue. HighValue
Below-Low-Level Analog Triggering Mode
is unused.
highValue. LowValue
National Instruments Corporation
is unused.
highValue
Trigger
Chapter 3 Hardware Overview
Figure 3-5.
Above-High-Level Analog Triggering Mode
In inside-region analog triggering mode, the trigger is generated when
the signal value is between the
highValue
lowValue
Trigger
Figure 3-6.
lowValue
and the
highValue.
Inside-Region Analog Triggering Mode
In high-hysteresis analog triggering mode, the trigger is generated
when the signal value is greater than highValue, with the hysteresis specified by lowValue.
highValue
lowValue
Trigger

Figure 3-7. High-Hysteresis Analog Triggering Mode

National Instruments Corporation 3-13 VXI-MIO Series User Manual
Chapter 3 Hardware Overview
In low-hysteresis analog triggering mode, the trigger is generated when
the signal value is less than lowValue, with the hysteresis specified by
highValue.
highValue
lowValue
Trigger

Figure 3-8. Low-Hysteresis Analog Triggering Mode

The analog trigger circuit generates an internal digital trigger based on the analog input signal and the user-defined trigger levels. This digital trigger can be used by any of the timing sections of the DAQ-STC, including the analog input, analog output, and general-purpose counter/timer sections. For example, the analog input section can be configured to acquire n scans after the analog input signal crosses a specific threshold. As another example, the analog output section can be configured to update its outputs whenever the analog input signal crosses a specific threshold.

Digital I/O

The VXI-MIO Series modules contain eight lines of digital I/O for general-purpose use. You can individually configure each line through software for either input or output. At system startup and reset, the digital I/O ports are all high impedance.
The hardware up/down control for general-purpose counters 0 and 1 are connected onboard to DIO6 and DIO7, respectively. Thus, you can use DIO6 and DIO7 to control the general-purpose counters. The up/down control signals are input only and do not affect the operation of the DIO lines.
VXI-MIO Series User Manual 3-14
National Instruments Corporation

Timing Signal Routing

The DAQ-STC provides a very flexible interface for connecting timing signals to other modules or external circuitry. Your VXI-MIO Series module uses the VXIbus trigger for interconnecting timing signals between modules and the Programmable Function Input (PFI) pins on the I/O connector for connecting to external circuitry. These connections are designed to enable the VXI-MIO Series module to both control and be controlled by other modules and circuits.
There are a total of 13 timing signals internal to the DAQ-STC that can be controlled by an external source. These timing signals can also be controlled by signals generated internally to the DAQ-STC, and these selections are fully software-configurable. For example, the signal routing multiplexer for controlling the CONVERT* signal is shown in Figure 3-9.
VXI TTL Trigger <0..4>
VXI ECL Trigger <0..1>
Chapter 3 Hardware Overview
CONVERT*
PFI<0..9>
Sample Interval Counter TC
GPCTR0_OUT

Figure 3-9. CONVERT* Signal Routing

National Instruments Corporation 3-15 VXI-MIO Series User Manual
Chapter 3 Hardware Overview
This figure shows that CONVERT* can be generated from a number of sources, including the external signals VXI TTL Trig<0..4>, VXI ECL Trig<0..1>, and PFI<0..9>, and the internal signals Sample Interval Counter TC and GPCTR0_OUT.
Many of these timing signals are also available as outputs on the VXIbus trigger, as indicated in the VXIbus Triggers section later in this chapter, and on the PFI pins, as indicated in Chapter 4, Signal Connections.

Programmable Function Inputs

The 10 PFIs are connected to the signal routing multiplexer for each timing signal, and software can select one of the PFIs as the external source for a given timing signal. It is important to note that any of the PFIs can be used as an input by any of the timing signals and that multiple timing signals can use the same PFI simultaneously. This flexible routing scheme reduces the need to change physical connections to the I/O connector for different applications.
You can also individually enable each of the PFI pins to output a specific internal timing signal. For example, if you need the UPDATE* signal as an output on the I/O connector, your software can turn on the output driver for the PFI5/UPDATE* pin.

Module and Timebase

Many functions that the VXI-MIO Series modules perform require a frequency timebase to generate the necessary timing signals for controlling A/D conversions, DAC updates, or general-purpose signals at the I/O connector.
A VXI-MIO Series module can use either its internal 20 MHz timebase, which is phase-locked to CLK10 on the VXIbus, or a timebase received over a VXIbus trigger line. In addition, if you configure the module to use the internal timebase, you can also program the module to drive its internal timebase over the VXIbus trigger line to another module that is programmed to receive this timebase signal. This clock source, whether local or from the VXIbus trigger line, is used directly by the module as the primary frequency source. The default configuration at startup is to use the internal timebase without driving the VXIbus trigger line timebase signal. This timebase is software-selectable.
VXI-MIO Series User Manual 3-16
National Instruments Corporation

VXIbus Triggers

Chapter 3 Hardware Overview
The VXI-MIO Series modules can use up to seven of the 10 VXIbus trigger lines to coordinate sampling and/or triggering across multiple modules.
When using NI-DAQ software, the VXIbus trigger lines are functionally equivalent to RTSI bus trigger lines.
DAQ-STC TRIG1 TRIG2 CONVERT* UPDATE* WFTRIG
TTL Triggers
5
ECL Triggers
VXIbus Trigger Lines
2
Crossbar Switch
GPCTR0_SOURCE GPCTR0_GATE GPCTR0_OUT STARTSCAN AIGATE SISOURCE UISOURCE GPCTR1_SOURCE GPCTR1_GATE RTSI_OSC (20 MHz)

Figure 3-10. VXIbus Trigger Utilization

Refer to the Timing Connections section of Chapter 4 for a description of the signals shown in Figure 3-10.
National Instruments Corporation 3-17 VXI-MIO Series User Manual
Chapter
Signal Connections
This chapter describes how to make input and output signal connections
to your VXI-MIO Series module via the module I/O connector.
The VXI-MIO-64E-1 and VXI-MIO-64XE-10 I/O connector has
96 pins that you can connect to 68-pin accessories with the SH966868
shielded cable. Refer to Appendix B,

I/O Connector

Warning:
Connections that exceed any of the maximum ratings of input or output signals on the VXI-MIO Series modules can damage the module. Maximum input ratings for each signal are given in Tables 4-1 and 4-2 in the resulting from signal connections that exceed these maximum ratings.
Descriptions
Figure 4-1 shows the 96-pin I/O connector pin assignments on the
VXI-MIO-64E-1 and VXI-MIO-64XE-10. A signal description follows
the connector pinouts.
Protection
, for more information.
column. National Instruments is
4
Optional Cable Connector
NOT
liable for any damages
National Instruments Corporation 4-1 VXI-MIO Series User Manual
Chapter 4 Signal Connections
PFI9/GPCTR0_GATE
PFI6/WFTRIG
PFI4/GPCTR1_GATE
PFI1/TRIG2
+5 V DIO7 DIO2 DIO4
DAC0OUT
ACH0 ACH9
ACH3
ACH4
ACH13
ACH7
ACH16
ACH25 ACH19
ACH28 ACH22 ACH31 ACH33 ACH42
AISENSE2
ACH37 ACH46 ACH48 ACH57
ACH51 ACH60 ACH54 ACH63
A
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
1
9 8 7 6 5 4 3 2 1
GPCTR0_OUT
PFI7/STARTSCAN
GPCTR1_OUT
PFI2/CONVERT*
EXTSTROBE*
DGND
DIO6 DIO1
AOGND
EXTREF
ACH1
ACH10
AISENSE
ACH5
ACH14
AIGND
ACH17 ACH26
ACH20 ACH29 ACH23 ACH40 ACH34 ACH43 ACH44 ACH38 ACH47 ACH49 ACH58 ACH52 ACH61 ACH55
B
32 31
PFI8/GPCTR0_SOURCE
30
PFI3/GPCTR1_SOURCE
29 28 27 26 25 24
2
23 22 21
3
20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
FREQ_OUT
PFI5/UPDATE*
PFI0/TRIG1
SCANCLK
DIO3 DIO5
DIO0
DAC1OUT
ACH8
ACH2
ACH11 ACH12
ACH6
ACH15
ACH24 ACH18
ACH27 ACH21 ACH30 ACH32 ACH41 ACH35 ACH36 ACH45 ACH39 ACH56 ACH50 ACH59 ACH53 ACH62
C
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
1
SENSE for ACH16 through ACH63
2
This pin is not connected on the VXI-MIO-64XE-10
3
SENSE for ACH0 through ACH15
Figure 4-1.
I/O Connector Pin Assignment for the VXI-MIO-64E-1 and
VXI-MIO Series User Manual 4-2
VXI-MIO-64XE-10
National Instruments Corporation

I/O Connector Signal Descriptions

Chapter 4 Signal Connections
Signal Name
AIGND
ACH<0..15> AIGND Input Analog Input Channels 0 through 15—Each channel pair,
ACH<16..63> AIGND Input Analog Input Channels 16 through 63—Each channel pair,
AISENSE AIGND Input Analog Input Sense—This pin serves as the reference node
AISENSE2 AIGND Input Analog Input Sense—This pin serves as the reference node
DAC0OUT AOGND Output Analog Channel 0 Output—This pin supplies the voltage
DAC1OUT AOGND Output Analog Channel 1 Output—This pin supplies the voltage
EXTREF AOGND Input External Reference—This is the external reference input for
Reference Direction Description
Analog Input Ground—These pins are the reference point
for single-ended measurements and the bias current return point for differential measurements. All three ground references—AIGND, AOGND, and DGND—are connected together on your VXI-MIO Series module.
ACH<i, i+8> (i = 0..7), can be configured as either one differential input or two single-ended inputs.
ACH<i, i+8> (i = 16..23, 32..39, 48..55), can be configured as either one differential input or two single-ended inputs.
for any of channels ACH <0..15> in NRSE configuration.
for any of channels ACH <16..63> in NRSE configuration.
output of analog output channel 0.
output of analog output channel 1.
the analog output circuitry. This pin is VXI-MIO-64XE-10.
not
available on the
AOGND Analog Output Ground—The analog output voltages are
referenced to this node. All three ground references— AIGND, AOGND, and DGND—are connected together on your VXI-MIO Series module.
DGND Digital Ground—This pin supplies the reference for the
digital signals at the I/O connector as well as the +5 VDC supply. All three ground references—AIGND, AOGND, and DGND—are connected together on your VXI-MIO Series module.
DIO<0..7> DGND Input or
Output
+5 V DGND Output +5 VDC Source—These pins are fused for up to 1 A of
National Instruments Corporation 4-3 VXI-MIO Series User Manual
Digital I/O signals—DIO6 and 7 can control the up/down signal of general-purpose counters 0 and 1, respectively.
+5 V supply. The circuit breaker is self-resetting.
Chapter 4 Signal Connections
Signal Name
SCANCLK
EXTSTROBE* DGND Output External Strobe—This output can be toggled under software
PFI0/TRIG1 DGND Input
PFI1/TRIG2 DGND Input
PFI2/CONVERT* DGND Input
Reference Direction Description
DGND Output Scan Clock—This pin pulses once for each A/D conversion
in the scanning modes when enabled. The low-to-high edge indicates when the input signal can be removed from the input or switched to another signal.
control to latch signals or trigger events on external devices.
PFI0/Trigger 1—As an input, this is either one of the PFIs or the source for the hardware analog trigger. PFI signals are explained in the chapter. The hardware analog trigger is explained in the
Analog Trigger
Output
Output
As an output, this is the TRIG1 signal. In posttrigger data acquisition sequences, a low-to-high transition indicates the initiation of the acquisition sequence. In pretrigger applications, a low-to-high transition indicates the initiation of the pretrigger conversions.
PFI1/Trigger 2—As an input, this is one of the PFIs.
As an output, this is the TRIG2 signal. In pretrigger applications, a low-to-high transition indicates the initiation of the posttrigger conversions. TRIG2 is not used in posttrigger applications.
PFI2/Convert—As an input, this is one of the PFIs.
(Continued)
Timing Connections
section in Chapter 2.
section later in this
Output
PFI3/GPCTR1_SOURCE DGND Input
Output
PFI4/GPCTR1_GATE DGND Input
Output
GPCTR1_OUT DGND Output Counter 1 Output—This output is from the general-purpose
VXI-MIO Series User Manual 4-4
As an output, this is the CONVERT* signal. A high-to-low edge on CONVERT* indicates that an A/D conversion is occurring.
PFI3/Counter 1 Source—As an input, this is one of the PFIs.
As an output, this is the GPCTR1_SOURCE signal. This signal reflects the actual source connected to the general-purpose counter 1.
PFI4/Counter 1 Gate—As an input, this is one of the PFIs.
As an output, this is the GPCTR1_GATE signal. This signal reflects the actual gate signal connected to the general-purpose counter 1.
counter 1 output.
National Instruments Corporation
Chapter 4 Signal Connections
Signal Name
PFI5/UPDATE*
PFI6/WFTRIG DGND Input
PFI7/STARTSCAN DGND Input
PFI8/GPCTR0_SOURCE DGND Input
PFI9/GPCTR0_GATE DGND Input
Reference Direction Description
DGND Input
Output
Output
Output
Output
(Continued)
PFI5/Update—As an input, this is one of the PFIs.
As an output, this is the UPDATE* signal. A high-to-low edge on UPDATE* indicates that the analog output primary group is being updated.
PFI6/Waveform Trigger—As an input, this is one of the PFIs.
As an output, this is the WFTRIG signal. In timed analog output sequences, a low-to-high transition indicates the initiation of the waveform generation.
PFI7/Start of Scan—As an input, this is one of the PFIs.
As an output, this is the STARTSCAN signal. This pin pulses once at the start of each analog input scan in the interval scan. A low-to-high transition indicates the start of the scan.
PFI8/Counter 0 Source—As an input, this is one of the PFIs.
As an output, this is the GPCTR0_SOURCE signal. This signal reflects the actual source connected to the general-purpose counter 0.
PFI9/Counter 0 Gate—As an input, this is one of the PFIs.
Output
GPCTR0_OUT DGND Output Counter 0 Output—This output is from the general-purpose
FREQ_OUT DGND Output Frequency Output—This output is from the frequency
National Instruments Corporation 4-5 VXI-MIO Series User Manual
As an output, this is the GPCTR0_GATE signal. This signal reflects the actual gate signal connected to the general-purpose counter 0.
counter 0 output.
generator output.
Chapter 4 Signal Connections
Table 4-1 shows the I/O signal summary for the VXI-MIO-64E-1.
Table 4-1.
Signal Name
ACH<0..63>
AISENSE, AISENSE2 AI 100 GΩ
AIGND AI
DAC0OUT AO 0.1
DAC1OUT AO 0.1
EXTREF AO 10 k
AOGND AO
DGND DO
Drive Impedance
AI 100 GΩ
VXI-MIO-64E-1 I/O Signal Summary
Protection
Input/
Output
in parallel with 100 pF
in parallel with 100 pF
(Volts)
Power On/Off
25/15
25/15
Short-circuit to ground
Short-circuit to ground
25/15
Source
(mA at V)
5 at 10 V 5 at -10 V 20
5 at 10 V 5 at -10 V 20
Sink
(mA at
V)
Rise
Time
(ns)
±
±
V/µs
V/µs
Bias
200 pA
200 pA
+5 V DO 0.1
DIO<0..7> DIO 5.5 V 13 at (4.6 V) 24 at 0.4 1.1 50 kΩ pu
SCANCLK
EXTSTROBE* DO 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
PFI0/TRIG1 ADIO 10 k
PFI1/TRIG2
PFI2/CONVERT* DIO 5.5 V 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
PFI3/GPCTR1_SOURCE DIO 5.5 V 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
PFI4/GPCTR1_GATE DIO 5.5 V 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
DO 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
DIO 5.5 V 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
VXI-MIO Series User Manual 4-6
Short-circuit to ground
5.5 V
1 A at 5 V
3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
National Instruments Corporation
1
2
Chapter 4 Signal Connections
Signal Name
GPCTR1_OUT
Table 4-1.
Drive Impedance
DO 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
VXI-MIO-64E-1 I/O Signal Summary (Continued)
Input/
Output
Protection
(Volts)
Power On/Off
Source
(mA at V)
Sink
(mA at
V)
Rise
Time
(ns)
Bias
PFI5/UPDATE* DIO 5.5 V 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
PFI6/WFTRIG DIO 5.5 V 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
PFI7/STARTSCAN DIO 5.5 V 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
PFI8/GPCTR0_SOURCE DIO 5.5 V 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
PFI9/GPCTR0_GATE DIO 5.5 V 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
GPCTR0_OUT DO 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
FREQ_OUT DO 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
AI = Analog Input DIO = Digital Input/Output pu = pullup AO = Analog Output DO = Digital Output ADIO = Analog/Digital Input/Output
1
DIO <6..7> are also pulled down with a 50 kΩ resistor.
2
Also pulled down with a 10 kΩ resistor.
Note:
The tolerance on the 50 kΩ pullup and pulldown resistors is very large. Actual value may range between 17 and 100 kΩ.
National Instruments Corporation 4-7 VXI-MIO Series User Manual
Chapter 4 Signal Connections
Table 4-2 shows the I/O signal summary for the VXI-MIO-64XE-10.
Table 4-2.
Signal Name
ACH<0..63>
AISENSE AI 100 GΩ in
AIGND AI
DAC0OUT AO 0.1
DAC1OUT AO 0.1
AOGND AO
DGND DO
+5 V DO 0.1
Drive Impedance
AI 100 GΩ in
VXI-MIO-64XE-10 I/O Signal Summary
Protection
Input/
Output
parallel with 100 pF
parallel with 100 pF
(Volts)
Power On/Off
25/15
25/15
Short-circuit to ground
Short-circuit to ground
Short-circuit to ground
(mA at V)
5 at 10 V 5 at -10 V 5
5 at 10 V 5 at -10 V 5
1A
Source
Sink
(mA at V)
Rise
Time
(ns)
V/µs
V/µs
±
±
Bias
1 nA
1 nA
DIO<0..7> DIO 5.5 V 13 at (4.6 V) 24 at 0.4 1.1 50 kΩ pu
SCANCLK DO 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
EXTSTROBE* DO 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
PFI0/TRIG1 DIO 5.5 V 3.5 at (4.6 V) 5 at 0.4 1.5 4.75 kΩ pu
PFI1/TRIG2 DIO 5.5 V 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
PFI2/CONVERT* DIO 5.5 V 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
PFI3/GPCTR1_SOURCE DIO 5.5 V 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
PFI4/GPCTR1_GATE DIO 5.5 V 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
GPCTR1_OUT DO 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
VXI-MIO Series User Manual 4-8
National Instruments Corporation
Chapter 4 Signal Connections
Table 4-2.
Signal Name
PFI5/UPDATE*
PFI6/WFTRIG DIO 5.5 V 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
PFI7/STARTSCAN DIO 5.5 V 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
PFI8/GPCTR0_SOURCE DIO 5.5 V 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
PFI9/GPCTR0_GATE DIO 5.5 V 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
GPCTR0_OUT DO 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
FREQ_OUT DO 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
AI = Analog Input DIO = Digital Input/Output pu = pullup AO = Analog Output DO = Digital Output
Note:
The tolerance on the 50 kΩ pullup and pulldown resistors is very large. Actual value may range between 17 and 100 kΩ.
Drive Impedance
DIO 5.5 V 3.5 at (4.6 V) 5 at 0.4 1.5 50 kΩ pu
VXI-MIO-64XE-10 I/O Signal Summary (Continued)
Input/
Output
Protection
(Volts)
Power On/Off
Source
(mA at V)
Sink
(mA at V)
Rise
Time
(ns)

Analog Input Signal Connections

Bias
The VXI-MIO-64E-1 and VXI-MIO-64XE-10 analog input signals are ACH<0..63>, AISENSE, AISENSE2, and AIGND. The ACH<0..63> signals are tied to the 64 analog input channels of both modules. In single-ended mode, signals connected to ACH<0..63> are routed to the positive input of both modules. In differential mode, signals connected to ACH<0..7, 16..23, 32..39,
48..55> are routed to the positive input of the PGIA, and signals connected to ACH<8..15, 24..31, 40..47, 56..63> are routed to the negative input of the PGIA.
Warning:
Exceeding the differential and common-mode input ranges distorts your input signals. Exceeding the maximum input voltage rating can damage the VXI-MIO Series module and your VXIbus system. National Instruments is
liable for any damages resulting from such signal
NOT
connections. The maximum input voltage ratings are listed in Tables 4-1 and 4-2 in the
National Instruments Corporation 4-9 VXI-MIO Series User Manual
Protection
column.
Chapter 4 Signal Connections
In NRSE mode, the AISENSE and AISENSE2 signals are connected internally to the negative input of the VXI-MIO Series module PGIA when their corresponding channels are selected. In DIFF and RSE modes, the AISENSE/AISENSE signals are left unconnected.
AIGND is an analog input common signal that is routed directly to the ground tie point on the VXI-MIO Series modules. You can use this signal for a general analog ground tie point to your VXI-MIO Series module if necessary.
Connection of analog input signals to your VXI-MIO Series module depends on the configuration of the analog input channels you are using and the type of input signal source. With the different configurations, you can use the PGIA in different ways. Figure 4-2 shows a diagram of your VXI-MIO Series module PGIA.
Instrumentation
Amplifier
V
in+
+
V
in-
Figure 4-2.
The PGIA applies gain and common-mode voltage rejection and presents high input impedance to the analog input signals connected to your VXI-MIO Series module. Signals are routed to the positive and negative inputs of the PGIA through input multiplexers on the module. The PGIA converts two input signals to a signal that is the difference between the two input signals multiplied by the gain setting of the amplifier. The amplifier output voltage is referenced to the board
VXI-MIO Series User Manual 4-10
PGIA
-
Vm = [V
VXI-MIO Series PGIA
in+
- V
+
V
m
Measured
Voltage
-
]* Gain
in-
National Instruments Corporation
ground. Your VXI-MIO Series module ADC measures this output voltage when it performs A/D conversions.
You must reference all signals to ground either at the signal source or at the module. If you have a floating source, reference the signal to ground by using the RSE input mode or the DIFF input configuration with bias resistors (see the
or Floating Signal Sources
grounded source, you should not reference the signal to AIGND. You can avoid this reference by using DIFF or NRSE input configurations.

Types of Signal Sources

When configuring the input channels and making signal connections, you must first determine whether the signal sources are floating or ground-referenced. The following sections describe these two types of signals.

Floating Signal Sources

A floating signal source is one that is not connected in any way to earth ground but, rather, has an isolated ground-reference point. Some examples of floating signal sources are outputs of transformers, thermocouples, battery-powered devices, optical isolated outputs, and isolation amplifiers. Tie the ground reference of a floating signal to your VXI-MIO Series module analog input ground to establish a local or onboard reference for the signal. Otherwise, the measured input signal varies as the source floats out of the common-mode input range.
Chapter 4 Signal Connections
Differential Connections for Nonreferenced
section later in this chapter). If you have a

Ground-Referenced Signal Sources

A ground-referenced signal source is one that is connected in some way to the same ground reference as the VXI-MIO Series module. An example of this type of signal is a nonisolated output of a signal generator which is powered from the same power strip as the VXIbus system.
The difference in ground potential between two instruments connected to the same power distribution system is typically between 1 and 100 mV but can be much higher if power distribution circuits are not properly connected. If a grounded signal source is improperly measured, this difference may appear as an error in the measurement. The connection instructions for grounded signal sources are designed to eliminate this ground potential difference from the measured signal.
National Instruments Corporation 4-11 VXI-MIO Series User Manual
Chapter 4 Signal Connections

Input Configurations

You can configure your VXI-MIO Series module for one of three input modes—NRSE, RSE, or DIFF. The following sections discuss the use of single-ended and differential measurements and considerations for measuring both floating and ground-referenced signal sources.
VXI-MIO Series User Manual 4-12
National Instruments Corporation
Chapter 4 Signal Connections
Figure 4-3 summarizes the recommended input configuration for both types of signal sources.
Signal Source Type
Input
Differential
(DIFF)
Referenced
Single-Ended
Ground
(RSE)
Floating Signal Source
(Not Connected to Earth Ground)
Examples
• Ungrounded thermocouples
• Signal conditioning with isolated outputs
• Battery devices
+
V
1
-
ACH(+)
ACH (-)
R
+
-
AIGND
See text for information on bias resistors.
+
V
1
-
ACH
AIGND
+
-
Grounded Signal Source
Examples
• Plug-in instruments with nonisolated outputs
+
V
1
-
NOT RECOMMENDED
+
V
1
-
+ Vg -
ACH(+)
ACH (-)
ACH
+
-
AIGND
+
-
Ground-loop losses, Vg, are added to measured signal
Nonreferenced
Single-Ended
(NRSE)
+
V
1
-
ACH
AISENSE
+
-
R
AIGND
+
V
1
-
ACH
AISENSE
+
-
AIGND
See text for information on bias resistors.
Figure 4-3.
National Instruments Corporation 4-13 VXI-MIO Series User Manual
Summary of Analog Input Connections
Chapter 4 Signal Connections

Differential Connection Considerations (DIFF Input Configuration)

A differential connection is one in which the VXI-MIO Series module analog input signal has its own reference signal or signal return path. These connections are available when the selected channel is configured in DIFF input mode. The input signal is tied to the positive input of the PGIA, and its reference signal, or return, is tied to the negative input of the PGIA.
When you configure a channel for differential input, each signal uses two multiplexer input lines—one for the signal and one for its reference signal. Therefore, with a differential configuration for every channel, up to 32 analog input channels are available.
You should use differential input connections for any channel that meets any of the following conditions:
The input signal is low level (less than 1 V).
The leads connecting the signal to the VXI-MIO Series module are greater than 10 ft (3 m).
The input signal requires a separate ground-reference point or return signal.
The signal leads travel through noisy environments.
DIFF input connections reduce pick-up noise and increase common-mode noise rejection. Differential signal connections also allow input signals to float within the common-mode limits of the PGIA.
VXI-MIO Series User Manual 4-14
National Instruments Corporation
Ground-
Referenced
Signal
Source
Chapter 4 Signal Connections
Differential Connections for Ground-Referenced Signal Sources
Figure 4-4 shows how to connect a ground-referenced signal source to a channel on a VXI-MIO Series module configured in DIFF input mode.
ACH<0..7>
+
V
s
-
Instrumentation
Amplifier
+
Common-
Mode
Noise and
Ground
Potential
I/O Connector
PGIA
ACH<8..15>
-
+
V
cm
-
Other Input Multiplexers
AISENSE
AIGND
Selected Channel in DIFF Configuration
Figure 4-4.
Differential Input Connections for Ground-Referenced Signals
+
m
Measured
Voltage
-
V
With this type of connection, the PGIA rejects both the common-mode noise in the signal and the ground potential difference between the signal source and the VXI-MIO Series module ground, shown as Vcm in Figure 4-4.
National Instruments Corporation 4-15 VXI-MIO Series User Manual
Chapter 4 Signal Connections
Bias resistors (see text)
Floating
Signal
Source
+
V
S
-
Differential Connections for Nonreferenced or Floating Signal Sources
Figure 4-5 shows how to connect a floating signal source to a channel on a VXI-MIO Series module configured in DIFF input mode.
ACH<0..7>
Instrumentation
Amplifier
+
Bias
Current
Return
Paths
I/O Connector
PGIA
ACH<8..15>
-
Other Input Multiplexers
AISENSE
AIGND
Selected Channel in DIFF Configuration
+
m
Measured
Voltage
-
V

Figure 4-5. Differential Input Connections for Nonreferenced Signals

Figure 4-5 shows two bias resistors connected in parallel with the signal leads of a floating signal source. If you do not use the resistors and the source is truly floating, the source is not likely to remain within the common-mode signal range of the PGIA, and the PGIA will saturate, causing erroneous readings. You must reference the source to AIGND. The easiest way is simply to connect the positive side of the signal to the positive input of the PGIA and connect the negative side of the signal to AIGND as well as to the negative input of the PGIA, without
VXI-MIO Series User Manual 4-16
National Instruments Corporation
Chapter 4 Signal Connections
any resistors at all. This connection works well for DC-coupled sources with low source impedance (less than 100 ).
However, for larger source impedances, this connection leaves the differential signal path significantly out of balance. Noise that couples electrostatically onto the positive line does not couple onto the negative line because it is connected to ground. Hence, this noise appears as a differential-mode signal instead of a common-mode signal, and so the PGIA does not reject it. In this case, instead of directly connecting the negative line to AIGND, connect it to AIGND through a resistor that is about 100 times the equivalent source impedance. The resistor puts the signal path nearly in balance, so that about the same amount of noise couples onto both connections, yielding better rejection of electrostatically coupled noise. Also, this configuration does not load down the source (other than the very high input impedance of the PGIA).
You can fully balance the signal path by connecting another resistor of the same value between the positive input and AIGND, as shown in Figure 4-5. This fully-balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination (sum) of the two resistors. If, for example, the source impedance is 2 k and each of the two resistors is 100 k, the resistors load down the source with 200 k and produce a -1% gain error.
Both PGIA inputs require a DC path to ground in order for the PGIA to work. If the source is AC-coupled (capacitively coupled), the PGIA needs a resistor between the positive input and AIGND. If the source has low impedance, choose a resistor that is large enough not to significantly load the source but small enough not to produce significant input offset voltage as a result of input bias current (typically 100 k to 1 M). In this case, you can tie the negative input directly to AIGND. If the source has high output impedance, you should balance the signal path as previously described using the same value resistor on both the positive and negative inputs; you should be aware that there is some gain error from loading down the source.
Refer to Application Note 025, Field Wiring and Noise Considerations for Analog Signals, for more information.
National Instruments Corporation 4-17 VXI-MIO Series User Manual
Chapter 4 Signal Connections

Single-Ended Connection Considerations

A single-ended connection is one in which the VXI-MIO Series module analog input signal is referenced to a ground that can be shared with other input signals. The input signal is tied to the PGIA positive input, and the ground is tied to the PGIA negative input.
When you configure every channel for single-ended input, up to 64 analog input channels are available.
You can use single-ended input connections for any channel signal that meets all of the following conditions:
The input signal is high level (greater than 1 V).
The leads connecting the signal to the VXI-MIO Series module are less than 10 ft (3 m).
The input signal can share a common reference point with other signals.
DIFF input connections are recommended for greater signal integrity
for any input signal that does not meet the preceding conditions.
You can software-configure the VXI-MIO Series module channels for two different types of single-ended connections—RSE configuration and NRSE configuration. The RSE configuration is used for floating signal sources; in this case, the VXI-MIO Series module provides the reference ground point for the external signal. The NRSE input configuration is used for ground-referenced signal sources; in this case, the external signal supplies its own reference ground point and the VXI-MIO Series module should not supply one.
In single-ended configurations, more electrostatic and magnetic noise couples into the signal connections than in differential configurations. The coupling is the result of differences in the signal path. Magnetic coupling is proportional to the area between the two signal conductors. Electrical coupling is a function of how much the electric field differs between the two conductors.
VXI-MIO Series User Manual 4-18
National Instruments Corporation
Chapter 4 Signal Connections
Single-Ended Connections for Floating Signal
Sources (RSE Configuration)
Figure 4-6 shows how to connect a floating signal source to a channel on the VXI-MIO Series module configured for RSE mode.
ACH<0..15>
Floating
Signal
Source
+
V
s
-
I/O Connector
Figure 4-6.
Single-Ended Connections for Grounded Signal
Sources (NRSE Configuration)
To measure a grounded signal source with a single-ended configuration, you must configure your VXI-MIO Series module in the NRSE input configuration. The signal is then connected to the module’s PGIA positive input, and the signal local ground reference is connected to the PGIA negative input. The ground point of the signal should, therefore, be connected to the AISENSE pin. Any potential difference between the VXI-MIO Series ground and the signal ground appears as a common-mode signal at both the positive and negative inputs of the PGIA, and this difference is rejected by the amplifier. If the input circuitry of the VXI-MIO module were referenced to ground in this situation as in the RSE input configuration, this difference in ground potentials would appear as an error in the measured voltage.
Instrumentation
PGIA
Amplifier
V
m
+
Measured
Voltage
-
+
Other Input Multiplexers
-
AISENSE
AIGND
Selected Channel in RSE Configuration
Single-Ended Input Connections for Nonreferenced or Floating Signals
Figure 4-7 shows how to connect a grounded signal source to a channel on the VXI-MIO Series module configured for NRSE mode.
National Instruments Corporation 4-19 VXI-MIO Series User Manual
Chapter 4 Signal Connections
ACH<0..15>
Ground-
Referenced
Signal
Source
Common-
Mode Noise
and Ground
Potential
+
V
s
-
+
V
cm
-
I/O Connector
Figure 4-7.
Input Multiplexers
AIGND
Selected Channel in NRSE Configuration
AISENSE
Single-Ended Input Connections for Ground-Referenced Signal

Common-Mode Signal Rejection Considerations

Figures 4-6 and 4-7 show connections for signal sources that are already referenced to some ground point with respect to the VXI-MIO Series module. In these cases, the PGIA can reject any voltage caused by ground potential differences between the signal source and the module. In addition, with differential input connections, the PGIA can reject common-mode noise pickup in the leads connecting the signal sources to the module. The PGIA can reject common-mode signals as long as V
+
in
and V
-
are both within ±11 V of AIGND
in
Instrumentation
+
PGIA
-
Amplifier
V
m
+
Measured
Voltage
-
.

Analog Output Signal Connections

The analog output signals are DAC0OUT, DAC1OUT, EXTREF, and AOGND.
DAC0OUT is the voltage output signal for analog output channel 0. DAC1OUT is the voltage output signal for analog output channel 1.
EXTREF is the external reference input signal for both analog output channels. You must configure each analog output channel individually for external reference selection in order for the signal applied at the
VXI-MIO Series User Manual 4-20
EXTREF is not available on the VXI-MIO-64XE-10
.
National Instruments Corporation
External
Reference
Signal
(Optional)
Chapter 4 Signal Connections
external reference input to be used by that channel. If you do not specify an external reference, the channel will use the internal reference.
You cannot use an external analog output reference with the VXI-MIO-64XE-10.
in the
Analog Output
Analog output configuration options are explained
section in Chapter 3,
Hardware Overview
. The
following ranges and ratings apply to the EXTREF input signal:
Usable input voltage range: ±11 V peak with respect to AOGND
Absolute maximum ratings: ±15 V peak with respect to AOGND AOGND is the ground reference signal for both analog output channels
and the external reference signal.
Figure 4-8 shows how to make analog output connections and the
external reference input connection to your VXI-MIO Series module.
EXTREF
DAC0OUT
+
V
ref
­Load
+
V
0
OUT
-
AOGND
Channel 0
-
V
1
Load
OUT
+
Figure 4-8.
DAC1OUT
Channel 1
Analog Output Channels
VXI-MIO Series Board
Analog Output Connections
The external reference signal can be either a DC or an AC signal. The module multiplies this reference signal by the DAC code (divided by the full-scale DAC code) to generate the output voltage.
National Instruments Corporation 4-21 VXI-MIO Series User Manual
Chapter 4 Signal Connections

Digital I/O Signal Connections

The digital I/O signals are DIO<0..7> and DGND. DIO<0..7> are the signals making up the DIO port, and DGND is the ground reference signal for the DIO port. You can program all lines individually to be inputs or outputs.
Warning:
LED
+5 V
Exceeding the maximum input voltage ratings, which are listed in Tables 4-1 and 4-2, can damage the VXI-MIO Series module. National Instruments is
NOT
liable for any damages resulting from such incorrect
signal connections.
Figure 4-9 shows signal connections for three typical digital I/O applications.
+5 V
DIO<7> DIO<6>
DIO<5> DIO<4> DIO<3>
TTL Signal
Switch*
DIO<2> DIO<1> DIO<0>
I/O Connector
* Complex switch circuitry is not shown in order to simplify the figure.
Figure 4-9.
VXI-MIO Series User Manual 4-22
DGND
VXI-MIO Series Board
Digital I/O Connections
National Instruments Corporation
Figure 4-9 shows DIO<0, 2..3, 5..6> configured for digital input and DIO<1, 4, 7> configured for digital output. Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch. Digital output applications include sending TTL signals and driving external devices such as the LED.

Power Connections

One pin on the I/O connector supplies +5 V from the VXIbus power supply via a self-resetting fuse. The fuse will reset automatically after you remove the overcurrent condition. These pins are referenced to DGND and can be used to power external digital circuitry.
Power rating +4.65 to +5.25 VDC at 1 A
Chapter 4 Signal Connections
Warning:
Under no circumstances should you connect these +5 V power pins directly to analog or digital ground or to any other voltage source on the VXI-MIO Series module or any other device. Doing so can damage the VXI-MIO Series module and your device. National Instruments is liable for damages resulting from such a connection.

Timing Connections

Warning:
Exceeding the maximum input voltage ratings, which are listed in Tables 4-1 and 4-2, can damage the VXI-MIO Series module. National Instruments is connections.
All external control over the VXI-MIO module timing is routed through the 10 programmable function input signals labeled PFI<0..9>. These signals are explained in detail in the
Connections
as output signals they are not programmable and reflect the state of many data acquisition, waveform generation, and general-purpose timing signals. There are five other dedicated output lines for the remainder of the timing signals. As input signals, the PFI signals are programmable and can control any data acquisition, waveform generation, and general-purpose timing signals.
NOT
liable for any damages resulting from incorrect signal
NOT
Programmable Function Input
section in this chapter. These PFI signals are bidirectional;
The data acquisition signals are explained in the
Timing Connections
generation signals are explained in the
National Instruments Corporation 4-23 VXI-MIO Series User Manual
section later in this chapter. The waveform
Waveform Generation Timing
Data Acquisition
Chapter 4 Signal Connections
Connections
signals are explained in the
Connections
section later in this chapter. The general-purpose timing
General-Purpose Timing Signal
section later in this chapter.
All digital timing connections are referenced to DGND. This reference is demonstrated in Figure 4-10, which shows how to connect an external TRIG1 source and an external CONVERT* source to two of the VXI-MIO Series module PFI pins.
PFI0/TRIG1
PFI2/CONVERT*
TRIG1
Source
CONVERT*
Source
DGND
I/O Connector
Figure 4-10.

Programmable Function Input Connections

There are a total of 13 internal timing signals that you can externally control from the PFI pins. The source for each of these signals is software-selectable from any of the PFIs when you want external control. This flexible routing scheme reduces the need to change the physical wiring to the module I/O connector for different applications requiring alternative wiring.
You can individually enable each of the PFI pins to output a specific internal timing signal. For example, if you need the CONVERT* signal as an output on the I/O connector, your software can turn on the output
VXI-MIO Series User Manual 4-24
VXI-MIO Series Board
Timing I/O Connections
National Instruments Corporation
driver for the PFI2/CONVERT* pin. Be careful not to drive a PFI signal externally when it is configured as an output.
As an input, you can individually configure each PFI for edge or level detection and also for polarity selection. You can use the polarity selection for any of the 13 timing signals, but the edge or level detection will depend upon the particular timing signal being controlled. The detection requirements for each timing signal are listed in the section that discusses that individual signal.
In edge-detection mode, a minimum pulse width of 10 ns is required. This applies for both rising-edge and falling-edge polarity settings. There is no maximum pulse-width requirement in edge-detection mode.
In level-detection mode, there are no minimum or maximum pulse-width requirements imposed by the PFIs themselves, but limits may be imposed by the particular timing signal being controlled. These requirements are listed later in this chapter.

Data Acquisition Timing Connections

The data acquisition timing signals are SCANCLK, EXTSTROBE*, TRIG1, TRIG2, STARTSCAN, CONVERT*, AIGATE, and SISOURCE.
Chapter 4 Signal Connections
Posttriggered data acquisition allows you to view only data that is acquired after a trigger event is received. A typical posttriggered data acquisition sequence is shown in Figure 4-11. Pretriggered data acquisition allows you to view data that is acquired before the trigger of interest in addition to data acquired after the trigger. Figure 4-12 shows a typical pretriggered data acquisition sequence. The description for each signal shown in these figures is included later in this chapter.
TRIG1
STARTSCAN
CONVERT*
Scan Counter
Figure 4-11.
National Instruments Corporation 4-25 VXI-MIO Series User Manual
Typical Posttriggered Acquisition
13042
Chapter 4 Signal Connections
TRIG1
TRIG2
STARTSCAN
CONVERT*
Scan Counter
Don't Care
01231 0222
Figure 4-12.
Typical Pretriggered Acquisition
SCANCLK Signal
SCANCLK is an output-only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A/D conversion begins. The polarity of this output is software selectable but is typically configured so that a low-to-high leading edge can clock external analog input multiplexers indicating when the input signal has been sampled and can be removed. This signal has a 400 to 500 ns pulse width and is software-enabled. Figure 4-13 shows the timing for the SCANCLK signal.
CONVERT*
SCANCLK
Figure 4-13.
EXTSTROBE* Signal
EXTSTROBE* is an output-only signal that generates either a single pulse or a sequence of eight pulses in the hardware-strobe mode. An external device can use this signal to latch signals or to trigger events. In the single-pulse mode, your software controls the EXTSTROBE*
VXI-MIO Series User Manual 4-26
t
d
t
t
d
t
w
SCANCLK Signal Timing
National Instruments Corporation
w
= 50 to 100 ns = 400 to 500 ns
Chapter 4 Signal Connections
signal level. A 10 and 1.2 µs clock is available for generating a sequence of eight pulses in the hardware-strobe mode. Figure 4-14 shows the timing for the hardware-strobe mode EXTSTROBE* signal.
V
OH
V
OL
t
t
w
w
t
= 600 ns or 5 µs
w
Figure 4-14.
EXTSTROBE* Signal Timing
TRIG1 Signal
Any PFI pin can externally input the TRIG1 signal, which is available as an output on the PFI0/TRIG1 pin.
Refer to Figures 4-11 and 4-12 for the relationship of TRIG1 to the data acquisition sequence.
As an input, the TRIG1 signal is configured in the edge-detection mode. You can select any PFI pin as the source for TRIG1 and configure the polarity selection for either rising or falling edge. The selected edge of the TRIG1 signal starts the data acquisition sequence for both posttriggered and pretriggered acquisitions. The VXI-MIO-64E-1 and VXI-MIO-64XE-10 support analog triggering on the PFI0/TRIG1 pin. See Chapter 3 for more information on analog triggering.
As an output, the TRIG1 signal reflects the action that initiates a data acquisition sequence. This is true even if the acquisition is being externally triggered by another PFI. The output is an active high pulse with a pulse width of 50 to 100 ns. This signal is set to input (High-Z) at startup.
Figures 4-15 and 4-16 show the input and output timing requirements for the TRIG1 signal.
National Instruments Corporation 4-27 VXI-MIO Series User Manual
Chapter 4 Signal Connections
Rising-edge polarity
Falling-edge polarity
t
w
t
= 10 ns minimum
w
Figure 4-15.
Figure 4-16.
TRIG1 Input Signal Timing
t
w
t
= 50-100 ns
w
TRIG1 Output Signal Timing
The module also uses the TRIG1 signal to initiate pretriggered data acquisition operations. In most pretriggered applications, the acquisition is started by a software trigger. Refer to the TRIG2 signal description for a complete description of the use of TRIG1 and TRIG2 in a pretriggered data acquisition operation.
TRIG2 Signal
Any PFI pin can externally input the TRIG2 signal, which is available as an output on the PFI1/TRIG2 pin.
Refer to Figure 4-12 for the relationship of TRIG2 to the data acquisition sequence.
As an input, the TRIG2 signal is configured in the edge-detection mode. You can select any PFI pin as the source for TRIG2 and configure the polarity selection for either rising or falling edge. The selected edge of the TRIG2 signal initiates the posttriggered phase of a pretriggered acquisition sequence. In pretriggered mode, the TRIG1 signal initiates the data acquisition. The scan counter indicates the minimum number of
VXI-MIO Series User Manual 4-28
National Instruments Corporation
Chapter 4 Signal Connections
scans before TRIG2 can be recognized. After the scan counter decrements to zero, it is loaded with the number of posttrigger scans to acquire while the acquisition continues. The module ignores the TRIG2 signal if it is asserted prior to the scan counter decrementing to zero. After the selected edge of TRIG2 is received, the module will acquire a fixed number of scans and the acquisition will stop. This mode acquires data both before and after receiving TRIG2.
As an output, the TRIG2 signal reflects the posttrigger in a pretriggered acquisition sequence. This is true even if the acquisition is being externally triggered by another PFI. The TRIG2 signal is not used in posttriggered data acquisition. The output is an active high pulse with a pulse width of 50 to 100 ns. This signal is set to input (High-Z) at startup.
Figures 4-17 and 4-18 show the input and output timing requirements for the TRIG2 signal.
t
w
Rising-edge polarity
Falling-edge polarity
t
= 10 ns minimum
w
Figure 4-17.
Figure 4-18.
National Instruments Corporation 4-29 VXI-MIO Series User Manual
TRIG2 Input Signal Timing
t
w
t
= 50-100 ns
w
TRIG2 Output Signal Timing
Chapter 4 Signal Connections
STARTSCAN Signal
Any PFI pin can externally input the STARTSCAN signal, which is available as an output on the PFI7/STARTSCAN pin.
Refer to Figures 4-11 and 4-12 for the relationship of STARTSCAN to the data acquisition sequence.
As an input, the STARTSCAN signal is configured in the edge-detection mode. You can select any PFI pin as the source for STARTSCAN and configure the polarity selection for either rising or falling edge. The selected edge of the STARTSCAN signal initiates a scan. The sample interval counter starts if you select internally triggered CONVERT*.
As an output, the STARTSCAN signal reflects the actual start pulse that initiates a scan. This is true even if the starts are being externally triggered by another PFI. You have two output options. The first is an active high pulse with a pulse width of 50 to 100 ns, which indicates the start of the scan. The second action is an active high pulse that terminates at the start of the last conversion in the scan, which indicates a scan in progress. STARTSCAN will be deasserted t conversion in the scan is initiated. This signal is set to input (High-Z) at startup.
after the last
off
Figures 4-19 and 4-20 show the input and output timing requirements for the STARTSCAN signal.
Rising-edge polarity
Falling-edge polarity
Figure 4-19.
VXI-MIO Series User Manual 4-30
t
w
t
= 10 ns minimum
w
STARTSCAN Input Signal Timing
National Instruments Corporation
STARTSCAN
Start Pulse
CONVERT*
STARTSCAN
t
w
tw = 50-100 ns
a. Start of Scan
t
= 10 ns minimum
off
Chapter 4 Signal Connections
t
off
b. Scan in Progress, Two Conversions per Scan
Figure 4-20.
STARTSCAN Output Signal Timing
The CONVERT* pulses are masked off until the module generates the STARTSCAN signal. If you are using internally generated conversions, the first CONVERT* will appear when the onboard sample interval counter reaches zero. If you select an external CONVERT*, the first external pulse after STARTSCAN will generate a conversion. Separate the STARTSCAN pulses by at least one scan period.
A counter on your VXI-MIO Series module internally generates the STARTSCAN signal unless you select some external source. This counter is started by the TRIG1 signal and is stopped either by software or by the sample counter.
Scans generated by either an internal or external STARTSCAN signal are inhibited unless they occur within a data acquisition sequence. Scans occurring within a data acquisition sequence may be gated by either the hardware (AIGATE) signal or software command register gate.
National Instruments Corporation 4-31 VXI-MIO Series User Manual
Chapter 4 Signal Connections
CONVERT* Signal
Any PFI pin can externally input the CONVERT* signal, which is available as an output on the PFI2/CONVERT* pin.
Refer back to Figures 4-11 and 4-12 for the relationship of CONVERT* to the data acquisition sequence.
As an input, the CONVERT* signal is configured in the edge-detection mode. You can select any PFI pin as the source for CONVERT* and configure the polarity selection for either rising or falling edge. The selected edge of the CONVERT* signal initiates an A/D conversion.
As an output, the CONVERT* signal reflects the actual convert pulse that is connected to the ADC. This is true even if the conversions are being externally generated by another PFI. The output is an active low pulse with a pulse width of 50 to 100 ns. This signal is set to input (High-Z) at startup.
Figures 4-21 and 4-22 show the input and output timing requirements for the CONVERT* signal.
Rising-edge polarity
Falling-edge polarity
Figure 4-21.
VXI-MIO Series User Manual 4-32
t
w
t
= 10 ns minimum
w
CONVERT* Input Signal Timing
National Instruments Corporation
t
= 50-100 ns
w
Chapter 4 Signal Connections
t
w
Figure 4-22.
CONVERT* Output Signal Timing
The ADC switches to hold mode within 60 ns of the selected edge. This hold-mode delay time is a function of temperature and does not vary from one conversion to the next. Separate the CONVERT* pulses by at least one conversion period.
The sample interval counter on the VXI-MIO Series module normally generates the CONVERT* signal unless you select some external source. The STARTSCAN signal starts the counter and the counter continues to count down and reload itself until the scan is finished. It then reloads itself in readiness for the next STARTSCAN pulse.
A/D conversions generated by either an internal or external CONVERT* signal are inhibited unless they occur within a data acquisition sequence. Scans occurring within a data acquisition sequence may be gated by either the hardware (AIGATE) signal or software command register gate.
AIGATE Signal
Any PFI pin can externally input the AIGATE signal, which is not available as an output on the I/O connector. The AIGATE signal can mask off scans in a data acquisition sequence. You can configure the PFI pin you select as the source for the AIGATE signal in either the level-detection or edge-detection mode. You can configure the polarity selection for the PFI pin for either active high or active low.
In the level-detection mode if AIGATE is active, the STARTSCAN signal is masked off and no scans can occur. In the edge-detection mode, the first active edge disables the STARTSCAN signal, and the second active edge enables STARTSCAN.
The AIGATE signal can neither stop a scan in progress nor continue a previously gated-off scan; in other words, once a scan has started,
National Instruments Corporation 4-33 VXI-MIO Series User Manual
Chapter 4 Signal Connections
AIGATE does not gate off conversions until the beginning of the next scan and, conversely, if conversions are being gated off, AIGATE does not gate them back on until the beginning of the next scan.
SISOURCE Signal
Any PFI pin can externally input the SISOURCE signal, which is not available as an output on the I/O connector. The onboard scan interval counter uses the SISOURCE signal as a clock to time the generation of the STARTSCAN signal. You must configure the PFI pin you select as the source for the SISOURCE signal in the level-detection mode. You can configure the polarity selection for the PFI pin for either active high or active low.
The maximum allowed frequency is 20 MHz, with a minimum pulse width of 23 ns high or low. There is no minimum frequency limitation.
Either the 20 MHz or 100 kHz internal timebase generates the SISOURCE signal unless you select some external source. Figure 4-23 shows the timing requirements for the SISOURCE signal.
t
p
t
t
w
Figure 4-23.
w
t
p
t
w
= 50 ns minimum = 23 ns minimum

Waveform Generation Timing Connections

The analog group defined for your VXI-MIO Series module is controlled by WFTRIG, UPDATE*, and UISOURCE.
WFTRIG Signal
Any PFI pin can externally input the WFTRIG signal, which is available as an output on the PFI6/WFTRIG pin.
VXI-MIO Series User Manual 4-34
SISOURCE Signal Timing
National Instruments Corporation
Chapter 4 Signal Connections
As an input, the WFTRIG signal is configured in the edge-detection mode. You can select any PFI pin as the source for WFTRIG and configure the polarity selection for either rising or falling edge. The selected edge of the WFTRIG signal starts the waveform generation for the DACs. The update interval (UI) counter is started if you select internally generated UPDATE*.
As an output, the WFTRIG signal reflects the trigger that initiates waveform generation. This is true even if the waveform generation is being externally triggered by another PFI. The output is an active high pulse with a pulse width of 50 to 100 ns. This signal is set to input (High-Z) at startup.
Figures 4-24 and 4-25 show the input and output timing requirements for the WFTRIG signal.
t
w
Rising-edge polarity
Falling-edge polarity
t
= 10 ns minimum
w
Figure 4-24.
Figure 4-25.
National Instruments Corporation 4-35 VXI-MIO Series User Manual
WFTRIG Input Signal Timing
t
w
t
= 50-100 ns
w
WFTRIG Output Signal Timing
Chapter 4 Signal Connections
UPDATE* Signal
Any PFI pin can externally input the UPDATE* signal, which is available as an output on the PFI5/UPDATE* pin.
As an input, the UPDATE* signal is configured in the edge-detection mode. You can select any PFI pin as the source for UPDATE* and configure the polarity selection for either rising or falling edge. The selected edge of the UPDATE* signal updates the outputs of the DACs. In order to use UPDATE*, you must set the DACs to posted-update mode.
As an output, the UPDATE* signal reflects the actual update pulse that is connected to the DACs. This is true even if the updates are being externally generated by another PFI. The output is an active low pulse with a pulse width of 300 to 350 ns. This signal is set to input (High-Z) at startup.
Figures 4-26 and 4-27 show the input and output timing requirements for the UPDATE* signal.
VXI-MIO Series User Manual 4-36
National Instruments Corporation
Rising-edge polarity
Falling-edge polarity
t
w
t
= 10 ns minimum
w
Chapter 4 Signal Connections
Figure 4-26.
Figure 4-27.
UPDATE* Input Signal Timing
t
w
t
= 300-350 ns
w
UPDATE* Output Signal Timing
The DACs are updated within 100 ns of the leading edge. Separate the UPDATE* pulses with enough time that new data can be written to the DAC latches.
The VXI-MIO Series module UI counter normally generates the UPDATE* signal unless you select some external source. The UI counter is started by the WFTRIG signal and can be stopped by software or the internal Buffer Counter.
D/A conversions generated by either an internal or external UPDATE* signal do not occur when gated by the software command register gate.
UISOURCE Signal
Any PFI pin can externally input the UISOURCE signal, which is not available as an output on the I/O connector. The UI counter uses the UISOURCE signal as a clock to time the generation of the UPDATE* signal. You must configure the PFI pin you select as the source for the UISOURCE signal in the level-detection mode. You can configure the
National Instruments Corporation 4-37 VXI-MIO Series User Manual
Chapter 4 Signal Connections
polarity selection for the PFI pin for either active high or active low. Figure 4-28 shows the timing requirements for the UISOURCE signal.
t
p
t
t
w
Figure 4-28.
w
t
= 50 ns minimum
p
t
w
= 23 ns minimum
UISOURCE Signal Timing
The maximum allowed frequency is 20 MHz, with a minimum pulse width of 23 ns high or low. There is no minimum frequency limitation.
Either the 20 MHz or 100 kHz internal timebase normally generates the UISOURCE signal unless you select some external source.

General-Purpose Timing Signal Connections

The general-purpose timing signals are GPCTR0_SOURCE, GPCTR0_GATE, GPCTR0_OUT, GPCTR0_UP_DOWN, GPCTR1_SOURCE, GPCTR1_GATE, GPCTR1_OUT, GPCTR1_UP_DOWN, and FREQ_OUT.
GPCTR0_SOURCE Signal
Any PFI pin can externally input the GPCTR0_SOURCE signal, which is available as an output on the PFI8/GPCTR0_SOURCE pin.
As an input, the GPCTR0_SOURCE signal is configured in the edge-detection mode. You can select any PFI pin as the source for GPCTR0_SOURCE and configure the polarity selection for either rising or falling edge.
As an output, the GPCTR0_SOURCE signal reflects the actual clock connected to general-purpose counter 0. This is true even if another PFI is externally inputting the source clock. This signal is set to input (High-Z) at startup.
VXI-MIO Series User Manual 4-38
National Instruments Corporation
Chapter 4 Signal Connections
Figure 4-29 shows the timing requirements for the GPCTR0_SOURCE signal.
t
p
t
Figure 4-29.
t
w
w
t
= 50 ns minimum
p
t
= 23 ns minimum
w
GPCTR0_SOURCE Signal Timing
The maximum allowed frequency is 20 MHz, with a minimum pulse width of 23 ns high or low. There is no minimum frequency limitation.
The 20 MHz or 100 kHz timebase normally generates the GPCTR0_SOURCE signal unless you select some external source.
GPCTR0_GATE Signal
Any PFI pin can externally input the GPCTR0_GATE signal, which is available as an output on the PFI9/GPCTR0_GATE pin.
As an input, the GPCTR0_GATE signal is configured in the edge-detection mode. You can select any PFI pin as the source for GPCTR0_GATE and configure the polarity selection for either rising or falling edge. You can use the gate signal in a variety of different applications to perform actions such as starting and stopping the counter, generating interrupts, saving the counter contents, and so on.
As an output, the GPCTR0_GATE signal reflects the actual gate signal connected to general-purpose counter 0. This is true even if the gate is being externally generated by another PFI. This signal is set to input (High-Z) at startup.
Figure 4-30 shows the timing requirements for the GPCTR0_GATE signal.
National Instruments Corporation 4-39 VXI-MIO Series User Manual
Chapter 4 Signal Connections
Rising-edge polarity
Falling-edge polarity
t
w
t
= 10 ns minimum
w
GPCTR0_OUT Signal
This signal is available only as an output on the GPCTR0_OUT pin. The GPCTR0_OUT signal reflects the terminal count (TC) of general-purpose counter 0. You have two software-selectable output options— pulse on TC and toggle output polarity on TC. The output polarity is software-selectable for both options. This signal is set to input (High-Z) at startup. Figure 4-31 shows the timing of the GPCTR0_OUT signal.
GPCTR0_SOURCE
GPCTR0_OUT
(Pulse on TC)
GPCTR0_OUT
(Toggle output on TC)
Figure 4-30.
GPCTR0_GATE Signal Timing in Edge-Detection Mode
TC
Figure 4-31.
GPCTR0_OUT Signal Timing
GPCTR0_UP_DOWN Signal
This signal can be externally input on the DIO6 pin and is not available as an output on the I/O connector. The general-purpose counter 0 will count down when this pin is at a logic low and count up when it is at a logic high. You can disable this input so that software can control the up-down functionality and leave the DIO6 pin free for general use.
VXI-MIO Series User Manual 4-40
National Instruments Corporation
Chapter 4 Signal Connections
GPCTR1_SOURCE Signal
Any PFI pin can externally input the GPCTR1_SOURCE signal, which is available as an output on the PFI3/GPCTR1_SOURCE pin.
As an input, the GPCTR1_SOURCE signal is configured in the edge-detection mode. You can select any PFI pin as the source for GPCTR1_SOURCE and configure the polarity selection for either rising or falling edge.
As an output, the GPCTR1_SOURCE monitors the actual clock connected to general-purpose counter 1. This is true even if the source clock is being externally generated by another PFI. This signal is set to input (High-Z) at startup.
Figure 4-32 shows the timing requirements for the GPCTR1_SOURCE signal.
t
p
t
Figure 4-32.
t
w
w
t
= 50 ns minimum
p
t
= 23 ns minimum
w
GPCTR1_SOURCE Signal Timing
The maximum allowed frequency is 20 MHz, with a minimum pulse width of 23 ns high or low. There is no minimum frequency limitation.
The 20 MHz or 100 kHz timebase normally generates the GPCTR1_SOURCE unless you select some external source.
GPCTR1_GATE Signal
Any PFI pin can externally input the GPCTR1_GATE signal, which is available as an output on the PFI4/GPCTR1_GATE pin.
As an input, the GPCTR1_GATE signal is configured in edge-detection mode. You can select any PFI pin as the source for GPCTR1_GATE and
National Instruments Corporation 4-41 VXI-MIO Series User Manual
Chapter 4 Signal Connections
configure the polarity selection for either rising or falling edge. You can use the gate signal in a variety of different applications to perform such actions as starting and stopping the counter, generating interrupts, saving the counter contents, and so on.
As an output, the GPCTR1_GATE signal monitors the actual gate signal connected to general-purpose counter 1. This is true even if the gate is being externally generated by another PFI. This signal is set to input (High-Z) at startup.
Figure 4-33 shows the timing requirements for the GPCTR1_GATE signal.
t
w
Rising-edge polarity
Falling-edge polarity
Figure 4-33.
GPCTR1_GATE Signal Timing in Edge-Detection Mode
GPCTR1_OUT Signal
This signal is available only as an output on the GPCTR1_OUT pin. The GPCTR1_OUT signal monitors the TC module general-purpose counter 1. You have two software-selectable output options—pulse on TC and toggle output polarity on TC. The output polarity is software­selectable for both options. This signal is set to input (High-Z) at startup. Figure 4-34 shows the timing requirements for the GPCTR1_OUT signal.
VXI-MIO Series User Manual 4-42
t
= 10 ns minimum
w
National Instruments Corporation
GPCTR1_SOURCE
GPCTR1_OUT
(Pulse on TC)
GPCTR1_OUT
(Toggle output on TC)
Chapter 4 Signal Connections
TC
SOURCE
GATE
OUT
Figure 4-34.
GPCTR1_OUT Signal Timing
GPCTR1_UP_DOWN Signal
This signal can be externally input on the DIO7 pin and is not available as an output on the I/O connector. General-purpose counter 1 counts down when this pin is at a logic low and counts up at a logic high. This input can be disabled so that software can control the up-down functionality and leave the DIO7 pin free for general use. Figure 4-35 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of your VXI-MIO Series module.
t
sc
V
IH
V
IL
t
gsu
V
IH
V
IL
V
OH
V
OL
Source Clock Period Source Pulse Width Gate Setup Time Gate Hold Time Gate Pulse Width Output Delay Time
t
gw
t
out
t 50 ns minimum
sc
t
sp
t
gsu
t
gh
t
gw
t
out
t
sp
t
gh
23 ns minimum
10 ns minimum
0 ns minimum
10 ns minimum
80 ns maximum
t
sp
Figure 4-35.
National Instruments Corporation 4-43 VXI-MIO Series User Manual
GPCTR Timing Summary
Chapter 4 Signal Connections
The GATE and OUT signal transitions shown in Figure 4-35 are referenced to the rising edge of the SOURCE signal. This timing diagram assumes that the counters are programmed to count rising edges. The same timing diagram, but with the source signal inverted and referenced to the falling edge of the source signal, would apply when the counter is programmed to count falling edges.
The GATE input timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated signals on your VXI-MIO Series module. Figure 4-35 shows the GATE signal referenced to the rising edge of a source signal. The gate must be valid (either high or low) for at least 10 ns before the rising or falling edge of a source signal for the gate to take effect at that source edge, as shown by t
and tgh in Figure 4-35. The gate signal is not required to be held
gsu
after the active edge of the source signal.
If an internal timebase clock is used, the gate signal cannot be synchronized with the clock. In this case, gates applied close to a source edge take effect either on that source edge or on the next one. This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources.
The OUT output timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated clock signals on the VXI-MIO Series modules. Figure 4-35 shows the OUT signal referenced to the rising edge of a source signal. Any OUT signal state changes occur within 80 ns after the rising or falling edge of the source signal.
FREQ_OUT Signal
This signal is available only as an output on the FREQ_OUT pin. The FREQ_OUT signal is the output of the VXI-MIO Series module frequency generator. The frequency generator is a 4-bit counter that can divide its input clock by the numbers 1 through 16. The input clock of the frequency generator is software selectable from the internal 10 MHz and 100 kHz timebases. The output polarity is software selectable. This signal is set to input (High-Z) at startup.
VXI-MIO Series User Manual 4-44
National Instruments Corporation

Field Wiring Considerations

Environmental noise can seriously affect the accuracy of measurements made with your VXI-MIO Series module if you do not take proper care when running signal wires between signal sources and the module. The following recommendations apply mainly to analog input signal routing to the module, although they also apply to signal routing in general.
Take the following precautions to minimize noise pickup and maximize measurement accuracy:
Use differential analog input connections to reject common-mode noise.
Use individually shielded, twisted-pair wires to connect analog input signals to the module. With this type of wire, the signals attached to the CH+ and CH- inputs are twisted together and then covered with a shield. You then connect this shield only at one point to the signal source ground. This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference.
Route signals to the module carefully. Keep cabling away from noise sources. A common noise source in many data acquisition systems is the video monitor. Separate the monitor from the analog signals as much as possible.
Chapter 4 Signal Connections
The following recommendations apply for all signal connections to
your VXI-MIO Series module:
Separate VXI-MIO Series module signal lines from high-current or high-voltage lines. These lines are capable of inducing currents in or voltages on the VXI-MIO Series module signal lines if they run in parallel paths at a close distance. To reduce the magnetic coupling between lines, separate them by a reasonable distance if they run in parallel, or run the lines at right angles to each other.
Do not run signal lines through conduits that also contain power lines.
Protect signal lines from magnetic fields caused by electric motors, welding equipment, breakers, or transformers by running them through special metal conduits.
For more information, refer to the application note,
Noise Consideration for Analog Signals
Instruments.
National Instruments Corporation 4-45 VXI-MIO Series User Manual
available from National
Field Wiring and
Chapter
Calibration
This chapter discusses the calibration procedures for your VXI-MIO Series module. NI-DAQ and the VXI drivers include calibration functions for performing all of the steps in the calibration process.
Calibration refers to the process of minimizing measurement and output voltage errors by making small circuit adjustments. On the VXI-MIO Series modules, these adjustments take the form of writing values to onboard calibration DACs (CalDACs).
Some form of module calibration is required for all but the most forgiving applications. If you do not perform module calibration, your signals and measurements could have offset, gain, and linearity errors.
Three levels of calibration are available to you and described in this chapter. The first level is the fastest, easiest, and least accurate, whereas the last level is the slowest, most difficult, and most accurate.

Loading Calibration Constants

5
plug&play
instrument
Your VXI-MIO Series module is factory calibrated before shipment at approximately 25° C to the levels indicated in Appendix A,
Specifications
were written to the CalDACs to achieve calibration in the factory—are stored in the onboard nonvolatile memory (EEPROM). Because the CalDACs have no memory capability, they do not retain calibration information when the module is unpowered. Loading calibration constants refers to the process of loading the CalDACs with the values stored in the EEPROM. NI-DAQ, the VXI drivers, or your application software determine when this is necessary and do it automatically. If you are not using NI-DAQ, the VXI
plug&play
must load these values yourself.
In the EEPROM there is a user-modifiable calibration area in addition to the permanent factory calibration area. This means that you can load
National Instruments Corporation 5-1 VXI-MIO Series User Manual
. The associated calibration constants—the values that
plug&play
instrument drivers, or your application software, you
instrument
Chapter 5 Calibration
the CalDACs with values either from the original factory calibration or from a calibration that you subsequently performed.
This method of calibration is not very accurate because it does not take into account the fact that the module measurement and output voltage errors can vary with time and temperature. It is better to self-calibrate when the module is installed in the environment in which it will be used.

Self-Calibration

Your VXI-MIO Series module can measure and correct for almost all of its calibration-related errors without any external signal connections. Your National Instruments software provides a self-calibration method for you. This self-calibration process, which generally takes less than a minute, is the preferred method of assuring accuracy in your application. Initiate self-calibration to ensure that you minimize the effects of any offset, gain, and linearity drifts, particularly those due to warmup.
Immediately after self-calibration, the only significant residual calibration error could be gain error due to time or temperature drift of the onboard voltage reference. External calibration addresses this error, which is discussed in the following section. If you are interested primarily in relative measurements, you can ignore a small amount of gain error, and self-calibration should be sufficient.

External Calibration

Your VXI-MIO Series module has an onboard calibration reference to ensure the accuracy of self-calibration. Its specifications are listed in Appendix A, factory and stored in the EEPROM for subsequent self-calibrations. This voltage is stable enough for most applications, but if you are using your module at an extreme temperature or if the onboard reference has not been measured for a year or more, you may wish to externally calibrate your module.
An external calibration refers to calibrating your module with a known external reference rather than relying on the onboard reference. Redetermining the value of the onboard reference is part of this process and the results can be saved in the EEPROM, so you should not have to perform an external calibration very often. Externally calibrate your
VXI-MIO Series User Manual 5-2
Specifications
. The reference voltage is measured at the
National Instruments Corporation
Chapter 5 Calibration
module by calling the NI-DAQ or VXI calibration function.
To externally calibrate your module, be sure to use a very accurate external reference. The reference should be several times more accurate than the module itself. For example, to calibrate a 12-bit module, the external reference should be at least ±0.005% (±50 ppm) accurate. To calibrate a 16-bit module, the external reference should be at least
±
0.001% (±10 ppm) accurate.

Other Considerations

The CalDACs adjust the gain error of each analog output channel by adjusting the value of the reference voltage supplied to that channel. This calibration mechanism is designed to work only with the internal 10 V reference. Thus, in general, it is not possible to calibrate the analog output gain error when using an external reference. In this case, it is advisable to account for the nominal gain error of the analog output channel either in software or with external hardware. See Appendix A,
Specifications
plug&play
, for analog output gain error information.
instrument driver
National Instruments Corporation 5-3 VXI-MIO Series User Manual
Appendix
Specifications
This appendix lists the specifications of each module in the
VXI-MIO Series. These specifications are typical at 25° C unless
otherwise noted.

VXI-MIO-64E-1

Analog Input

Input Characteristics
Number of channels .......................... 64 single-ended or 32
Type of ADC..................................... Successive approximation
Resolution......................................... 12 bits, 1 in 4,096
Max sampling rate ............................. 1.25 MS/s guaranteed
A
differential (software selectable)
National Instruments Corporation A-1 VXI-MIO Series User Manual
Appendix A Specifications for VXI-MIO-64E-1
Input signal ranges................
Module Gain
(Software
Selectable)
Module Range
(Software Selectable)
Bipolar Unipolar
0.5
1
2
5
10
20
50
100
±
10 V
±
5 V
±
2.5 V
±
1 V
±
500 mV
±
250 mV
±
100 mV
±
50 mV
0 to 10 V
0 to 5 V
0 to 2 V
0 to 1 V
0 to 500 mV
0 to 200 mV
0 to 100 mV
Input coupling ....................................DC
Max working voltage
(signal + common mode).................Each input should remain within
±
11 V of ground
Overvoltage protection.......................±25 V powered on, ± 15 V
powered off
Inputs protected.......................... ACH<0..63>, AISENSE,
AISENSE2
FIFO buffer size................................. 8,192 S
Data transfers .....................................DMA, interrupts, programmed
I/O
Configuration memory size................ 512 words
VXI-MIO Series User Manual A-2
National Instruments Corporation
Appendix A Specifications for VXI-MIO-64E-1
Transfer Characteristics
Relative accuracy .............................±0.5 LSB typ dithered, ±1.5 LSB
max undithered
DNL..................................................±0.5 LSB typ, ±1.0 LSB max
No missing codes .............................. 12 bits, guaranteed
Offset error
Pregain error after calibration .....±12 µV max
Pregain error before calibration...±2.5 mV max
Postgain error after calibration ....±0.5 mV max
Postgain error before calibration.±100 mV max
Gain error (relative to calibration reference)
After calibration (gain = 1) .........±0.02% of reading max
Before calibration .......................±2.5% of reading max
Gain ≠ 1 with gain error
adjusted to 0 at gain = 1 .......±0.02% of reading max
Amplifier Characteristics
Input impedance
Normal powered on.....................100 GΩ in parallel with 100 pF
Powered off ................................1 kΩ min
Overload.....................................1 kΩ min
Input bias current ..............................±200 pA
Input offset current ............................±100 pA
CMRR, DC to 60 Hz
Gain = 0.5...................................95 dB
Gain = 1......................................100 dB
Gain ≥ 2......................................106 dB
National Instruments Corporation A-3 VXI-MIO Series User Manual
Appendix A Specifications for VXI-MIO-64E-1
Dynamic Characteristics
Bandwidth .........................
Settling time for
Small signal (-3 dB)
1.6 MHz
Gain
Large signal (1% THD)
1 MHz
Accuracy
full-scale step ....................
±
System noise (LSBrms)
(not including quantization).......
0.012%
(±0.5 LSB)
All
3 µs typ 5 µs max
Gain
0.5 to 20
50 0.3 0.6
100 0.5 0.7
±
0.024%
(±1 LSB)
2 µs typ 3 µs max
Noise,
dither off
0.15 0.5
Crosstalk............................................-70 dB, DC to 100 kHz
±
0.098%
(±4 LSB)
1.8 µs typ 2 µs max
Noise,
dither on
Stability
Recommended warm-up time.............15 min
Offset temperature coefficient
Pregain .......................................±5 µV/°C
Postgain ......................................±240 µV/°C
Gain temperature coefficient..............±20 ppm/°C
Onboard calibration reference
Level .......................................... 5.000 V (±0.5 mV) (actual value
Temperature coefficient ..............±0.6 ppm/°C max
Long-term stability.....................±6 ppm/
VXI-MIO Series User Manual A-4
stored in EEPROM)
1,000 h
National Instruments Corporation

Analog Output

Appendix A Specifications for VXI-MIO-64E-1
Output Characteristics
Number of channels .......................... 2 voltage
Resolution......................................... 12 bits, 1 in 4,096
Max update rate
FIFO mode waveform generation
Internally timed ...................1 MS/s per channel
All other cases ............................950 kS/s per channel
Type of DAC..................................... Double buffered, multiplying
FIFO buffer size ............................... 2,048 samples
Data transfers.................................... DMA, interrupts,
programmed I/O
Transfer Characteristics
Relative accuracy (INL)
After calibration..........................±0.3 LSB typ, ±0.5 LSB max
Before calibration .......................±4 LSB max
DNL
After calibration..........................±0.3 LSB typ, ±1.0 LSB max
Before calibration .......................±3 LSB max
Monotonicity ..................................... 12 bits, guaranteed after
calibration
Offset error
After calibration..........................±1.0 mV max
Before calibration .......................±200 mV max
Gain error (relative to internal reference)
After calibration..........................±0.01% of output max
Before calibration .......................±0.5% of output max
National Instruments Corporation A-5 VXI-MIO Series User Manual
Appendix A Specifications for VXI-MIO-64E-1
Gain error
(relative to external reference) ...........+0% to +0.5% of output max, not
Voltage Output
Ranges...............................................±5 V, 0 to 10 V, ±EXTREF,
Output coupling .................................DC
Output impedance..............................0.1 Ω max
Current drive......................................±5 mA max
Protection...........................................Short-circuit to ground
Power-on state ...................................0 V
External reference input
Range .........................................±11 V
Overvoltage protection ...............±25 V powered on, ±15 V
Input impedance ......................... 10 k
Bandwidth (-3 dB)...................... 1 MHz
adjustable
0 to EXTREF (software-selectable)
powered off
Dynamic Characteristics
Settling time for full-scale step ..........3 µs to ±0.5 LSB accuracy
Slew rate............................................ 20 V/µs
Noise .................................................200 µVrms, DC to 1 MHz
Glitch energy (at midscale transition)
Magnitude
Reglitching disabled.............±70 mV
Reglitching enabled .............±40 mV
Duration ..................................... 1.5 µs
Stability
Offset temperature coefficient............±50 µV/°C
Gain temperature coefficient
Internal reference........................±25 ppm/°C
External reference.......................±25 ppm/°C
VXI-MIO Series User Manual A-6
National Instruments Corporation
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